Linux clock framework development
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From: sashiko-bot@kernel.org
To: "Miquel Raynal" <miquel.raynal@bootlin.com>
Cc: devicetree@vger.kernel.org, conor+dt@kernel.org, robh@kernel.org,
	linux-clk@vger.kernel.org
Subject: Re: [PATCH v3 3/6] dt-bindings: clock: ma35d1: Add missing WDT/WWDT parent clocks
Date: Fri, 25 Sep 2026 14:55:10 +0000	[thread overview]
Message-ID: <20260925145510.94EAF1F000FF@smtp.kernel.org> (raw)
In-Reply-To: <20260925-perso-ma35d1-upstream-clk-v3-3-ffbae7e020a8@bootlin.com>

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] clk: nuvoton: ma35d1: missing MA35D1_CLK_COUNT increment causes latent OOB array write
--

commit fa4195c8a4eac6a0140746768ad2e5ab623b88e4
Author: Miquel Raynal <miquel.raynal@bootlin.com>

dt-bindings: clock: ma35d1: Add missing WDT/WWDT parent clocks

This commit adds PCLK3_DIV4096 and PCLK4_DIV4096 to the dt-bindings header
to describe the clock tree for WDT and WWDT muxes.

> diff --git a/include/dt-bindings/clock/nuvoton,ma35d1-clk.h b/include/dt-bindings/clock/nuvoton,ma35d1-clk.h
> index 2d6a44a7e55c4..764d837d6162a 100644
> --- a/include/dt-bindings/clock/nuvoton,ma35d1-clk.h
> +++ b/include/dt-bindings/clock/nuvoton,ma35d1-clk.h
> @@ -248,5 +248,7 @@
>  #define ADC_GATE	233
>  #define EADC_DIV	234
>  #define EADC_GATE	235
> +#define PCLK3_DIV4096	236
> +#define PCLK4_DIV4096	237

[Severity: High]
Does this introduction of clock IDs 236 and 237 require a corresponding
update to MA35D1_CLK_COUNT in the clock driver?

In drivers/clk/nuvoton/clk-ma35d1.c, MA35D1_CLK_COUNT is currently hardcoded
to 236:

drivers/clk/nuvoton/clk-ma35d1.c:
#define MA35D1_CLK_COUNT        236

The driver's ma35d1_clocks_probe() function uses this count to allocate the
hardware clock pointer array:

drivers/clk/nuvoton/clk-ma35d1.c:ma35d1_clocks_probe()
    ma35d1_hw_data = devm_kzalloc(dev,
                                  struct_size(ma35d1_hw_data, hws, MA35D1_CLK_COUNT),
                                  GFP_KERNEL);

If subsequent patches instantiate these new fixed factor clocks and write to
hws[PCLK3_DIV4096] or hws[PCLK4_DIV4096], it appears it will write out of
bounds into adjacent heap memory because the array only holds 236 elements
(indices 0 to 235).

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260925-perso-ma35d1-upstream-clk-v3-0-ffbae7e020a8@bootlin.com?part=3

  reply	other threads:[~2026-09-25 14:55 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-09-25 14:44 [PATCH v3 0/6] clk: nuvoton: ma35d1: Fix mux parenting and peripheral clock rates Miquel Raynal
2026-09-25 14:44 ` [PATCH v3 1/6] clk: nuvoton: ma35d1: Keep the clock count in the driver Miquel Raynal
2026-09-25 14:44 ` [PATCH v3 2/6] dt-bindings: clock: ma35d1: Drop CLK_MAX_IDX define Miquel Raynal
2026-09-25 14:44 ` [PATCH v3 3/6] dt-bindings: clock: ma35d1: Add missing WDT/WWDT parent clocks Miquel Raynal
2026-09-25 14:55   ` sashiko-bot [this message]
2026-09-25 14:44 ` [PATCH v3 4/6] clk: nuvoton: " Miquel Raynal
2026-09-25 14:57   ` sashiko-bot
2026-09-25 15:06     ` Miquel Raynal
2026-09-25 14:44 ` [PATCH v3 5/6] clk: nuvoton: ma35d1: Use clk_hw pointers as mux parents Miquel Raynal
2026-09-25 14:44 ` [PATCH v3 6/6] clk: nuvoton: ma35d1: Avoid possible error pointer dereferencing Miquel Raynal

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