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[60.250.196.139]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3a497edd76dsm3833931a91.7.2026.09.29.00.21.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Sep 2026 00:21:11 -0700 (PDT) From: Joey Lu To: sboyd@kernel.org Cc: ychuang3@nuvoton.com, schung@nuvoton.com, yclu4@nuvoton.com, bmasney+clk@redhat.com, jbrunet+clk@baylibre.com, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Joey Lu Subject: [PATCH 0/1] clk: nuvoton: ma35d1-divider: use direct formula instead of divider table Date: Tue, 29 Sep 2026 15:21:05 +0800 Message-ID: <20260929072106.175202-1-a0987203069@gmail.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The MA35D1 ADC clock divider register implements a simple closed-form relation, rate = parent_rate / (2 * (N + 1)), but the driver models it by building a clk_div_table with one entry per possible divider value (up to 2^width entries) and feeding it through the generic divider_recalc_rate()/divider_determine_rate()/divider_get_val() helpers. Replace the table with direct arithmetic in recalc_rate()/determine_rate()/ set_rate(), and drop the unused mask_bit mechanism, whose only call site passed a bitmask instead of a bit index, causing an out-of-range BIT() shift. Joey Lu (1): clk: nuvoton: ma35d1-divider: use direct formula instead of divider table drivers/clk/nuvoton/clk-ma35d1-divider.c | 73 +++++++++++------------- drivers/clk/nuvoton/clk-ma35d1.c | 2 +- drivers/clk/nuvoton/clk-ma35d1.h | 2 +- 3 files changed, 36 insertions(+), 41 deletions(-) -- 2.43.0