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[60.250.196.139]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2e6046feacdsm19997845ad.18.2026.10.07.23.43.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Oct 2026 23:43:28 -0700 (PDT) From: Joey Lu To: sboyd@kernel.org Cc: ychuang3@nuvoton.com, schung@nuvoton.com, yclu4@nuvoton.com, bmasney+clk@redhat.com, jbrunet+clk@baylibre.com, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Joey Lu Subject: [PATCH v2 0/1] clk: nuvoton: ma35d1-divider: use direct formula instead of divider table Date: Thu, 8 Oct 2026 14:43:06 +0800 Message-ID: <20261008064307.2757324-1-a0987203069@gmail.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The MA35D1 ADC clock divider register implements a simple closed-form relation, rate = parent_rate / (2 * (N + 1)), but the driver models it by building a clk_div_table with one entry per possible divider value (up to 2^width entries) and feeding it through the generic divider_recalc_rate()/divider_determine_rate()/divider_get_val() helpers. Replace the table with direct arithmetic in recalc_rate()/determine_rate()/ set_rate(), and drop the unused mask_bit mechanism, whose only call site passed a bitmask instead of a bit index, causing an out-of-range BIT() shift. Changes in v2 (addressing the Sashiko AI review of v1): - Fix a possible division by zero: 2 * rate in determine_rate() and set_rate() could overflow for very large requested rates, making the divisor zero. Rates above parent_rate / 2 now short-circuit to a divider of 1 before the multiplication. - Fix the mismatch between determine_rate() and set_rate(): both used a ceiling to pick the divider, yet determine_rate() reported a closest-rounded rate, so set_rate() could program a different divider than the one promised. Both now use closest rounding, as the original CLK_DIVIDER_ROUND_CLOSEST code did, via a single shared helper (ma35d1_clkdiv_get_val()) that also clamps the divider to its valid range. - Not changed: min_rate/max_rate are not checked in the driver, since the clk core already applies them and the previous divider_determine_rate() based code did not either. Joey Lu (1): clk: nuvoton: ma35d1-divider: use direct formula instead of divider table drivers/clk/nuvoton/clk-ma35d1-divider.c | 79 ++++++++++++------------ drivers/clk/nuvoton/clk-ma35d1.c | 2 +- drivers/clk/nuvoton/clk-ma35d1.h | 2 +- 3 files changed, 42 insertions(+), 41 deletions(-) -- 2.43.0