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[88.207.14.234]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4a35a00e1b0sm152200695e9.3.2026.10.26.05.09.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 26 Oct 2026 05:09:33 -0700 (PDT) From: Robert Marko To: andersson@kernel.org, abelvesa@kernel.org, sboyd@kernel.org, bmasney+clk@redhat.com, jbrunet+clk@baylibre.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, konradybcio@kernel.org, taniya.das@oss.qualcomm.com, ansuelsmth@gmail.com, john@phrozen.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Robert Marko Subject: [PATCH v2 3/4] clk: qcom: gcc-ipq8074: Align CMN PLL inputs with binding Date: Mon, 26 Oct 2026 13:08:14 +0100 Message-ID: <20261026120920.1667982-3-robimarko@gmail.com> X-Mailer: git-send-email 2.56.0 In-Reply-To: <20261026120920.1667982-1-robimarko@gmail.com> References: <20261026120920.1667982-1-robimarko@gmail.com> X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The GCC binding names the CMN PLL inputs bias_pll_cc and bias_pll_nss_noc. Use those names as fw_name so GCC resolves the clocks through DT references. Keep the existing .name values as fallbacks for older device trees without these optional inputs. Signed-off-by: Robert Marko --- Changes in v2: - New patch to align GCC parent lookups with the binding input names. drivers/clk/qcom/gcc-ipq8074.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/clk/qcom/gcc-ipq8074.c b/drivers/clk/qcom/gcc-ipq8074.c index 1329ea28d703..68c080d49154 100644 --- a/drivers/clk/qcom/gcc-ipq8074.c +++ b/drivers/clk/qcom/gcc-ipq8074.c @@ -1132,7 +1132,7 @@ static const struct freq_tbl ftbl_nss_noc_bfdcd_clk_src[] = { static const struct clk_parent_data gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2[] = { { .fw_name = "xo", .name = "xo" }, - { .fw_name = "bias_pll_nss_noc_clk", .name = "bias_pll_nss_noc_clk" }, + { .fw_name = "bias_pll_nss_noc", .name = "bias_pll_nss_noc_clk" }, { .hw = &gpll0.clkr.hw }, { .hw = &gpll2.clkr.hw }, }; @@ -1357,7 +1357,7 @@ static const struct freq_tbl ftbl_nss_ppe_clk_src[] = { static const struct clk_parent_data gcc_xo_bias_gpll0_gpll4_nss_ubi32[] = { { .fw_name = "xo", .name = "xo" }, - { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" }, + { .fw_name = "bias_pll_cc", .name = "bias_pll_cc_clk" }, { .hw = &gpll0.clkr.hw }, { .hw = &gpll4.clkr.hw }, { .hw = &nss_crypto_pll.clkr.hw }, @@ -1411,7 +1411,7 @@ static const struct clk_parent_data gcc_xo_uniphy0_rx_tx_ubi32_bias[] = { { .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" }, { .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" }, { .hw = &ubi32_pll.clkr.hw }, - { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" }, + { .fw_name = "bias_pll_cc", .name = "bias_pll_cc_clk" }, }; static const struct parent_map gcc_xo_uniphy0_rx_tx_ubi32_bias_map[] = { @@ -1463,7 +1463,7 @@ static const struct clk_parent_data gcc_xo_uniphy0_tx_rx_ubi32_bias[] = { { .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" }, { .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" }, { .hw = &ubi32_pll.clkr.hw }, - { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" }, + { .fw_name = "bias_pll_cc", .name = "bias_pll_cc_clk" }, }; static const struct parent_map gcc_xo_uniphy0_tx_rx_ubi32_bias_map[] = { @@ -1704,7 +1704,7 @@ static const struct clk_parent_data gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bia { .fw_name = "uniphy1_gcc_rx_clk", .name = "uniphy1_gcc_rx_clk" }, { .fw_name = "uniphy1_gcc_tx_clk", .name = "uniphy1_gcc_tx_clk" }, { .hw = &ubi32_pll.clkr.hw }, - { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" }, + { .fw_name = "bias_pll_cc", .name = "bias_pll_cc_clk" }, }; static const struct parent_map @@ -1774,7 +1774,7 @@ static const struct clk_parent_data gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bia { .fw_name = "uniphy1_gcc_tx_clk", .name = "uniphy1_gcc_tx_clk" }, { .fw_name = "uniphy1_gcc_rx_clk", .name = "uniphy1_gcc_rx_clk" }, { .hw = &ubi32_pll.clkr.hw }, - { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" }, + { .fw_name = "bias_pll_cc", .name = "bias_pll_cc_clk" }, }; static const struct parent_map @@ -1842,7 +1842,7 @@ static const struct clk_parent_data gcc_xo_uniphy2_rx_tx_ubi32_bias[] = { { .fw_name = "uniphy2_gcc_rx_clk", .name = "uniphy2_gcc_rx_clk" }, { .fw_name = "uniphy2_gcc_tx_clk", .name = "uniphy2_gcc_tx_clk" }, { .hw = &ubi32_pll.clkr.hw }, - { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" }, + { .fw_name = "bias_pll_cc", .name = "bias_pll_cc_clk" }, }; static const struct parent_map gcc_xo_uniphy2_rx_tx_ubi32_bias_map[] = { @@ -1907,7 +1907,7 @@ static const struct clk_parent_data gcc_xo_uniphy2_tx_rx_ubi32_bias[] = { { .fw_name = "uniphy2_gcc_tx_clk", .name = "uniphy2_gcc_tx_clk" }, { .fw_name = "uniphy2_gcc_rx_clk", .name = "uniphy2_gcc_rx_clk" }, { .hw = &ubi32_pll.clkr.hw }, - { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" }, + { .fw_name = "bias_pll_cc", .name = "bias_pll_cc_clk" }, }; static const struct parent_map gcc_xo_uniphy2_tx_rx_ubi32_bias_map[] = { -- 2.56.0