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Thu, 29 Oct 2026 00:03:23 -0700 (PDT) Received: from Sobhana.localdomain ([152.58.200.233]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-36a2398fa4csm16955443eec.24.2026.10.29.00.03.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Oct 2026 00:03:22 -0700 (PDT) From: Sreeshankar K Subject: [PATCH RESEND v11 0/5] Add initial support for Qualcomm SM7250 SoC Date: Thu, 29 Oct 2026 07:02:57 +0000 Message-Id: <20261029-master-v11-0-2c29e382162c@gmail.com> X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-B4-Tracking: v=1; b=H4sIAKHv4moC/6tWKk4tykwtVrJSqFYqSi3LLM7MzwNyDA11FJSSM xLz0lN1M1OAAkpGBkZmhgZGlrq5icUlqUW6iQbGFuZmFhaWBiZmSkDFBUWpaZkVYJOilYJcg13 9XJRia2sBw02Md2EAAAA= To: Bjorn Andersson , Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Danila Tikhonov , David Wronek , Abel Vesa , Robert Marko , Guru Das Srinagesh , "Rafael J. Wysocki" , Viresh Kumar , Manivannan Sadhasivam Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Sreeshankar K , Krzysztof Kozlowski X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1793257394; l=6160; i=sreeshankar0910@gmail.com; s=20261029; h=from:subject:message-id; bh=pMaV3p1wY/hJ19yVZNVUSH6boZE8iznCu8d5b6Dyemw=; b=LwPehCJnihIRvMueFhLEqIdojCA/JwtVKPuYsUDw522On0R9tTY1rSkXbTjqDNPHDjGf1RiWG uPX3Hqn5vvjCxMd4yqS4Xi2FRAh/SYDQ16/HLu8FoVDnd8Q38+YLd+P X-Developer-Key: i=sreeshankar0910@gmail.com; a=ed25519; pk=CGSHduvtn2hwLCNRXRc9s/fh6X8PH/zNdp08zC8hOuQ= This patchset introduces foundational upstream support for the Qualcomm SM7250 SoC (internally codenamed Lito). SM7250 is an ARMv8.2-A platform manufactured on a 7nm process, featuring an octa-core Kryo 475 CPU configuration (1x Prime Cortex-A76, 1x Gold Cortex-A76, and 6x Silver Cortex-A55) and Adreno 620 GPU. This patchset is organized as follows: > Document relevant device tree bindings (SoC ID, Kryo 475 CPUs, SCM, PDC, RPMh clocks/power domains, GCC and cpufreq hardware). > Add driver support for SM7250 in socinfo, rpmh-clk, rpmhpd, and GCC. > Add the base SoC DTSI (sm7250.dtsi) defining the cpus, PSCI, interrupt controllers, clock providers, power domains, and reserved memory. >-----------------------------------------------------------------------------< Merged patches: dt-bindings: arm: qcom,ids: Add SoC ID for SM7250 soc: qcom: socinfo: Add SM7250 SoC ID dt-bindings: clock: qcom,rpmhcc: Document RPMHCC compatible clk: qcom: rpmh: Add SM7250 rpmh clocks dt-bindings: power: qcom,rpmhpd: Document RPMh power domain for SM7250 pmdomain: qcom: rpmhpd: Add RPMh power domains dt-bindings: arm: cpus: Document Kryo 475 CPUs dt-bindings: interrupt-controller: qcom,pdc: Document SM7250 PDC Pending patches: dt-bindings: clock: Add SM7250 global clock controller clk: qcom: Add Global Clock Controller (GCC) driver for SM7250 dt-bindings: firmware: qcom,scm: Document SM7250 SCM dt-bindings: cpufreq: qcom-hw: Document SM7250 cpufreq hardware arm64: dts: qcom: Add SM7250 devicetree file >------------------------------------------------------------------------------< Previous v11: https://lore.kernel.org/linux-arm-msm/20261016042432.824-1-sreeshankar0910@gmail.com/T/#t Changelog [v11]: [PATCH v11 2/5] clk: qcom: Add Global Clock Controller (GCC) driver > Drop hw_ctl clock branches > Populate default values for GDSCs Link [v10]: https://lore.kernel.org/linux-arm-msm/20261015051926.13752-1-sreeshankar0910@gmail.com/T/#t Changelog [v10]: [PATCH v10 2/6] clk: qcom: Add Global Clock Controller (GCC) driver > Update .halt_check and .ops are per the review. Link [v9]: https://lore.kernel.org/linux-arm-msm/20260901092447.3028-1-sreeshankar0910@gmail.com/T/#t Changelog [v9]: [PATCH v9 04/13]: clk: qcom: Add Global Clock Controller (GCC) driver for SM7250 > Make all clk_init_data instances const across the driver. Link [v8]: https://lore.kernel.org/linux-arm-msm/20260901070717.20513-1-sreeshankar0910@gmail.com/T/#t Changelog [v8]: Same as v7. Resending the full patchset as v8 due to a transmission interruption during v7. Link [v7]: https://lore.kernel.org/linux-arm-msm/20260901064357.20055-1-sreeshankar0910@gmail.com/T/#t Changelog [v7]: [PATCH v7 04/13]: clk: qcom: Add Global Clock Controller (GCC) driver for SM7250 > Fixed missing (struct device *dev) in gcc_sm7250_clk_regs_configure Link [v6]: https://lore.kernel.org/linux-arm-msm/20260824150156.1310-1-sreeshankar0910@gmail.com/T/#t Changelog [v6]: [PATCH v6 04/13]: clk: qcom: Add Global Clock Controller (GCC) driver for SM7250 > Make all clk_init_data instances const across the driver. Link [v5]: https://lore.kernel.org/linux-arm-msm/20260824130437.2771-1-sreeshankar0910@gmail.com/T/#t Changelog [v5]: [PATCH v5 13/13]: arm64: dts: qcom: Add SM7250 devicetree file > Reformat multi-entry phandle lists (domain-idle-states) to '<&a>, <&b>'. > Reformat multi-entry tuples and string lists (qcom,pdc-ranges, qcom,tcs-config, reg-names) to one item per line. > Enable QUPv3 wrapper globally by dropping 'status = "disabled"'. > Move compatible property to first. > Remove clock-frequency property for timer. Link [v4]: https://lore.kernel.org/linux-arm-msm/20260821154030.2514-1-sreeshankar0910@gmail.com/T/#t Changelog [v4]: [PATCH v4 04/13] clk: qcom: Add Global Clock Controller (GCC) driver for SM7250 > Update .fw_name with .index [PATCH v4 13/13] arm64: dts: qcom: Add SM7250 devicetree file > Added missing capacity-dmips-mhz and dynamic-power-coefficient for cpu@300 > Added power-domains for cpus and apps_rsc Link [v3]: https://lore.kernel.org/linux-arm-msm/20260821081125.4522-1-sreeshankar0910@gmail.com/T/#t Changelog [v3]: [PATCH v3 04/13] clk: qcom: Add Global Clock Controller (GCC) driver for SM7250 > Updated the way of registering critical clocks. > Made some more clock critical. GCC_VIDEO_XO_CLK GCC_CAMERA_XO_CLK GCC_DISP_XO_CLK GCC_NPU_CFG_AHB_CLK GCC_CPUSS_AHB_CLK GCC_NPU_BWMON_CFG_AHB_CLK These clocks are flagged as critical in gcc-lito.c Link [v2]: https://lore.kernel.org/linux-arm-msm/20260819152545.3934-1-sreeshankar0910@gmail.com/T/#t Changelog [v2]: [PATCH v2 12/13] dt-bindings: cpufreq: qcom-hw: Document SM7250 cpufreq hardware [PATCH v2 13/13] arm64: dts: qcom: Add SM7250 devicetree file > Added SM7250 cpufreq hardware Link [v1]: https://lore.kernel.org/linux-arm-msm/20260818080754.4362-1-sreeshankar0910@gmail.com/T/#t Signed-off-by: Sreeshankar K --- Sreeshankar K (5): dt-bindings: clock: Add SM7250 global clock controller clk: qcom: Add Global Clock Controller (GCC) driver for SM7250 dt-bindings: firmware: qcom,scm: Document SM7250 SCM dt-bindings: cpufreq: qcom-hw: Document SM7250 cpufreq hardware arm64: dts: qcom: Add SM7250 devicetree file .../devicetree/bindings/clock/qcom,sm6375-gcc.yaml | 4 +- .../bindings/cpufreq/cpufreq-qcom-hw.yaml | 1 + .../devicetree/bindings/firmware/qcom,scm.yaml | 1 + arch/arm64/boot/dts/qcom/sm7250.dtsi | 771 +++++++ drivers/clk/qcom/Kconfig | 10 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/gcc-sm7250.c | 2286 ++++++++++++++++++++ include/dt-bindings/clock/qcom,sm7250-gcc.h | 163 ++ 8 files changed, 3236 insertions(+), 1 deletion(-) --- base-commit: f5491c67aeee4a68dd2b218e2f4c5baa7786c566 change-id: 20261029-master-a03876889046 Best regards, -- Sreeshankar K