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Wed, 04 Nov 2026 08:47:34 -0800 (PST) Received: from Sobhana.localdomain ([157.51.207.207]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-1b245c57430sm10839666c88.18.2026.11.04.08.47.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Nov 2026 08:47:34 -0800 (PST) From: Sreeshankar K Date: Wed, 04 Nov 2026 16:46:37 +0000 Subject: [PATCH v13 5/8] thermal/qcom/lmh: Add support for Qualcomm SM7250 X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20261104-master-v13-5-355b65c6f764@gmail.com> References: <20261104-master-v13-0-355b65c6f764@gmail.com> In-Reply-To: <20261104-master-v13-0-355b65c6f764@gmail.com> To: Bjorn Andersson , Abel Vesa , Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Taniya Das , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Konrad Dybcio , Robert Marko , Guru Das Srinagesh , Viresh Kumar , Manivannan Sadhasivam Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Sreeshankar K X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1793810796; l=1940; i=sreeshankar0910@gmail.com; s=20261029; h=from:subject:message-id; bh=CFhfNpAR/hsUoYP+FpbYSd22wi56uWW4Vnq2ksqBL70=; b=AHV5arLvLuQqAMLn4qDczJBTrUzBqyZHmum7vYKn9NSDkm/FNjxIHZSp/eoAIkIM4IVrypzxN KTUVsrytn6yAlacDB88TgXiRGdRNT7Cl5IXO6NA6AoS0kuPs8fkybxB X-Developer-Key: i=sreeshankar0910@gmail.com; a=ed25519; pk=CGSHduvtn2hwLCNRXRc9s/fh6X8PH/zNdp08zC8hOuQ= Qualcomm SM7250 features an asymmetric 6+2 core topology where the Silver cluster consists of CPU 0 to CPU 5 and the Gold/Prime cluster starts at logical CPU 6. Add the SoC match data defining the CPU-to-node mapping (CPU 0 to LMH_CLUSTER0_NODE_ID, and CPU 6 to LMH_CLUSTER1_NODE_ID), and register the "qcom,sm7250-lmh" compatible string so both LMh cluster instances can probe and register their respective DCVSh interrupt domains. Signed-off-by: Sreeshankar K --- drivers/thermal/qcom/lmh.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/thermal/qcom/lmh.c b/drivers/thermal/qcom/lmh.c index ef49ed1c6..ad6d34b8e 100644 --- a/drivers/thermal/qcom/lmh.c +++ b/drivers/thermal/qcom/lmh.c @@ -110,12 +110,22 @@ static const struct qcom_lmh_node_map sdm845_lmh_map[] = { { .cpu_id = 4, .node_id = LMH_CLUSTER1_NODE_ID }, }; +static const struct qcom_lmh_node_map sm7250_lmh_map[] = { + { .cpu_id = 0, .node_id = LMH_CLUSTER0_NODE_ID }, + { .cpu_id = 6, .node_id = LMH_CLUSTER1_NODE_ID }, +}; + static const struct qcom_lmh_soc_data sdm845_lmh_data = { .map = sdm845_lmh_map, .num_nodes = ARRAY_SIZE(sdm845_lmh_map), .flags = LMH_ENABLE_ALGOS, }; +static const struct qcom_lmh_soc_data sm7250_lmh_data = { + .map = sm7250_lmh_map, + .num_nodes = ARRAY_SIZE(sm7250_lmh_map), +}; + static const struct qcom_lmh_soc_data sm8150_lmh_data = { .map = sdm845_lmh_map, .num_nodes = ARRAY_SIZE(sdm845_lmh_map), @@ -124,6 +134,7 @@ static const struct qcom_lmh_soc_data sm8150_lmh_data = { static const struct of_device_id lmh_table[] = { { .compatible = "qcom,sc8180x-lmh", .data = &sm8150_lmh_data }, { .compatible = "qcom,sdm845-lmh", .data = &sdm845_lmh_data }, + { .compatible = "qcom,sm7250-lmh", .data = &sm7250_lmh_data }, { .compatible = "qcom,sm8150-lmh", .data = &sm8150_lmh_data }, {} }; -- 2.43.0