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[82.69.66.36]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4b795038782sm2465185e9.3.2026.11.06.10.00.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Nov 2026 10:00:31 -0800 (PST) Date: Fri, 6 Nov 2026 18:00:29 +0000 From: David Laight To: Jerome Brunet Cc: Brian Masney , Carlo Caione , Stephen Boyd , Brian Masney , Jerome Brunet , Brian Norris , Brian Norris , Sebastian Reichel , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Stephen Boyd Subject: Re: [PATCH 1/2] clk: divider: Fix the divisor for rates above 4.29 GHz Message-ID: <20261106180029.05452269@pumpkin> In-Reply-To: <179398031041.2573818.13317727784501684521.b4-reply@b4> References: <20261102-upstream-clk-divider-large-rates-v1-0-eb17035bfad2@baylibre.com> <20261102-upstream-clk-divider-large-rates-v1-1-eb17035bfad2@baylibre.com> <179382912410.620422.14715602424648962218.b4-review@b4> <179398031041.2573818.13317727784501684521.b4-reply@b4> X-Mailer: Claws Mail 4.1.1 (GTK 3.24.38; arm-unknown-linux-gnueabihf) X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit On Fri, 06 Nov 2026 16:51:50 +0100 Jerome Brunet wrote: > On 2026-11-04 16:52:04-05:00, Brian Masney wrote: > > > DIV_ROUND_UP_ULL() takes a 32-bit divisor, so on 64-bit platforms a > > > requested rate above 4.29 GHz is truncated. A divider fed by a 5.94 GHz > > > PLL then computes a divisor of 7, not 1, for 5.94 GHz. > > > > > > Use DIV64_U64_ROUND_UP(), which takes a 64-bit divisor. > > > > > > Fixes: 9556f9dad8f5 ("clk: divider: handle integer overflow when dividing large clock rates") > > > Signed-off-by: Sebastian Reichel > > > Signed-off-by: Carlo Caione > > > > Reviewed-by: Brian Masney > > > > Since this is a core change to the framework, I'd also like to see what > > Jerome thinks before we merge this. > > I've had not problem with the change initially but then the AI told me that > it brings back the overflow problem fixed by 9556f9dad8f5. > > At first I thought it was crazy because it would mean parent_rate + rate is > more than 18 billion GHz ... BUT, a common way to ask for the maximum rate a > clock supports is clk_round_rate(clk, ULONG_MAX). This could trigger the overflow > and there are instance of this in the kernel right now. > > A way to make the calculation without the overflow could be: > parent_rate / rate + (parent_rate % rate ? 1 : 0) > You just want: parent_rate ? (parent_rate - 1) / rate + 1 : 0 it is even likely here that you can assume parent_rate in non-zero. David