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Mon, 09 Nov 2026 20:31:41 -0800 (PST) Received: from eldorado ([2600:8802:b00:1f88::287]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-375212e9d78sm3340996eec.25.2026.11.09.20.31.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Nov 2026 20:31:40 -0800 (PST) From: Florian Fainelli To: linux-mips@vger.kernel.org Cc: =?UTF-8?q?=E5=91=A8=E7=90=B0=E6=9D=B0=20=28Zhou=20Yanjie=29?= , Florian Fainelli , Thomas Bogendoerfer , Paul Burton , Paul Cercueil , Stephen Boyd , Brian Masney , Jerome Brunet , Jiaxun Yang , linux-kernel@vger.kernel.org (open list), linux-clk@vger.kernel.org (open list:COMMON CLK FRAMEWORK), hns@goldelico.com, paul@boddie.org.uk Subject: [PATCH v2 3/3] MIPS: CI20: Enable SMP with two CPUs Date: Mon, 9 Nov 2026 20:31:31 -0800 Message-ID: <20261110043131.1985993-4-f.fainelli@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261110043131.1985993-1-f.fainelli@gmail.com> References: <20261110043131.1985993-1-f.fainelli@gmail.com> X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit From: 周琰杰 (Zhou Yanjie) Enable both JZ4780 cores now that the generic Ingenic platform provides secondary CPU reset and mailbox support. The existing device tree already reserves TCU channels for both per-CPU clock events. Link: https://lists.openwall.net/linux-kernel/2020/05/19/739 Signed-off-by: 周琰杰 (Zhou Yanjie) Signed-off-by: Florian Fainelli --- arch/mips/configs/ci20_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/mips/configs/ci20_defconfig b/arch/mips/configs/ci20_defconfig index 90536cab417e..09d65094b1bd 100644 --- a/arch/mips/configs/ci20_defconfig +++ b/arch/mips/configs/ci20_defconfig @@ -22,6 +22,8 @@ CONFIG_EXPERT=y CONFIG_MACH_INGENIC_SOC=y CONFIG_JZ4780_CI20=y CONFIG_HIGHMEM=y +CONFIG_SMP=y +CONFIG_NR_CPUS=2 CONFIG_HZ_100=y # CONFIG_SUSPEND is not set # CONFIG_SECCOMP is not set -- 2.53.0