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Wed, 11 Nov 2026 13:57:44 -0800 (PST) Received: from ryzen.lan ([2601:644:8000:37f::e34]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3b197ce556dsm965429a91.6.2026.11.11.13.57.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Nov 2026 13:57:44 -0800 (PST) From: Rosen Penev To: Thomas Bogendoerfer , Stephen Boyd , Brian Masney , Jerome Brunet , Alban Bedel , Antony Pavlov , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v3 5/7] dt-bindings: clock: ath79: add the UART1 and PCIe PLL clocks Date: Wed, 11 Nov 2026 13:57:27 -0800 Message-ID: <20261111215729.10683-6-rosenp@gmail.com> X-Mailer: git-send-email 2.56.1 In-Reply-To: <20261111215729.10683-1-rosenp@gmail.com> References: <20261111215729.10683-1-rosenp@gmail.com> X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Add IDs for two more clocks: The second, high speed UART of AR934x, which is compatible with the qca,ar9330-uart one, can run from a 100 MHz clock instead of the reference clock. AR724x, AR934x, QCA953x, QCA955x and QCA956x have a PCIe PLL, which the PCIe host controller nodes need to reference. Signed-off-by: Rosen Penev --- include/dt-bindings/clock/ath79-clk.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/dt-bindings/clock/ath79-clk.h b/include/dt-bindings/clock/ath79-clk.h index 27e31452544d..57d966ae9722 100644 --- a/include/dt-bindings/clock/ath79-clk.h +++ b/include/dt-bindings/clock/ath79-clk.h @@ -11,5 +11,7 @@ #define ATH79_CLK_AHB 2 #define ATH79_CLK_REF 3 #define ATH79_CLK_MDIO 4 +#define ATH79_CLK_UART1 5 +#define ATH79_CLK_PCIE 6 #endif /* __DT_BINDINGS_ATH79_CLK_H */ -- 2.56.0