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[82.149.12.148]) by smtp.gmail.com with ESMTPSA id e2-20020adfef02000000b00336644c400bsm9770223wro.64.2023.12.20.07.12.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Dec 2023 07:12:45 -0800 (PST) From: Jernej =?utf-8?B?xaBrcmFiZWM=?= To: Frank Oltmanns Cc: Michael Turquette , Stephen Boyd , Chen-Yu Tsai , Samuel Holland , Guido =?ISO-8859-1?Q?G=FCnther?= , Purism Kernel Team , Ondrej Jirman , Neil Armstrong , Jessica Zhang , Sam Ravnborg , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org Subject: Re: [PATCH 4/5] clk: sunxi-ng: a64: Add constraints on PLL-VIDEO0's n/m ratio Date: Wed, 20 Dec 2023 16:12:42 +0100 Message-ID: <2174554.Mh6RI2rZIc@jernej-laptop> In-Reply-To: <87il4t9wi1.fsf@oltmanns.dev> References: <20231218-pinephone-pll-fixes-v1-0-e238b6ed6dc1@oltmanns.dev> <13411739.uLZWGnKmhe@jernej-laptop> <87il4t9wi1.fsf@oltmanns.dev> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="UTF-8" Dne sreda, 20. december 2023 ob 08:09:28 CET je Frank Oltmanns napisal(a): >=20 > On 2023-12-19 at 17:54:19 +0100, Jernej =C5=A0krabec wrote: > > Dne ponedeljek, 18. december 2023 ob 14:35:22 CET je Frank Oltmanns nap= isal(a): > >> The Allwinner A64 manual lists the following constraint for the > >> PLL-VIDEO0 clock: 8 <=3D N/M <=3D 25 > >> > >> Use this constraint. > >> > >> Signed-off-by: Frank Oltmanns > >> --- > >> drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 8 ++++++-- > >> 1 file changed, 6 insertions(+), 2 deletions(-) > >> > >> diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi= =2Dng/ccu-sun50i-a64.c > >> index c034ac027d1c..75d839da446c 100644 > >> --- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c > >> +++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c > >> @@ -68,7 +68,8 @@ static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_bas= e_clk, "pll-audio-base", > >> BIT(28), /* lock */ > >> CLK_SET_RATE_UNGATE); > >> > >> -static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX_CLOSEST(pll_video0_cl= k, "pll-video0", > >> +static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX_FEAT_NM_RATIO(pll_vid= eo0_clk, > >> + "pll-video0", > >> "osc24M", 0x010, > >> 192000000, /* Minimum rate */ > >> 1008000000, /* Maximum rate */ > >> @@ -80,7 +81,10 @@ static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX_CLO= SEST(pll_video0_clk, "pll-vid > >> 297000000, /* frac rate 1 */ > >> BIT(31), /* gate */ > >> BIT(28), /* lock */ > >> - CLK_SET_RATE_UNGATE); > >> + CLK_SET_RATE_UNGATE, > >> + CCU_FEATURE_FRACTIONAL | > >> + CCU_FEATURE_CLOSEST_RATE, > > > > Above flags are unrelated change, put them in new patch if needed. >=20 > You might notice that I am using a new macro for initializing the > pll_video0_clk struct: > New: SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX_FEAT_NM_RATIO > Old: SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX_CLOSEST >=20 > Setting the two CCU_FEATURE flags is part of the old initialization > macro. >=20 > I'll add SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX_NM_RATIO_CLOSEST which > hopefully resolves the confusion. I'm in doubt if we need so many macros. How many users of these macro we'll= have? I see that R40 SoC would also need same ratio limits, but other that that, = none? Best regards, Jernej >=20 > Thanks, > Frank >=20 > > > > Best regards, > > Jernej > > > >> + 8, 25); /* min/max nm ratio */ > >> > >> static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve", > >> "osc24M", 0x018, > >> > >> >=20