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([2a01:e0a:106d:1080:3caf:d840:c911:29a9]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49d20fc23fcsm99287025e9.3.2026.09.10.00.13.26 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 10 Sep 2026 00:13:28 -0700 (PDT) Message-ID: <22576e60-df08-4994-a7ce-130d5bae80d9@linaro.org> Date: Thu, 10 Sep 2026 09:13:26 +0200 Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird From: Neil Armstrong Reply-To: Neil Armstrong Subject: Re: [PATCH v2 3/4] arm64: dts: amlogic: t7: add the pipeline clock to the MMC controllers To: Lucas Tanure , Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jerome Brunet , Kevin Hilman , Martin Blumenstingl , Stephen Boyd Cc: Brian Masney , Chuan Liu , Jian Hu , Ronald Claveau , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260905153234.133217-1-tanure@linux.com> <20260905153234.133217-4-tanure@linux.com> Content-Language: en-US, fr Autocrypt: addr=neil.armstrong@linaro.org; keydata= xsBNBE1ZBs8BCAD78xVLsXPwV/2qQx2FaO/7mhWL0Qodw8UcQJnkrWmgTFRobtTWxuRx8WWP GTjuhvbleoQ5Cxjr+v+1ARGCH46MxFP5DwauzPekwJUD5QKZlaw/bURTLmS2id5wWi3lqVH4 BVF2WzvGyyeV1o4RTCYDnZ9VLLylJ9bneEaIs/7cjCEbipGGFlfIML3sfqnIvMAxIMZrvcl9 qPV2k+KQ7q+aXavU5W+yLNn7QtXUB530Zlk/d2ETgzQ5FLYYnUDAaRl+8JUTjc0CNOTpCeik 80TZcE6f8M76Xa6yU8VcNko94Ck7iB4vj70q76P/J7kt98hklrr85/3NU3oti3nrIHmHABEB AAHNKk5laWwgQXJtc3Ryb25nIDxuZWlsLmFybXN0cm9uZ0BsaW5hcm8ub3JnPsLAkQQTAQoA OwIbIwULCQgHAwUVCgkICwUWAgMBAAIeAQIXgBYhBInsPQWERiF0UPIoSBaat7Gkz/iuBQJk Q5wSAhkBAAoJEBaat7Gkz/iuyhMIANiD94qDtUTJRfEW6GwXmtKWwl/mvqQtaTtZID2dos04 YqBbshiJbejgVJjy+HODcNUIKBB3PSLaln4ltdsV73SBcwUNdzebfKspAQunCM22Mn6FBIxQ GizsMLcP/0FX4en9NaKGfK6ZdKK6kN1GR9YffMJd2P08EO8mHowmSRe/ExAODhAs9W7XXExw UNCY4pVJyRPpEhv373vvff60bHxc1k/FF9WaPscMt7hlkbFLUs85kHtQAmr8pV5Hy9ezsSRa GzJmiVclkPc2BY592IGBXRDQ38urXeM4nfhhvqA50b/nAEXc6FzqgXqDkEIwR66/Gbp0t3+r yQzpKRyQif3OwE0ETVkGzwEIALyKDN/OGURaHBVzwjgYq+ZtifvekdrSNl8TIDH8g1xicBYp QTbPn6bbSZbdvfeQPNCcD4/EhXZuhQXMcoJsQQQnO4vwVULmPGgtGf8PVc7dxKOeta+qUh6+ SRh3vIcAUFHDT3f/Zdspz+e2E0hPV2hiSvICLk11qO6cyJE13zeNFoeY3ggrKY+IzbFomIZY 4yG6xI99NIPEVE9lNBXBKIlewIyVlkOaYvJWSV+p5gdJXOvScNN1epm5YHmf9aE2ZjnqZGoM Mtsyw18YoX9BqMFInxqYQQ3j/HpVgTSvmo5ea5qQDDUaCsaTf8UeDcwYOtgI8iL4oHcsGtUX oUk33HEAEQEAAcLAXwQYAQIACQUCTVkGzwIbDAAKCRAWmrexpM/4rrXiB/sGbkQ6itMrAIfn M7IbRuiSZS1unlySUVYu3SD6YBYnNi3G5EpbwfBNuT3H8//rVvtOFK4OD8cRYkxXRQmTvqa3 3eDIHu/zr1HMKErm+2SD6PO9umRef8V82o2oaCLvf4WeIssFjwB0b6a12opuRP7yo3E3gTCS KmbUuLv1CtxKQF+fUV1cVaTPMyT25Od+RC1K+iOR0F54oUJvJeq7fUzbn/KdlhA8XPGzwGRy 4zcsPWvwnXgfe5tk680fEKZVwOZKIEuJC3v+/yZpQzDvGYJvbyix0lHnrCzq43WefRHI5XTT QbM0WUIBIcGmq38+OgUsMYu4NzLu7uZFAcmp6h8g Organization: Linaro In-Reply-To: <20260905153234.133217-4-tanure@linux.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 9/5/26 17:32, Lucas Tanure wrote: > The SD/eMMC controllers reach the DRAM through a pipeline stage that > the hardware design inserts in the bus path to the NIC_MATRIX fabric, > clocked by CLKID_SYS_AMPIPE_NAND. When that clock is disabled, a > controller that starts a DMA transfer can never complete it. > > Reference the clock from the three MMC controller nodes so the driver > keeps it running, instead of relying on the clock being marked critical > in the clock controller. > > Assisted-by: Claude:claude-fable-5 > Signed-off-by: Lucas Tanure > --- > arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi | 15 +++++++++------ > 1 file changed, 9 insertions(+), 6 deletions(-) > > diff --git a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi > index c3dc479b137d..dbb4a95652c6 100644 > --- a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi > +++ b/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi > @@ -730,8 +730,9 @@ sd_emmc_a: mmc@88000 { > interrupts = ; > clocks = <&clkc_periphs CLKID_SYS_SD_EMMC_A>, > <&clkc_periphs CLKID_SD_EMMC_A>, > - <&scmi_clk CLKID_FCLK_DIV2>; > - clock-names = "core", "clkin0", "clkin1"; > + <&scmi_clk CLKID_FCLK_DIV2>, > + <&clkc_periphs CLKID_SYS_AMPIPE_NAND>; > + clock-names = "core", "clkin0", "clkin1", "pipeline"; > resets = <&reset RESET_SD_EMMC_A>; > assigned-clocks = <&clkc_periphs CLKID_SD_EMMC_A_SEL>; > assigned-clock-parents = <&xtal>; > @@ -744,8 +745,9 @@ sd_emmc_b: mmc@8a000 { > interrupts = ; > clocks = <&clkc_periphs CLKID_SYS_SD_EMMC_B>, > <&clkc_periphs CLKID_SD_EMMC_B>, > - <&scmi_clk CLKID_FCLK_DIV2>; > - clock-names = "core", "clkin0", "clkin1"; > + <&scmi_clk CLKID_FCLK_DIV2>, > + <&clkc_periphs CLKID_SYS_AMPIPE_NAND>; > + clock-names = "core", "clkin0", "clkin1", "pipeline"; > resets = <&reset RESET_SD_EMMC_B>; > assigned-clocks = <&clkc_periphs CLKID_SD_EMMC_B_SEL>; > assigned-clock-parents = <&xtal>; > @@ -758,8 +760,9 @@ sd_emmc_c: mmc@8c000 { > interrupts = ; > clocks = <&clkc_periphs CLKID_SYS_SD_EMMC_C>, > <&clkc_periphs CLKID_SD_EMMC_C>, > - <&scmi_clk CLKID_FCLK_DIV2>; > - clock-names = "core", "clkin0", "clkin1"; > + <&scmi_clk CLKID_FCLK_DIV2>, > + <&clkc_periphs CLKID_SYS_AMPIPE_NAND>; > + clock-names = "core", "clkin0", "clkin1", "pipeline"; > resets = <&reset RESET_SD_EMMC_C>; > assigned-clocks = <&clkc_periphs CLKID_SD_EMMC_C_SEL>; > assigned-clock-parents = <&xtal>; Reviewed-by: Neil Armstrong Thanks, Neil