* [PATCH v3 0/6] add support for T7 family clock controller
@ 2025-05-09 7:48 Jian Hu
2025-05-09 7:48 ` [PATCH v3 1/6] dt-bindings: clock: add Amlogic T7 PLL " Jian Hu
` (5 more replies)
0 siblings, 6 replies; 19+ messages in thread
From: Jian Hu @ 2025-05-09 7:48 UTC (permalink / raw)
To: Jerome Brunet, Xianwei Zhao, Chuan Liu, Neil Armstrong,
Kevin Hilman, Stephen Boyd, Michael Turquette, Dmitry Rokosov,
robh+dt, Rob Herring
Cc: Jian Hu, devicetree, linux-clk, linux-amlogic, linux-kernel,
linux-arm-kernel
It introduces three clock controllers:
- SCMI clock controller: these clocks are managed by the SCP and handled through SCMI.
- PLL clock controller.
- peripheral clock controller.
Changes v3 since v2 at [2]:
- update T7 PLL YAML
- add 't7_' prefix for t7 clock name and variable in t7-pll.c and t7-peripherals.c
- correct v1 patch link
- add new macro MESON_PCLK_V2
- update the driver,header,yaml file license
Changes v2 since v1 at [1]:
- add CLK_MESON import
- add const for clkc_regmap_config in PLL driver
- fix eth_rmii_sel parent
- update T7 PLL YAML file
[1]: https://lore.kernel.org/all/20241231060047.2298871-1-jian.hu@amlogic.com
[2]: https://lore.kernel.org/all/20250108094025.2664201-1-jian.hu@amlogic.com
Jian Hu (6):
dt-bindings: clock: add Amlogic T7 PLL clock controller
dt-bindings: clock: add Amlogic T7 SCMI clock controller
dt-bindings: clock: add Amlogic T7 peripherals clock controller
clk: meson: t7: add support for the T7 SoC PLL clock
clk: meson: add MESON_PCLK_V2 for sys gate clock
clk: meson: t7: add t7 clock peripherals controller driver
.../clock/amlogic,t7-peripherals-clkc.yaml | 112 +
.../bindings/clock/amlogic,t7-pll-clkc.yaml | 114 +
drivers/clk/meson/Kconfig | 27 +
drivers/clk/meson/Makefile | 2 +
drivers/clk/meson/clk-regmap.h | 24 +
drivers/clk/meson/t7-peripherals.c | 2359 +++++++++++++++++
drivers/clk/meson/t7-pll.c | 1193 +++++++++
.../clock/amlogic,t7-peripherals-clkc.h | 230 ++
.../dt-bindings/clock/amlogic,t7-pll-clkc.h | 56 +
include/dt-bindings/clock/amlogic,t7-scmi.h | 47 +
10 files changed, 4164 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/amlogic,t7-peripherals-clkc.yaml
create mode 100644 Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml
create mode 100644 drivers/clk/meson/t7-peripherals.c
create mode 100644 drivers/clk/meson/t7-pll.c
create mode 100644 include/dt-bindings/clock/amlogic,t7-peripherals-clkc.h
create mode 100644 include/dt-bindings/clock/amlogic,t7-pll-clkc.h
create mode 100644 include/dt-bindings/clock/amlogic,t7-scmi.h
--
2.47.1
^ permalink raw reply [flat|nested] 19+ messages in thread* [PATCH v3 1/6] dt-bindings: clock: add Amlogic T7 PLL clock controller 2025-05-09 7:48 [PATCH v3 0/6] add support for T7 family clock controller Jian Hu @ 2025-05-09 7:48 ` Jian Hu 2025-05-09 16:09 ` Conor Dooley 2025-05-09 7:48 ` [PATCH v3 2/6] dt-bindings: clock: add Amlogic T7 SCMI " Jian Hu ` (4 subsequent siblings) 5 siblings, 1 reply; 19+ messages in thread From: Jian Hu @ 2025-05-09 7:48 UTC (permalink / raw) To: Jerome Brunet, Xianwei Zhao, Chuan Liu, Neil Armstrong, Kevin Hilman, Stephen Boyd, Michael Turquette, Dmitry Rokosov, robh+dt, Rob Herring Cc: Jian Hu, devicetree, linux-clk, linux-amlogic, linux-kernel, linux-arm-kernel Add DT bindings for the PLL clock controller of the Amlogic T7 SoC family. Signed-off-by: Jian Hu <jian.hu@amlogic.com> --- .../bindings/clock/amlogic,t7-pll-clkc.yaml | 114 ++++++++++++++++++ .../dt-bindings/clock/amlogic,t7-pll-clkc.h | 56 +++++++++ 2 files changed, 170 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml create mode 100644 include/dt-bindings/clock/amlogic,t7-pll-clkc.h diff --git a/Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml new file mode 100644 index 000000000000..aea3763616a0 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml @@ -0,0 +1,114 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2024 Amlogic, Inc. All rights reserved +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/amlogic,t7-pll-clkc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic T7 PLL Clock Control Controller + +maintainers: + - Neil Armstrong <neil.armstrong@linaro.org> + - Jerome Brunet <jbrunet@baylibre.com> + - Jian Hu <jian.hu@amlogic.com> + - Xianwei Zhao <xianwei.zhao@amlogic.com> + +properties: + compatible: + enum: + - amlogic,t7-pll-gp0 + - amlogic,t7-pll-gp1 + - amlogic,t7-pll-hifi + - amlogic,t7-pll-pcie + - amlogic,t7-mpll + - amlogic,t7-pll-hdmi + - amlogic,t7-pll-mclk + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + + clocks: + items: + - description: mclk pll input oscillator gate + - description: oscillator input clock source for mclk_sel_0 + - description: fixed input clock source for mclk_sel_0 + minItems: 1 + + clock-names: + items: + - const: in0 + - const: in1 + - const: in2 + minItems: 1 + +required: + - compatible + - '#clock-cells' + - reg + - clocks + - clock-names + +allOf: + - if: + properties: + compatible: + contains: + const: amlogic,t7-pll-mclk + + then: + properties: + clocks: + minItems: 3 + + clock-names: + minItems: 3 + + - if: + properties: + compatible: + contains: + enum: + - amlogic,t7-pll-gp0 + - amlogic,t7-pll-gp1 + - amlogic,t7-pll-hifi + - amlogic,t7-pll-pcie + - amlogic,t7-mpll + - amlogic,t7-pll-hdmi + + then: + properties: + clocks: + maxItems: 1 + + clock-names: + maxItems: 1 + +additionalProperties: false + +examples: + - | + apb { + #address-cells = <2>; + #size-cells = <2>; + + clock-controller@8080 { + compatible = "amlogic,t7-pll-gp0"; + reg = <0 0x8080 0 0x20>; + clocks = <&scmi_clk 2>; + clock-names = "in0"; + #clock-cells = <1>; + }; + + clock-controller@8300 { + compatible = "amlogic,t7-pll-mclk"; + reg = <0 0x8300 0 0x18>; + clocks = <&scmi_clk 2>, + <&xtal>, + <&scmi_clk 31>; + clock-names = "in0", "in1", "in2"; + #clock-cells = <1>; + }; + }; diff --git a/include/dt-bindings/clock/amlogic,t7-pll-clkc.h b/include/dt-bindings/clock/amlogic,t7-pll-clkc.h new file mode 100644 index 000000000000..b0cb5892ac34 --- /dev/null +++ b/include/dt-bindings/clock/amlogic,t7-pll-clkc.h @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright (C) 2024 Amlogic, Inc. All rights reserved + */ + +#ifndef __T7_PLL_CLKC_H +#define __T7_PLL_CLKC_H + +/* GP0 */ +#define CLKID_GP0_PLL_DCO 0 +#define CLKID_GP0_PLL 1 + +/* GP1 */ +#define CLKID_GP1_PLL_DCO 0 +#define CLKID_GP1_PLL 1 + +/* HIFI */ +#define CLKID_HIFI_PLL_DCO 0 +#define CLKID_HIFI_PLL 1 + +/* PCIE */ +#define CLKID_PCIE_PLL_DCO 0 +#define CLKID_PCIE_PLL_DCO_DIV2 1 +#define CLKID_PCIE_PLL_OD 2 +#define CLKID_PCIE_PLL 3 + +/* MPLL */ +#define CLKID_MPLL_PREDIV 0 +#define CLKID_MPLL0_DIV 1 +#define CLKID_MPLL0 2 +#define CLKID_MPLL1_DIV 3 +#define CLKID_MPLL1 4 +#define CLKID_MPLL2_DIV 5 +#define CLKID_MPLL2 6 +#define CLKID_MPLL3_DIV 7 +#define CLKID_MPLL3 8 + +/* HDMI */ +#define CLKID_HDMI_PLL_DCO 0 +#define CLKID_HDMI_PLL_OD 1 +#define CLKID_HDMI_PLL 2 + +/* MCLK */ +#define CLKID_MCLK_PLL_DCO 0 +#define CLKID_MCLK_PRE 1 +#define CLKID_MCLK_PLL 2 +#define CLKID_MCLK_0_SEL 3 +#define CLKID_MCLK_0_DIV2 4 +#define CLKID_MCLK_0_PRE 5 +#define CLKID_MCLK_0 6 +#define CLKID_MCLK_1_SEL 7 +#define CLKID_MCLK_1_DIV2 8 +#define CLKID_MCLK_1_PRE 9 +#define CLKID_MCLK_1 10 + +#endif /* __T7_PLL_CLKC_H */ -- 2.47.1 ^ permalink raw reply related [flat|nested] 19+ messages in thread
* Re: [PATCH v3 1/6] dt-bindings: clock: add Amlogic T7 PLL clock controller 2025-05-09 7:48 ` [PATCH v3 1/6] dt-bindings: clock: add Amlogic T7 PLL " Jian Hu @ 2025-05-09 16:09 ` Conor Dooley 0 siblings, 0 replies; 19+ messages in thread From: Conor Dooley @ 2025-05-09 16:09 UTC (permalink / raw) To: Jian Hu Cc: Jerome Brunet, Xianwei Zhao, Chuan Liu, Neil Armstrong, Kevin Hilman, Stephen Boyd, Michael Turquette, Dmitry Rokosov, robh+dt, Rob Herring, devicetree, linux-clk, linux-amlogic, linux-kernel, linux-arm-kernel [-- Attachment #1: Type: text/plain, Size: 287 bytes --] On Fri, May 09, 2025 at 07:48:19AM +0000, Jian Hu wrote: > Add DT bindings for the PLL clock controller of the Amlogic T7 SoC family. > > Signed-off-by: Jian Hu <jian.hu@amlogic.com> Looks like Rob's comments got resolved, Reviewed-by: Conor Dooley <conor.dooley@microchip.com> [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 228 bytes --] ^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v3 2/6] dt-bindings: clock: add Amlogic T7 SCMI clock controller 2025-05-09 7:48 [PATCH v3 0/6] add support for T7 family clock controller Jian Hu 2025-05-09 7:48 ` [PATCH v3 1/6] dt-bindings: clock: add Amlogic T7 PLL " Jian Hu @ 2025-05-09 7:48 ` Jian Hu 2025-05-09 7:48 ` [PATCH v3 3/6] dt-bindings: clock: add Amlogic T7 peripherals " Jian Hu ` (3 subsequent siblings) 5 siblings, 0 replies; 19+ messages in thread From: Jian Hu @ 2025-05-09 7:48 UTC (permalink / raw) To: Jerome Brunet, Xianwei Zhao, Chuan Liu, Neil Armstrong, Kevin Hilman, Stephen Boyd, Michael Turquette, Dmitry Rokosov, robh+dt, Rob Herring Cc: Jian Hu, devicetree, linux-clk, linux-amlogic, linux-kernel, linux-arm-kernel Add DT bindings for the SCMI clock controller of the Amlogic T7 SoC family. Signed-off-by: Jian Hu <jian.hu@amlogic.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> --- include/dt-bindings/clock/amlogic,t7-scmi.h | 47 +++++++++++++++++++++ 1 file changed, 47 insertions(+) create mode 100644 include/dt-bindings/clock/amlogic,t7-scmi.h diff --git a/include/dt-bindings/clock/amlogic,t7-scmi.h b/include/dt-bindings/clock/amlogic,t7-scmi.h new file mode 100644 index 000000000000..76061c5e79ea --- /dev/null +++ b/include/dt-bindings/clock/amlogic,t7-scmi.h @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright (C) 2024 Amlogic, Inc. All rights reserved + */ + +#ifndef __T7_SCMI_CLKC_H +#define __T7_SCMI_CLKC_H + +#define CLKID_DDR_PLL_OSC 0 +#define CLKID_AUD_PLL_OSC 1 +#define CLKID_TOP_PLL_OSC 2 +#define CLKID_TCON_PLL_OSC 3 +#define CLKID_USB_PLL0_OSC 4 +#define CLKID_USB_PLL1_OSC 5 +#define CLKID_MCLK_PLL_OSC 6 +#define CLKID_PCIE_OSC 7 +#define CLKID_ETH_PLL_OSC 8 +#define CLKID_PCIE_REFCLK_PLL_OSC 9 +#define CLKID_EARC_OSC 10 +#define CLKID_SYS1_PLL_OSC 11 +#define CLKID_HDMI_PLL_OSC 12 +#define CLKID_SYS_CLK 13 +#define CLKID_AXI_CLK 14 +#define CLKID_FIXED_PLL_DCO 15 +#define CLKID_FIXED_PLL 16 +#define CLKID_FCLK_DIV2_DIV 17 +#define CLKID_FCLK_DIV2 18 +#define CLKID_FCLK_DIV2P5_DIV 19 +#define CLKID_FCLK_DIV2P5 20 +#define CLKID_FCLK_DIV3_DIV 21 +#define CLKID_FCLK_DIV3 22 +#define CLKID_FCLK_DIV4_DIV 23 +#define CLKID_FCLK_DIV4 24 +#define CLKID_FCLK_DIV5_DIV 25 +#define CLKID_FCLK_DIV5 26 +#define CLKID_FCLK_DIV7_DIV 27 +#define CLKID_FCLK_DIV7 28 +#define CLKID_FCLK_50M_DIV 29 +#define CLKID_FCLK_50M 30 +#define CLKID_CPU_CLK 31 +#define CLKID_A73_CLK 32 +#define CLKID_CPU_CLK_DIV16_DIV 33 +#define CLKID_CPU_CLK_DIV16 34 +#define CLKID_A73_CLK_DIV16_DIV 35 +#define CLKID_A73_CLK_DIV16 36 + +#endif /* __T7_SCMI_CLKC_H */ -- 2.47.1 ^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v3 3/6] dt-bindings: clock: add Amlogic T7 peripherals clock controller 2025-05-09 7:48 [PATCH v3 0/6] add support for T7 family clock controller Jian Hu 2025-05-09 7:48 ` [PATCH v3 1/6] dt-bindings: clock: add Amlogic T7 PLL " Jian Hu 2025-05-09 7:48 ` [PATCH v3 2/6] dt-bindings: clock: add Amlogic T7 SCMI " Jian Hu @ 2025-05-09 7:48 ` Jian Hu 2025-05-09 7:48 ` [PATCH v3 4/6] clk: meson: t7: add support for the T7 SoC PLL clock Jian Hu ` (2 subsequent siblings) 5 siblings, 0 replies; 19+ messages in thread From: Jian Hu @ 2025-05-09 7:48 UTC (permalink / raw) To: Jerome Brunet, Xianwei Zhao, Chuan Liu, Neil Armstrong, Kevin Hilman, Stephen Boyd, Michael Turquette, Dmitry Rokosov, robh+dt, Rob Herring Cc: Jian Hu, devicetree, linux-clk, linux-amlogic, linux-kernel, linux-arm-kernel Add DT bindings for the peripheral clock controller of the Amlogic T7 SoC family. Signed-off-by: Jian Hu <jian.hu@amlogic.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> --- .../clock/amlogic,t7-peripherals-clkc.yaml | 112 +++++++++ .../clock/amlogic,t7-peripherals-clkc.h | 230 ++++++++++++++++++ 2 files changed, 342 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/amlogic,t7-peripherals-clkc.yaml create mode 100644 include/dt-bindings/clock/amlogic,t7-peripherals-clkc.h diff --git a/Documentation/devicetree/bindings/clock/amlogic,t7-peripherals-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,t7-peripherals-clkc.yaml new file mode 100644 index 000000000000..c7544d0d89c7 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/amlogic,t7-peripherals-clkc.yaml @@ -0,0 +1,112 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2024 Amlogic, Inc. All rights reserved +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/amlogic,t7-peripherals-clkc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic T7 Peripherals Clock Controller + +maintainers: + - Neil Armstrong <neil.armstrong@linaro.org> + - Jerome Brunet <jbrunet@baylibre.com> + - Xianwei Zhao <xianwei.zhao@amlogic.com> + - Jian Hu <jian.hu@amlogic.com> + +properties: + compatible: + const: amlogic,t7-peripherals-clkc + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + + clocks: + minItems: 13 + items: + - description: input oscillator + - description: input sys clk + - description: input fclk div 2 + - description: input fclk div 2p5 + - description: input fclk div 3 + - description: input fclk div 4 + - description: input fclk div 5 + - description: input fclk div 7 + - description: input hifi pll + - description: input gp0 pll + - description: input gp1 pll + - description: input mpll1 + - description: input mpll2 + - description: external input rmii oscillator (optional) + - description: input video pll0 (optional) + - description: external pad input for rtc (optional) + + clock-names: + minItems: 13 + items: + - const: xtal + - const: sys + - const: fdiv2 + - const: fdiv2p5 + - const: fdiv3 + - const: fdiv4 + - const: fdiv5 + - const: fdiv7 + - const: hifi + - const: gp0 + - const: gp1 + - const: mpll1 + - const: mpll2 + - const: ext_rmii + - const: vid_pll0 + - const: ext_rtc + +required: + - compatible + - '#clock-cells' + - reg + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + apb { + #address-cells = <2>; + #size-cells = <2>; + + clkc_periphs:clock-controller@0 { + compatible = "amlogic,t7-peripherals-clkc"; + reg = <0 0x0 0 0x1c8>; + #clock-cells = <1>; + clocks = <&xtal>, + <&scmi_clk 13>, + <&scmi_clk 18>, + <&scmi_clk 20>, + <&scmi_clk 22>, + <&scmi_clk 24>, + <&scmi_clk 26>, + <&scmi_clk 28>, + <&hifi 1>, + <&gp0 1>, + <&gp1 1>, + <&mpll 4>, + <&mpll 6>; + clock-names = "xtal", + "sys", + "fdiv2", + "fdiv2p5", + "fdiv3", + "fdiv4", + "fdiv5", + "fdiv7", + "hifi", + "gp0", + "gp1", + "mpll1", + "mpll2"; + }; + }; diff --git a/include/dt-bindings/clock/amlogic,t7-peripherals-clkc.h b/include/dt-bindings/clock/amlogic,t7-peripherals-clkc.h new file mode 100644 index 000000000000..82ce9a7624ac --- /dev/null +++ b/include/dt-bindings/clock/amlogic,t7-peripherals-clkc.h @@ -0,0 +1,230 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright (C) 2024 Amlogic, Inc. All rights reserved + */ + +#ifndef __T7_PERIPHERALS_CLKC_H +#define __T7_PERIPHERALS_CLKC_H + +#define CLKID_RTC_32K_IN 0 +#define CLKID_RTC_32K_DIV 1 +#define CLKID_RTC_32K_FORCE_SEL 2 +#define CLKID_RTC_32K_OUT 3 +#define CLKID_RTC_32K_MUX0_0 4 +#define CLKID_RTC_32K_MUX0_1 5 +#define CLKID_RTC 6 +#define CLKID_CECB_32K_IN 7 +#define CLKID_CECB_32K_DIV 8 +#define CLKID_CECB_32K_SEL_PRE 9 +#define CLKID_CECB_32K_SEL 10 +#define CLKID_CECA_32K_IN 11 +#define CLKID_CECA_32K_DIV 12 +#define CLKID_CECA_32K_SEL_PRE 13 +#define CLKID_CECA_32K_SEL 14 +#define CLKID_CECA_32K 15 +#define CLKID_CECB_32K 16 +#define CLKID_SC_SEL 17 +#define CLKID_SC_DIV 18 +#define CLKID_SC 19 +#define CLKID_DSPA_A_SEL 20 +#define CLKID_DSPA_A_DIV 21 +#define CLKID_DSPA_A 22 +#define CLKID_DSPA_B_SEL 23 +#define CLKID_DSPA_B_DIV 24 +#define CLKID_DSPA_B 25 +#define CLKID_DSPA 26 +#define CLKID_DSPB_A_SEL 27 +#define CLKID_DSPB_A_DIV 28 +#define CLKID_DSPB_A 29 +#define CLKID_DSPB_B_SEL 30 +#define CLKID_DSPB_B_DIV 31 +#define CLKID_DSPB_B 32 +#define CLKID_DSPB 33 +#define CLKID_CLK_24M 34 +#define CLKID_CLK_24M_DIV2 35 +#define CLKID_CLK_12M 36 +#define CLKID_ANAKIN_0_SEL 37 +#define CLKID_ANAKIN_0_DIV 38 +#define CLKID_ANAKIN_0 39 +#define CLKID_ANAKIN_1_SEL 40 +#define CLKID_ANAKIN_1_DIV 41 +#define CLKID_ANAKIN_1 42 +#define CLKID_ANAKIN 43 +#define CLKID_ANAKIN_CLK 44 +#define CLKID_FCLK_DIV2_DIVN_PRE 45 +#define CLKID_FCLK_DIV2_DIVN 46 +#define CLKID_TS_DIV 47 +#define CLKID_TS 48 +#define CLKID_MIPI_CSI_PHY_0_SEL 49 +#define CLKID_MIPI_CSI_PHY_0_DIV 50 +#define CLKID_MIPI_CSI_PHY_0 51 +#define CLKID_MIPI_CSI_PHY_1_SEL 52 +#define CLKID_MIPI_CSI_PHY_1_DIV 53 +#define CLKID_MIPI_CSI_PHY_1 54 +#define CLKID_MIPI_CSI_PHY 55 +#define CLKID_MIPI_ISP_SEL 56 +#define CLKID_MIPI_ISP_DIV 57 +#define CLKID_MIPI_ISP 58 +#define CLKID_MALI_0_SEL 59 +#define CLKID_MALI_0_DIV 60 +#define CLKID_MALI_0 61 +#define CLKID_MALI_1_SEL 62 +#define CLKID_MALI_1_DIV 63 +#define CLKID_MALI_1 64 +#define CLKID_MALI 65 +#define CLKID_ETH_RMII_SEL 66 +#define CLKID_ETH_RMII_DIV 67 +#define CLKID_ETH_RMII 68 +#define CLKID_FCLK_DIV2_DIV8 69 +#define CLKID_ETH_125M 70 +#define CLKID_SD_EMMC_C_SEL 71 +#define CLKID_SD_EMMC_C_DIV 72 +#define CLKID_SD_EMMC_C 73 +#define CLKID_SD_EMMC_A_SEL 74 +#define CLKID_SD_EMMC_A_DIV 75 +#define CLKID_SD_EMMC_A 76 +#define CLKID_SD_EMMC_B_SEL 77 +#define CLKID_SD_EMMC_B_DIV 78 +#define CLKID_SD_EMMC_B 79 +#define CLKID_SPICC0_SEL 80 +#define CLKID_SPICC0_DIV 81 +#define CLKID_SPICC0 82 +#define CLKID_SPICC1_SEL 83 +#define CLKID_SPICC1_DIV 84 +#define CLKID_SPICC1 85 +#define CLKID_SPICC2_SEL 86 +#define CLKID_SPICC2_DIV 87 +#define CLKID_SPICC2 88 +#define CLKID_SPICC3_SEL 89 +#define CLKID_SPICC3_DIV 90 +#define CLKID_SPICC3 91 +#define CLKID_SPICC4_SEL 92 +#define CLKID_SPICC4_DIV 93 +#define CLKID_SPICC4 94 +#define CLKID_SPICC5_SEL 95 +#define CLKID_SPICC5_DIV 96 +#define CLKID_SPICC5 97 +#define CLKID_SARADC_SEL 98 +#define CLKID_SARADC_DIV 99 +#define CLKID_SARADC 100 +#define CLKID_PWM_A_SEL 101 +#define CLKID_PWM_A_DIV 102 +#define CLKID_PWM_A 103 +#define CLKID_PWM_B_SEL 104 +#define CLKID_PWM_B_DIV 105 +#define CLKID_PWM_B 106 +#define CLKID_PWM_C_SEL 107 +#define CLKID_PWM_C_DIV 108 +#define CLKID_PWM_C 109 +#define CLKID_PWM_D_SEL 110 +#define CLKID_PWM_D_DIV 111 +#define CLKID_PWM_D 112 +#define CLKID_PWM_E_SEL 113 +#define CLKID_PWM_E_DIV 114 +#define CLKID_PWM_E 115 +#define CLKID_PWM_F_SEL 116 +#define CLKID_PWM_F_DIV 117 +#define CLKID_PWM_F 118 +#define CLKID_PWM_AO_A_SEL 119 +#define CLKID_PWM_AO_A_DIV 120 +#define CLKID_PWM_AO_A 121 +#define CLKID_PWM_AO_B_SEL 122 +#define CLKID_PWM_AO_B_DIV 123 +#define CLKID_PWM_AO_B 124 +#define CLKID_PWM_AO_C_SEL 125 +#define CLKID_PWM_AO_C_DIV 126 +#define CLKID_PWM_AO_C 127 +#define CLKID_PWM_AO_D_SEL 128 +#define CLKID_PWM_AO_D_DIV 129 +#define CLKID_PWM_AO_D 130 +#define CLKID_PWM_AO_E_SEL 131 +#define CLKID_PWM_AO_E_DIV 132 +#define CLKID_PWM_AO_E 133 +#define CLKID_PWM_AO_F_SEL 134 +#define CLKID_PWM_AO_F_DIV 135 +#define CLKID_PWM_AO_F 136 +#define CLKID_PWM_AO_G_SEL 137 +#define CLKID_PWM_AO_G_DIV 138 +#define CLKID_PWM_AO_G 139 +#define CLKID_PWM_AO_H_SEL 140 +#define CLKID_PWM_AO_H_DIV 141 +#define CLKID_PWM_AO_H 142 +#define CLKID_SYS_DDR 143 +#define CLKID_SYS_DOS 144 +#define CLKID_SYS_MIPI_DSI_A 145 +#define CLKID_SYS_MIPI_DSI_B 146 +#define CLKID_SYS_ETHPHY 147 +#define CLKID_SYS_MALI 148 +#define CLKID_SYS_AOCPU 149 +#define CLKID_SYS_AUCPU 150 +#define CLKID_SYS_CEC 151 +#define CLKID_SYS_GDC 152 +#define CLKID_SYS_DESWARP 153 +#define CLKID_SYS_AMPIPE_NAND 154 +#define CLKID_SYS_AMPIPE_ETH 155 +#define CLKID_SYS_AM2AXI0 156 +#define CLKID_SYS_AM2AXI1 157 +#define CLKID_SYS_AM2AXI2 158 +#define CLKID_SYS_SD_EMMC_A 159 +#define CLKID_SYS_SD_EMMC_B 160 +#define CLKID_SYS_SD_EMMC_C 161 +#define CLKID_SYS_SMARTCARD 162 +#define CLKID_SYS_ACODEC 163 +#define CLKID_SYS_SPIFC 164 +#define CLKID_SYS_MSR_CLK 165 +#define CLKID_SYS_IR_CTRL 166 +#define CLKID_SYS_AUDIO 167 +#define CLKID_SYS_ETH 168 +#define CLKID_SYS_UART_A 169 +#define CLKID_SYS_UART_B 170 +#define CLKID_SYS_UART_C 171 +#define CLKID_SYS_UART_D 172 +#define CLKID_SYS_UART_E 173 +#define CLKID_SYS_UART_F 174 +#define CLKID_SYS_AIFIFO 175 +#define CLKID_SYS_SPICC2 176 +#define CLKID_SYS_SPICC3 177 +#define CLKID_SYS_SPICC4 178 +#define CLKID_SYS_TS_A73 179 +#define CLKID_SYS_TS_A53 180 +#define CLKID_SYS_SPICC5 181 +#define CLKID_SYS_G2D 182 +#define CLKID_SYS_SPICC0 183 +#define CLKID_SYS_SPICC1 184 +#define CLKID_SYS_PCIE 185 +#define CLKID_SYS_USB 186 +#define CLKID_SYS_PCIE_PHY 187 +#define CLKID_SYS_I2C_AO_A 188 +#define CLKID_SYS_I2C_AO_B 189 +#define CLKID_SYS_I2C_M_A 190 +#define CLKID_SYS_I2C_M_B 191 +#define CLKID_SYS_I2C_M_C 192 +#define CLKID_SYS_I2C_M_D 193 +#define CLKID_SYS_I2C_M_E 194 +#define CLKID_SYS_I2C_M_F 195 +#define CLKID_SYS_HDMITX_APB 196 +#define CLKID_SYS_I2C_S_A 197 +#define CLKID_SYS_HDMIRX_PCLK 198 +#define CLKID_SYS_MMC_APB 199 +#define CLKID_SYS_MIPI_ISP_PCLK 200 +#define CLKID_SYS_RSA 201 +#define CLKID_SYS_PCLK_SYS_APB 202 +#define CLKID_SYS_A73PCLK_APB 203 +#define CLKID_SYS_DSPA 204 +#define CLKID_SYS_DSPB 205 +#define CLKID_SYS_VPU_INTR 206 +#define CLKID_SYS_SAR_ADC 207 +#define CLKID_SYS_GIC 208 +#define CLKID_SYS_TS_GPU 209 +#define CLKID_SYS_TS_NNA 210 +#define CLKID_SYS_TS_VPU 211 +#define CLKID_SYS_TS_HEVC 212 +#define CLKID_SYS_PWM_AB 213 +#define CLKID_SYS_PWM_CD 214 +#define CLKID_SYS_PWM_EF 215 +#define CLKID_SYS_PWM_AO_AB 216 +#define CLKID_SYS_PWM_AO_CD 217 +#define CLKID_SYS_PWM_AO_EF 218 +#define CLKID_SYS_PWM_AO_GH 219 + +#endif /* __T7_PERIPHERALS_CLKC_H */ -- 2.47.1 ^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v3 4/6] clk: meson: t7: add support for the T7 SoC PLL clock 2025-05-09 7:48 [PATCH v3 0/6] add support for T7 family clock controller Jian Hu ` (2 preceding siblings ...) 2025-05-09 7:48 ` [PATCH v3 3/6] dt-bindings: clock: add Amlogic T7 peripherals " Jian Hu @ 2025-05-09 7:48 ` Jian Hu 2025-05-14 7:52 ` Jerome Brunet 2025-05-09 7:48 ` [PATCH v3 5/6] clk: meson: add MESON_PCLK_V2 for sys gate clock Jian Hu 2025-05-09 7:48 ` [PATCH v3 6/6] clk: meson: t7: add t7 clock peripherals controller driver Jian Hu 5 siblings, 1 reply; 19+ messages in thread From: Jian Hu @ 2025-05-09 7:48 UTC (permalink / raw) To: Jerome Brunet, Xianwei Zhao, Chuan Liu, Neil Armstrong, Kevin Hilman, Stephen Boyd, Michael Turquette, Dmitry Rokosov, robh+dt, Rob Herring Cc: Jian Hu, devicetree, linux-clk, linux-amlogic, linux-kernel, linux-arm-kernel Add PLL clock controller driver for the Amlogic T7 SoC family. Signed-off-by: Jian Hu <jian.hu@amlogic.com> --- drivers/clk/meson/Kconfig | 14 + drivers/clk/meson/Makefile | 1 + drivers/clk/meson/t7-pll.c | 1193 ++++++++++++++++++++++++++++++++++++ 3 files changed, 1208 insertions(+) create mode 100644 drivers/clk/meson/t7-pll.c diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig index be2e3a5f8336..8bb4f26a86ed 100644 --- a/drivers/clk/meson/Kconfig +++ b/drivers/clk/meson/Kconfig @@ -202,4 +202,18 @@ config COMMON_CLK_S4_PERIPHERALS help Support for the peripherals clock controller on Amlogic S805X2 and S905Y4 devices, AKA S4. Say Y if you want S4 peripherals clock controller to work. + +config COMMON_CLK_T7_PLL + tristate "Amlogic T7 SoC PLL controller support" + depends on ARM64 + default y + select COMMON_CLK_MESON_REGMAP + select COMMON_CLK_MESON_CLKC_UTILS + select COMMON_CLK_MESON_PLL + imply COMMON_CLK_SCMI + help + Support for the PLL clock controller on Amlogic A311D2 based + device, AKA T7. PLLs are required by most peripheral to operate + Say Y if you are a T7 based device. + endmenu diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile index bc56a47931c1..646257694c34 100644 --- a/drivers/clk/meson/Makefile +++ b/drivers/clk/meson/Makefile @@ -27,3 +27,4 @@ obj-$(CONFIG_COMMON_CLK_G12A) += g12a.o g12a-aoclk.o obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o meson8-ddr.o obj-$(CONFIG_COMMON_CLK_S4_PLL) += s4-pll.o obj-$(CONFIG_COMMON_CLK_S4_PERIPHERALS) += s4-peripherals.o +obj-$(CONFIG_COMMON_CLK_T7_PLL) += t7-pll.o diff --git a/drivers/clk/meson/t7-pll.c b/drivers/clk/meson/t7-pll.c new file mode 100644 index 000000000000..d2ec45d5e783 --- /dev/null +++ b/drivers/clk/meson/t7-pll.c @@ -0,0 +1,1193 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR MIT) +/* + * Copyright (C) 2024 Amlogic, Inc. All rights reserved. + * Author: Jian Hu <jian.hu@amlogic.com> + */ + +#include <linux/clk-provider.h> +#include <linux/platform_device.h> +#include "clk-regmap.h" +#include "clk-pll.h" +#include "clk-mpll.h" +#include "meson-clkc-utils.h" +#include "meson-eeclk.h" +#include <dt-bindings/clock/amlogic,t7-pll-clkc.h> + +#define ANACTRL_GP0PLL_CTRL0 0x00 +#define ANACTRL_GP0PLL_CTRL1 0x04 +#define ANACTRL_GP0PLL_CTRL2 0x08 +#define ANACTRL_GP0PLL_CTRL3 0x0c +#define ANACTRL_GP0PLL_CTRL4 0x10 +#define ANACTRL_GP0PLL_CTRL5 0x14 +#define ANACTRL_GP0PLL_CTRL6 0x18 +#define ANACTRL_GP0PLL_STS 0x1c + +#define ANACTRL_GP1PLL_CTRL0 0x00 +#define ANACTRL_GP1PLL_CTRL1 0x04 +#define ANACTRL_GP1PLL_CTRL2 0x08 +#define ANACTRL_GP1PLL_CTRL3 0x0c +#define ANACTRL_GP1PLL_STS 0x1c + +#define ANACTRL_HIFIPLL_CTRL0 0x00 +#define ANACTRL_HIFIPLL_CTRL1 0x04 +#define ANACTRL_HIFIPLL_CTRL2 0x08 +#define ANACTRL_HIFIPLL_CTRL3 0x0c +#define ANACTRL_HIFIPLL_CTRL4 0x10 +#define ANACTRL_HIFIPLL_CTRL5 0x14 +#define ANACTRL_HIFIPLL_CTRL6 0x18 +#define ANACTRL_HIFIPLL_STS 0x1c + +#define ANACTRL_PCIEPLL_CTRL0 0x00 +#define ANACTRL_PCIEPLL_CTRL1 0x04 +#define ANACTRL_PCIEPLL_CTRL2 0x08 +#define ANACTRL_PCIEPLL_CTRL3 0x0c +#define ANACTRL_PCIEPLL_CTRL4 0x10 +#define ANACTRL_PCIEPLL_CTRL5 0x14 +#define ANACTRL_PCIEPLL_STS 0x18 + +#define ANACTRL_MPLL_CTRL0 0x00 +#define ANACTRL_MPLL_CTRL1 0x04 +#define ANACTRL_MPLL_CTRL2 0x08 +#define ANACTRL_MPLL_CTRL3 0x0c +#define ANACTRL_MPLL_CTRL4 0x10 +#define ANACTRL_MPLL_CTRL5 0x14 +#define ANACTRL_MPLL_CTRL6 0x18 +#define ANACTRL_MPLL_CTRL7 0x1c +#define ANACTRL_MPLL_CTRL8 0x20 +#define ANACTRL_MPLL_STS 0x24 + +#define ANACTRL_HDMIPLL_CTRL0 0x00 +#define ANACTRL_HDMIPLL_CTRL1 0x04 +#define ANACTRL_HDMIPLL_CTRL2 0x08 +#define ANACTRL_HDMIPLL_CTRL3 0x0c +#define ANACTRL_HDMIPLL_CTRL4 0x10 +#define ANACTRL_HDMIPLL_CTRL5 0x14 +#define ANACTRL_HDMIPLL_CTRL6 0x18 +#define ANACTRL_HDMIPLL_STS 0x1c + +#define ANACTRL_MCLK_PLL_CNTL0 0x00 +#define ANACTRL_MCLK_PLL_CNTL1 0x04 +#define ANACTRL_MCLK_PLL_CNTL2 0x08 +#define ANACTRL_MCLK_PLL_CNTL3 0x0c +#define ANACTRL_MCLK_PLL_CNTL4 0x10 +#define ANACTRL_MCLK_PLL_STS 0x14 + +static const struct pll_mult_range t7_media_pll_mult_range = { + .min = 125, + .max = 250, +}; + +static const struct reg_sequence t7_gp0_init_regs[] = { + { .reg = ANACTRL_GP0PLL_CTRL1, .def = 0x00000000 }, + { .reg = ANACTRL_GP0PLL_CTRL2, .def = 0x00000000 }, + { .reg = ANACTRL_GP0PLL_CTRL3, .def = 0x48681c00 }, + { .reg = ANACTRL_GP0PLL_CTRL4, .def = 0x88770290 }, + { .reg = ANACTRL_GP0PLL_CTRL5, .def = 0x3927200a }, + { .reg = ANACTRL_GP0PLL_CTRL6, .def = 0x56540000 }, +}; + +static struct clk_regmap t7_gp0_pll_dco = { + .data = &(struct meson_clk_pll_data){ + .en = { + .reg_off = ANACTRL_GP0PLL_CTRL0, + .shift = 28, + .width = 1, + }, + .m = { + .reg_off = ANACTRL_GP0PLL_CTRL0, + .shift = 0, + .width = 8, + }, + .n = { + .reg_off = ANACTRL_GP0PLL_CTRL0, + .shift = 10, + .width = 5, + }, + .l = { + .reg_off = ANACTRL_GP0PLL_STS, + .shift = 31, + .width = 1, + }, + .rst = { + .reg_off = ANACTRL_GP0PLL_CTRL0, + .shift = 29, + .width = 1, + }, + .range = &t7_media_pll_mult_range, + .init_regs = t7_gp0_init_regs, + .init_count = ARRAY_SIZE(t7_gp0_init_regs), + }, + .hw.init = &(struct clk_init_data){ + .name = "t7_gp0_pll_dco", + .ops = &meson_clk_pll_ops, + .parent_data = &(const struct clk_parent_data) { + .fw_name = "in0", + }, + .num_parents = 1, + }, +}; + +static struct clk_regmap t7_gp0_pll = { + .data = &(struct clk_regmap_div_data){ + .offset = ANACTRL_GP0PLL_CTRL0, + .shift = 16, + .width = 3, + .flags = CLK_DIVIDER_POWER_OF_TWO, + }, + .hw.init = &(struct clk_init_data) { + .name = "t7_gp0_pll", + .ops = &clk_regmap_divider_ops, + .parent_hws = (const struct clk_hw *[]) { + &t7_gp0_pll_dco.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +/* + * The gp1 pll IP is different with gp0 pll, the PLL DCO range is + * 1.6GHZ - 3.2GHZ, and the reg_sequence is short + */ +static const struct pll_mult_range t7_gp1_pll_mult_range = { + .min = 67, + .max = 133, +}; + +static const struct reg_sequence t7_gp1_init_regs[] = { + { .reg = ANACTRL_GP1PLL_CTRL1, .def = 0x1420500f }, + { .reg = ANACTRL_GP1PLL_CTRL2, .def = 0x00023001 }, + { .reg = ANACTRL_GP1PLL_CTRL3, .def = 0x00000000 }, +}; + +static struct clk_regmap t7_gp1_pll_dco = { + .data = &(struct meson_clk_pll_data){ + .en = { + .reg_off = ANACTRL_GP1PLL_CTRL0, + .shift = 28, + .width = 1, + }, + .m = { + .reg_off = ANACTRL_GP1PLL_CTRL0, + .shift = 0, + .width = 8, + }, + .n = { + .reg_off = ANACTRL_GP1PLL_CTRL0, + .shift = 16, + .width = 5, + }, + .l = { + .reg_off = ANACTRL_GP1PLL_STS, + .shift = 31, + .width = 1, + }, + .rst = { + .reg_off = ANACTRL_GP1PLL_CTRL0, + .shift = 29, + .width = 1, + }, + .range = &t7_gp1_pll_mult_range, + .init_regs = t7_gp1_init_regs, + .init_count = ARRAY_SIZE(t7_gp1_init_regs), + }, + .hw.init = &(struct clk_init_data){ + .name = "t7_gp1_pll_dco", + .ops = &meson_clk_pll_ops, + .parent_data = &(const struct clk_parent_data) { + .fw_name = "in0", + }, + .num_parents = 1, + }, +}; + +static struct clk_regmap t7_gp1_pll = { + .data = &(struct clk_regmap_div_data){ + .offset = ANACTRL_GP1PLL_CTRL0, + .shift = 12, + .width = 3, + .flags = CLK_DIVIDER_POWER_OF_TWO, + }, + .hw.init = &(struct clk_init_data) { + .name = "t7_gp1_pll", + .ops = &clk_regmap_divider_ops, + .parent_hws = (const struct clk_hw *[]) { + &t7_gp1_pll_dco.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static const struct reg_sequence t7_hifi_init_regs[] = { + { .reg = ANACTRL_HIFIPLL_CTRL1, .def = 0x00000000 }, + { .reg = ANACTRL_HIFIPLL_CTRL2, .def = 0x00000000 }, + { .reg = ANACTRL_HIFIPLL_CTRL3, .def = 0x6a285c00 }, + { .reg = ANACTRL_HIFIPLL_CTRL4, .def = 0x65771290 }, + { .reg = ANACTRL_HIFIPLL_CTRL5, .def = 0x3927200a }, + { .reg = ANACTRL_HIFIPLL_CTRL6, .def = 0x56540000 } +}; + +static struct clk_regmap t7_hifi_pll_dco = { + .data = &(struct meson_clk_pll_data){ + .en = { + .reg_off = ANACTRL_HIFIPLL_CTRL0, + .shift = 28, + .width = 1, + }, + .m = { + .reg_off = ANACTRL_HIFIPLL_CTRL0, + .shift = 0, + .width = 8, + }, + .n = { + .reg_off = ANACTRL_HIFIPLL_CTRL0, + .shift = 10, + .width = 5, + }, + .l = { + .reg_off = ANACTRL_HIFIPLL_STS, + .shift = 31, + .width = 1, + }, + .rst = { + .reg_off = ANACTRL_HIFIPLL_CTRL0, + .shift = 29, + .width = 1, + }, + .range = &t7_media_pll_mult_range, + .init_regs = t7_hifi_init_regs, + .init_count = ARRAY_SIZE(t7_hifi_init_regs), + }, + .hw.init = &(struct clk_init_data){ + .name = "t7_hifi_pll_dco", + .ops = &meson_clk_pll_ops, + .parent_data = &(const struct clk_parent_data) { + .fw_name = "in0", + }, + .num_parents = 1, + }, +}; + +static struct clk_regmap t7_hifi_pll = { + .data = &(struct clk_regmap_div_data){ + .offset = ANACTRL_HIFIPLL_CTRL0, + .shift = 16, + .width = 2, + .flags = CLK_DIVIDER_POWER_OF_TWO, + }, + .hw.init = &(struct clk_init_data) { + .name = "t7_hifi_pll", + .ops = &clk_regmap_divider_ops, + .parent_hws = (const struct clk_hw *[]) { + &t7_hifi_pll_dco.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +/* + * The T7 PCIE PLL is fined tuned to deliver a very precise + * 100MHz reference clock for the PCIe Analog PHY, and thus requires + * a strict register sequence to enable the PLL. + */ +static const struct reg_sequence t7_pcie_pll_init_regs[] = { + { .reg = ANACTRL_PCIEPLL_CTRL0, .def = 0x200c04c8 }, + { .reg = ANACTRL_PCIEPLL_CTRL0, .def = 0x300c04c8 }, + { .reg = ANACTRL_PCIEPLL_CTRL1, .def = 0x30000000 }, + { .reg = ANACTRL_PCIEPLL_CTRL2, .def = 0x00001100 }, + { .reg = ANACTRL_PCIEPLL_CTRL3, .def = 0x10058e00 }, + { .reg = ANACTRL_PCIEPLL_CTRL4, .def = 0x000100c0 }, + { .reg = ANACTRL_PCIEPLL_CTRL5, .def = 0x68000048 }, + { .reg = ANACTRL_PCIEPLL_CTRL5, .def = 0x68000068, .delay_us = 20 }, + { .reg = ANACTRL_PCIEPLL_CTRL4, .def = 0x008100c0, .delay_us = 20 }, + { .reg = ANACTRL_PCIEPLL_CTRL0, .def = 0x340c04c8 }, + { .reg = ANACTRL_PCIEPLL_CTRL0, .def = 0x140c04c8, .delay_us = 20 }, + { .reg = ANACTRL_PCIEPLL_CTRL2, .def = 0x00001000 } +}; + +static struct clk_regmap t7_pcie_pll_dco = { + .data = &(struct meson_clk_pll_data){ + .en = { + .reg_off = ANACTRL_PCIEPLL_CTRL0, + .shift = 28, + .width = 1, + }, + .m = { + .reg_off = ANACTRL_PCIEPLL_CTRL0, + .shift = 0, + .width = 8, + }, + .n = { + .reg_off = ANACTRL_PCIEPLL_CTRL0, + .shift = 10, + .width = 5, + }, + .l = { + .reg_off = ANACTRL_PCIEPLL_CTRL0, + .shift = 31, + .width = 1, + }, + .rst = { + .reg_off = ANACTRL_PCIEPLL_CTRL0, + .shift = 29, + .width = 1, + }, + .init_regs = t7_pcie_pll_init_regs, + .init_count = ARRAY_SIZE(t7_pcie_pll_init_regs), + }, + .hw.init = &(struct clk_init_data){ + .name = "t7_pcie_pll_dco", + .ops = &meson_clk_pcie_pll_ops, + .parent_data = &(const struct clk_parent_data) { + .fw_name = "in0", + }, + .num_parents = 1, + }, +}; + +static struct clk_fixed_factor t7_pcie_pll_dco_div2 = { + .mult = 1, + .div = 2, + .hw.init = &(struct clk_init_data){ + .name = "t7_pcie_pll_dco_div2", + .ops = &clk_fixed_factor_ops, + .parent_hws = (const struct clk_hw *[]) { + &t7_pcie_pll_dco.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_pcie_pll_od = { + .data = &(struct clk_regmap_div_data){ + .offset = ANACTRL_PCIEPLL_CTRL0, + .shift = 16, + .width = 5, + .flags = CLK_DIVIDER_ONE_BASED | + CLK_DIVIDER_ALLOW_ZERO, + }, + .hw.init = &(struct clk_init_data){ + .name = "t7_pcie_pll_od", + .ops = &clk_regmap_divider_ops, + .parent_hws = (const struct clk_hw *[]) { + &t7_pcie_pll_dco_div2.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_fixed_factor t7_pcie_pll = { + .mult = 1, + .div = 2, + .hw.init = &(struct clk_init_data){ + .name = "t7_pcie_pll", + .ops = &clk_fixed_factor_ops, + .parent_hws = (const struct clk_hw *[]) { + &t7_pcie_pll_od.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_fixed_factor t7_mpll_prediv = { + .mult = 1, + .div = 2, + .hw.init = &(struct clk_init_data){ + .name = "t7_mpll_prediv", + .ops = &clk_fixed_factor_ops, + .parent_data = &(const struct clk_parent_data) { + .fw_name = "in0", + }, + .num_parents = 1, + }, +}; + +static const struct reg_sequence t7_mpll0_init_regs[] = { + { .reg = ANACTRL_MPLL_CTRL2, .def = 0x40000033 } +}; + +static struct clk_regmap t7_mpll0_div = { + .data = &(struct meson_clk_mpll_data){ + .sdm = { + .reg_off = ANACTRL_MPLL_CTRL1, + .shift = 0, + .width = 14, + }, + .sdm_en = { + .reg_off = ANACTRL_MPLL_CTRL1, + .shift = 30, + .width = 1, + }, + .n2 = { + .reg_off = ANACTRL_MPLL_CTRL1, + .shift = 20, + .width = 9, + }, + .ssen = { + .reg_off = ANACTRL_MPLL_CTRL1, + .shift = 29, + .width = 1, + }, + .init_regs = t7_mpll0_init_regs, + .init_count = ARRAY_SIZE(t7_mpll0_init_regs), + }, + .hw.init = &(struct clk_init_data){ + .name = "t7_mpll0_div", + .ops = &meson_clk_mpll_ops, + .parent_hws = (const struct clk_hw *[]) { + &t7_mpll_prediv.hw + }, + .num_parents = 1, + }, +}; + +static struct clk_regmap t7_mpll0 = { + .data = &(struct clk_regmap_gate_data){ + .offset = ANACTRL_MPLL_CTRL1, + .bit_idx = 31, + }, + .hw.init = &(struct clk_init_data){ + .name = "t7_mpll0", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { &t7_mpll0_div.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static const struct reg_sequence t7_mpll1_init_regs[] = { + { .reg = ANACTRL_MPLL_CTRL4, .def = 0x40000033 } +}; + +static struct clk_regmap t7_mpll1_div = { + .data = &(struct meson_clk_mpll_data){ + .sdm = { + .reg_off = ANACTRL_MPLL_CTRL3, + .shift = 0, + .width = 14, + }, + .sdm_en = { + .reg_off = ANACTRL_MPLL_CTRL3, + .shift = 30, + .width = 1, + }, + .n2 = { + .reg_off = ANACTRL_MPLL_CTRL3, + .shift = 20, + .width = 9, + }, + .ssen = { + .reg_off = ANACTRL_MPLL_CTRL3, + .shift = 29, + .width = 1, + }, + .init_regs = t7_mpll1_init_regs, + .init_count = ARRAY_SIZE(t7_mpll1_init_regs), + }, + .hw.init = &(struct clk_init_data){ + .name = "t7_mpll1_div", + .ops = &meson_clk_mpll_ops, + .parent_hws = (const struct clk_hw *[]) { + &t7_mpll_prediv.hw + }, + .num_parents = 1, + }, +}; + +static struct clk_regmap t7_mpll1 = { + .data = &(struct clk_regmap_gate_data){ + .offset = ANACTRL_MPLL_CTRL3, + .bit_idx = 31, + }, + .hw.init = &(struct clk_init_data){ + .name = "t7_mpll1", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { &t7_mpll1_div.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static const struct reg_sequence t7_mpll2_init_regs[] = { + { .reg = ANACTRL_MPLL_CTRL6, .def = 0x40000033 } +}; + +static struct clk_regmap t7_mpll2_div = { + .data = &(struct meson_clk_mpll_data){ + .sdm = { + .reg_off = ANACTRL_MPLL_CTRL5, + .shift = 0, + .width = 14, + }, + .sdm_en = { + .reg_off = ANACTRL_MPLL_CTRL5, + .shift = 30, + .width = 1, + }, + .n2 = { + .reg_off = ANACTRL_MPLL_CTRL5, + .shift = 20, + .width = 9, + }, + .ssen = { + .reg_off = ANACTRL_MPLL_CTRL5, + .shift = 29, + .width = 1, + }, + .init_regs = t7_mpll2_init_regs, + .init_count = ARRAY_SIZE(t7_mpll2_init_regs), + }, + .hw.init = &(struct clk_init_data){ + .name = "t7_mpll2_div", + .ops = &meson_clk_mpll_ops, + .parent_hws = (const struct clk_hw *[]) { + &t7_mpll_prediv.hw + }, + .num_parents = 1, + }, +}; + +static struct clk_regmap t7_mpll2 = { + .data = &(struct clk_regmap_gate_data){ + .offset = ANACTRL_MPLL_CTRL5, + .bit_idx = 31, + }, + .hw.init = &(struct clk_init_data){ + .name = "t7_mpll2", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { &t7_mpll2_div.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static const struct reg_sequence t7_mpll3_init_regs[] = { + { .reg = ANACTRL_MPLL_CTRL8, .def = 0x40000033 } +}; + +static struct clk_regmap t7_mpll3_div = { + .data = &(struct meson_clk_mpll_data){ + .sdm = { + .reg_off = ANACTRL_MPLL_CTRL7, + .shift = 0, + .width = 14, + }, + .sdm_en = { + .reg_off = ANACTRL_MPLL_CTRL7, + .shift = 30, + .width = 1, + }, + .n2 = { + .reg_off = ANACTRL_MPLL_CTRL7, + .shift = 20, + .width = 9, + }, + .ssen = { + .reg_off = ANACTRL_MPLL_CTRL7, + .shift = 29, + .width = 1, + }, + .init_regs = t7_mpll3_init_regs, + .init_count = ARRAY_SIZE(t7_mpll3_init_regs), + }, + .hw.init = &(struct clk_init_data){ + .name = "t7_mpll3_div", + .ops = &meson_clk_mpll_ops, + .parent_hws = (const struct clk_hw *[]) { + &t7_mpll_prediv.hw + }, + .num_parents = 1, + }, +}; + +static struct clk_regmap t7_mpll3 = { + .data = &(struct clk_regmap_gate_data){ + .offset = ANACTRL_MPLL_CTRL7, + .bit_idx = 31, + }, + .hw.init = &(struct clk_init_data){ + .name = "t7_mpll3", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { &t7_mpll3_div.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static const struct reg_sequence t7_hdmi_init_regs[] = { + { .reg = ANACTRL_HDMIPLL_CTRL1, .def = 0x00000000 }, + { .reg = ANACTRL_HDMIPLL_CTRL2, .def = 0x00000000 }, + { .reg = ANACTRL_HDMIPLL_CTRL3, .def = 0x6a28dc00 }, + { .reg = ANACTRL_HDMIPLL_CTRL4, .def = 0x65771290 }, + { .reg = ANACTRL_HDMIPLL_CTRL5, .def = 0x39272000 }, + { .reg = ANACTRL_HDMIPLL_CTRL6, .def = 0x56540000 } +}; + +static struct clk_regmap t7_hdmi_pll_dco = { + .data = &(struct meson_clk_pll_data){ + .en = { + .reg_off = ANACTRL_HDMIPLL_CTRL0, + .shift = 28, + .width = 1, + }, + .m = { + .reg_off = ANACTRL_HDMIPLL_CTRL0, + .shift = 0, + .width = 9, + }, + .n = { + .reg_off = ANACTRL_HDMIPLL_CTRL0, + .shift = 10, + .width = 5, + }, + .l = { + .reg_off = ANACTRL_HDMIPLL_CTRL0, + .shift = 31, + .width = 1, + }, + .rst = { + .reg_off = ANACTRL_HDMIPLL_CTRL0, + .shift = 29, + .width = 1, + }, + .range = &t7_media_pll_mult_range, + .init_regs = t7_hdmi_init_regs, + .init_count = ARRAY_SIZE(t7_hdmi_init_regs), + }, + .hw.init = &(struct clk_init_data){ + .name = "t7_hdmi_pll_dco", + .ops = &meson_clk_pll_ops, + .parent_data = (const struct clk_parent_data []) { + { .fw_name = "in0", } + }, + .num_parents = 1, + }, +}; + +static struct clk_regmap t7_hdmi_pll_od = { + .data = &(struct clk_regmap_div_data){ + .offset = ANACTRL_HDMIPLL_CTRL0, + .shift = 16, + .width = 4, + .flags = CLK_DIVIDER_POWER_OF_TWO, + }, + .hw.init = &(struct clk_init_data){ + .name = "t7_hdmi_pll_od", + .ops = &clk_regmap_divider_ops, + .parent_hws = (const struct clk_hw *[]) { + &t7_hdmi_pll_dco.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_hdmi_pll = { + .data = &(struct clk_regmap_div_data){ + .offset = ANACTRL_HDMIPLL_CTRL0, + .shift = 20, + .width = 2, + .flags = CLK_DIVIDER_POWER_OF_TWO, + }, + .hw.init = &(struct clk_init_data){ + .name = "t7_hdmi_pll", + .ops = &clk_regmap_divider_ops, + .parent_hws = (const struct clk_hw *[]) { + &t7_hdmi_pll_od.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static const struct pll_mult_range t7_mclk_pll_mult_range = { + .min = 67, + .max = 133, +}; + +static const struct reg_sequence t7_mclk_init_regs[] = { + { .reg = ANACTRL_MCLK_PLL_CNTL1, .def = 0x1470500f }, + { .reg = ANACTRL_MCLK_PLL_CNTL2, .def = 0x00023041 }, + { .reg = ANACTRL_MCLK_PLL_CNTL3, .def = 0x18180000 }, + { .reg = ANACTRL_MCLK_PLL_CNTL4, .def = 0x00180303 }, + { .reg = ANACTRL_MCLK_PLL_CNTL2, .def = 0x00023001, .delay_us = 20 } +}; + +static struct clk_regmap t7_mclk_pll_dco = { + .data = &(struct meson_clk_pll_data){ + .en = { + .reg_off = ANACTRL_MCLK_PLL_CNTL0, + .shift = 28, + .width = 1, + }, + .m = { + .reg_off = ANACTRL_MCLK_PLL_CNTL0, + .shift = 0, + .width = 8, + }, + .n = { + .reg_off = ANACTRL_MCLK_PLL_CNTL0, + .shift = 16, + .width = 5, + }, + .l = { + .reg_off = ANACTRL_MCLK_PLL_CNTL0, + .shift = 31, + .width = 1, + }, + .rst = { + .reg_off = ANACTRL_MCLK_PLL_CNTL0, + .shift = 29, + .width = 1, + }, + .range = &t7_mclk_pll_mult_range, + .init_regs = t7_mclk_init_regs, + .init_count = ARRAY_SIZE(t7_mclk_init_regs), + }, + .hw.init = &(struct clk_init_data){ + .name = "t7_mclk_pll_dco", + .ops = &meson_clk_pll_ops, + .parent_data = &(const struct clk_parent_data) { + .fw_name = "in0", + }, + .num_parents = 1, + }, +}; + +/* max div is 16 */ +static const struct clk_div_table t7_mclk_div[] = { + { .val = 0, .div = 1 }, + { .val = 1, .div = 2 }, + { .val = 2, .div = 4 }, + { .val = 3, .div = 8 }, + { .val = 4, .div = 16 }, + { /* sentinel */ } +}; + +static struct clk_regmap t7_mclk_pre_od = { + .data = &(struct clk_regmap_div_data){ + .offset = ANACTRL_MCLK_PLL_CNTL0, + .shift = 12, + .width = 3, + .table = t7_mclk_div, + }, + .hw.init = &(struct clk_init_data){ + .name = "t7_mclk_pre_od", + .ops = &clk_regmap_divider_ops, + .parent_hws = (const struct clk_hw *[]) { + &t7_mclk_pll_dco.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_mclk_pll = { + .data = &(struct clk_regmap_div_data){ + .offset = ANACTRL_MCLK_PLL_CNTL4, + .shift = 16, + .width = 5, + .flags = CLK_DIVIDER_ONE_BASED, + }, + .hw.init = &(struct clk_init_data){ + .name = "t7_mclk_pll", + .ops = &clk_regmap_divider_ops, + .parent_hws = (const struct clk_hw *[]) { + &t7_mclk_pre_od.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_mclk_0_sel = { + .data = &(struct clk_regmap_mux_data){ + .offset = ANACTRL_MCLK_PLL_CNTL4, + .mask = 0x3, + .shift = 4, + }, + .hw.init = &(struct clk_init_data){ + .name = "t7_mclk_0_sel", + .ops = &clk_regmap_mux_ops, + .parent_data = (const struct clk_parent_data []) { + { .hw = &t7_mclk_pll.hw }, + { .fw_name = "in1", }, + { .fw_name = "in2", }, + }, + .num_parents = 3, + }, +}; + +static struct clk_fixed_factor t7_mclk_0_div2 = { + .mult = 1, + .div = 2, + .hw.init = &(struct clk_init_data){ + .name = "t7_mclk_0_div2", + .ops = &clk_fixed_factor_ops, + .parent_hws = (const struct clk_hw *[]) { &t7_mclk_0_sel.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_mclk_0_pre = { + .data = &(struct clk_regmap_gate_data){ + .offset = ANACTRL_MCLK_PLL_CNTL4, + .bit_idx = 2, + }, + .hw.init = &(struct clk_init_data) { + .name = "t7_mclk_0_pre", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &t7_mclk_0_div2.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_mclk_0 = { + .data = &(struct clk_regmap_gate_data){ + .offset = ANACTRL_MCLK_PLL_CNTL4, + .bit_idx = 0, + }, + .hw.init = &(struct clk_init_data) { + .name = "t7_mclk_0", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &t7_mclk_0_pre.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_mclk_1_sel = { + .data = &(struct clk_regmap_mux_data){ + .offset = ANACTRL_MCLK_PLL_CNTL4, + .mask = 0x3, + .shift = 12, + }, + .hw.init = &(struct clk_init_data){ + .name = "t7_mclk_1_sel", + .ops = &clk_regmap_mux_ops, + .parent_data = (const struct clk_parent_data []) { + { .hw = &t7_mclk_pll.hw }, + { .fw_name = "in1", }, + { .fw_name = "in2", }, + }, + .num_parents = 3, + }, +}; + +static struct clk_fixed_factor t7_mclk_1_div2 = { + .mult = 1, + .div = 2, + .hw.init = &(struct clk_init_data){ + .name = "t7_mclk_1_div2", + .ops = &clk_fixed_factor_ops, + .parent_hws = (const struct clk_hw *[]) { &t7_mclk_1_sel.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_mclk_1_pre = { + .data = &(struct clk_regmap_gate_data){ + .offset = ANACTRL_MCLK_PLL_CNTL4, + .bit_idx = 10, + }, + .hw.init = &(struct clk_init_data) { + .name = "t7_mclk_1_pre", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &t7_mclk_1_div2.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_mclk_1 = { + .data = &(struct clk_regmap_gate_data){ + .offset = ANACTRL_MCLK_PLL_CNTL4, + .bit_idx = 8, + }, + .hw.init = &(struct clk_init_data) { + .name = "t7_mclk_1", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &t7_mclk_1_pre.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_hw *t7_gp0_hw_clks[] = { + [CLKID_GP0_PLL_DCO] = &t7_gp0_pll_dco.hw, + [CLKID_GP0_PLL] = &t7_gp0_pll.hw, +}; + +static struct clk_hw *t7_gp1_hw_clks[] = { + [CLKID_GP1_PLL_DCO] = &t7_gp1_pll_dco.hw, + [CLKID_GP1_PLL] = &t7_gp1_pll.hw, +}; + +static struct clk_hw *t7_hifi_hw_clks[] = { + [CLKID_HIFI_PLL_DCO] = &t7_hifi_pll_dco.hw, + [CLKID_HIFI_PLL] = &t7_hifi_pll.hw, +}; + +static struct clk_hw *t7_pcie_hw_clks[] = { + [CLKID_PCIE_PLL_DCO] = &t7_pcie_pll_dco.hw, + [CLKID_PCIE_PLL_DCO_DIV2] = &t7_pcie_pll_dco_div2.hw, + [CLKID_PCIE_PLL_OD] = &t7_pcie_pll_od.hw, + [CLKID_PCIE_PLL] = &t7_pcie_pll.hw, +}; + +static struct clk_hw *t7_mpll_hw_clks[] = { + [CLKID_MPLL_PREDIV] = &t7_mpll_prediv.hw, + [CLKID_MPLL0_DIV] = &t7_mpll0_div.hw, + [CLKID_MPLL0] = &t7_mpll0.hw, + [CLKID_MPLL1_DIV] = &t7_mpll1_div.hw, + [CLKID_MPLL1] = &t7_mpll1.hw, + [CLKID_MPLL2_DIV] = &t7_mpll2_div.hw, + [CLKID_MPLL2] = &t7_mpll2.hw, + [CLKID_MPLL3_DIV] = &t7_mpll3_div.hw, + [CLKID_MPLL3] = &t7_mpll3.hw, +}; + +static struct clk_hw *t7_hdmi_hw_clks[] = { + [CLKID_HDMI_PLL_DCO] = &t7_hdmi_pll_dco.hw, + [CLKID_HDMI_PLL_OD] = &t7_hdmi_pll_od.hw, + [CLKID_HDMI_PLL] = &t7_hdmi_pll.hw, +}; + +static struct clk_hw *t7_mclk_hw_clks[] = { + [CLKID_MCLK_PLL_DCO] = &t7_mclk_pll_dco.hw, + [CLKID_MCLK_PRE] = &t7_mclk_pre_od.hw, + [CLKID_MCLK_PLL] = &t7_mclk_pll.hw, + [CLKID_MCLK_0_SEL] = &t7_mclk_0_sel.hw, + [CLKID_MCLK_0_DIV2] = &t7_mclk_0_div2.hw, + [CLKID_MCLK_0_PRE] = &t7_mclk_0_pre.hw, + [CLKID_MCLK_0] = &t7_mclk_0.hw, + [CLKID_MCLK_1_SEL] = &t7_mclk_1_sel.hw, + [CLKID_MCLK_1_DIV2] = &t7_mclk_1_div2.hw, + [CLKID_MCLK_1_PRE] = &t7_mclk_1_pre.hw, + [CLKID_MCLK_1] = &t7_mclk_1.hw, +}; + +static struct clk_regmap *const t7_gp0_regmaps[] = { + &t7_gp0_pll_dco, + &t7_gp0_pll, +}; + +static struct clk_regmap *const t7_gp1_regmaps[] = { + &t7_gp1_pll_dco, + &t7_gp1_pll, +}; + +static struct clk_regmap *const t7_hifi_regmaps[] = { + &t7_hifi_pll_dco, + &t7_hifi_pll, +}; + +static struct clk_regmap *const t7_pcie_regmaps[] = { + &t7_pcie_pll_dco, + &t7_pcie_pll_od, +}; + +static struct clk_regmap *const t7_mpll_regmaps[] = { + &t7_mpll0_div, + &t7_mpll0, + &t7_mpll1_div, + &t7_mpll1, + &t7_mpll2_div, + &t7_mpll2, + &t7_mpll3_div, + &t7_mpll3, +}; + +static struct clk_regmap *const t7_hdmi_regmaps[] = { + &t7_hdmi_pll_dco, + &t7_hdmi_pll_od, + &t7_hdmi_pll, +}; + +static struct clk_regmap *const t7_mclk_regmaps[] = { + &t7_mclk_pll_dco, + &t7_mclk_pre_od, + &t7_mclk_pll, + &t7_mclk_0_sel, + &t7_mclk_0_pre, + &t7_mclk_0, + &t7_mclk_1_sel, + &t7_mclk_1_pre, + &t7_mclk_1, +}; + +static const struct regmap_config t7_clkc_regmap_config = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, +}; + +static int amlogic_t7_pll_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + const struct meson_eeclkc_data *data; + void __iomem *base; + struct regmap *map; + int i, ret; + + data = of_device_get_match_data(&pdev->dev); + if (!data) + return -EINVAL; + + base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + map = devm_regmap_init_mmio(dev, base, &t7_clkc_regmap_config); + if (IS_ERR(map)) + return PTR_ERR(map); + + /* Populate regmap for the regmap backed clocks */ + for (i = 0; i < data->regmap_clk_num; i++) + data->regmap_clks[i]->map = map; + + if (data->init_count) + regmap_multi_reg_write(map, data->init_regs, + data->init_count); + + /* Register clocks */ + for (i = 0; i < data->hw_clks.num; i++) { + ret = devm_clk_hw_register(dev, data->hw_clks.hws[i]); + if (ret) + return ret; + } + + return devm_of_clk_add_hw_provider(dev, meson_clk_hw_get, (void *)&data->hw_clks); +} + +static const struct meson_eeclkc_data t7_gp0_data = { + .regmap_clks = t7_gp0_regmaps, + .regmap_clk_num = ARRAY_SIZE(t7_gp0_regmaps), + .hw_clks = { + .hws = t7_gp0_hw_clks, + .num = ARRAY_SIZE(t7_gp0_hw_clks), + }, +}; + +static const struct meson_eeclkc_data t7_gp1_data = { + .regmap_clks = t7_gp1_regmaps, + .regmap_clk_num = ARRAY_SIZE(t7_gp1_regmaps), + .hw_clks = { + .hws = t7_gp1_hw_clks, + .num = ARRAY_SIZE(t7_gp1_hw_clks), + }, +}; + +static const struct meson_eeclkc_data t7_hifi_data = { + .regmap_clks = t7_hifi_regmaps, + .regmap_clk_num = ARRAY_SIZE(t7_hifi_regmaps), + .hw_clks = { + .hws = t7_hifi_hw_clks, + .num = ARRAY_SIZE(t7_hifi_hw_clks), + }, +}; + +static const struct meson_eeclkc_data t7_pcie_data = { + .regmap_clks = t7_pcie_regmaps, + .regmap_clk_num = ARRAY_SIZE(t7_pcie_regmaps), + .hw_clks = { + .hws = t7_pcie_hw_clks, + .num = ARRAY_SIZE(t7_pcie_hw_clks), + }, +}; + +static const struct reg_sequence mpll_init_regs[] = { + { .reg = ANACTRL_MPLL_CTRL0, .def = 0x00000543 } +}; + +static const struct meson_eeclkc_data t7_mpll_data = { + .regmap_clks = t7_mpll_regmaps, + .regmap_clk_num = ARRAY_SIZE(t7_mpll_regmaps), + .init_regs = mpll_init_regs, + .init_count = ARRAY_SIZE(mpll_init_regs), + .hw_clks = { + .hws = t7_mpll_hw_clks, + .num = ARRAY_SIZE(t7_mpll_hw_clks), + }, +}; + +static const struct meson_eeclkc_data t7_hdmi_data = { + .regmap_clks = t7_hdmi_regmaps, + .regmap_clk_num = ARRAY_SIZE(t7_hdmi_regmaps), + .hw_clks = { + .hws = t7_hdmi_hw_clks, + .num = ARRAY_SIZE(t7_hdmi_hw_clks), + }, +}; + +static const struct meson_eeclkc_data t7_mclk_data = { + .regmap_clks = t7_mclk_regmaps, + .regmap_clk_num = ARRAY_SIZE(t7_mclk_regmaps), + .hw_clks = { + .hws = t7_mclk_hw_clks, + .num = ARRAY_SIZE(t7_mclk_hw_clks), + }, +}; + +static const struct of_device_id t7_pll_clkc_match_table[] = { + { + .compatible = "amlogic,t7-pll-gp0", + .data = &t7_gp0_data, + }, + { + .compatible = "amlogic,t7-pll-gp1", + .data = &t7_gp1_data, + }, + { + .compatible = "amlogic,t7-pll-hifi", + .data = &t7_hifi_data, + }, + { + .compatible = "amlogic,t7-pll-pcie", + .data = &t7_pcie_data, + }, + { + .compatible = "amlogic,t7-mpll", + .data = &t7_mpll_data, + }, + { + .compatible = "amlogic,t7-pll-hdmi", + .data = &t7_hdmi_data, + }, + { + .compatible = "amlogic,t7-pll-mclk", + .data = &t7_mclk_data, + }, + {} +}; +MODULE_DEVICE_TABLE(of, t7_pll_clkc_match_table); + +static struct platform_driver t7_pll_clkc_driver = { + .probe = amlogic_t7_pll_probe, + .driver = { + .name = "t7-pll-clkc", + .of_match_table = t7_pll_clkc_match_table, + }, +}; + +MODULE_DESCRIPTION("Amlogic T7 PLL Clock Controller driver"); +module_platform_driver(t7_pll_clkc_driver); +MODULE_AUTHOR("Jian Hu <jian.hu@amlogic.com>"); +MODULE_LICENSE("GPL"); +MODULE_IMPORT_NS("CLK_MESON"); -- 2.47.1 ^ permalink raw reply related [flat|nested] 19+ messages in thread
* Re: [PATCH v3 4/6] clk: meson: t7: add support for the T7 SoC PLL clock 2025-05-09 7:48 ` [PATCH v3 4/6] clk: meson: t7: add support for the T7 SoC PLL clock Jian Hu @ 2025-05-14 7:52 ` Jerome Brunet 2025-06-12 13:02 ` Jian Hu 0 siblings, 1 reply; 19+ messages in thread From: Jerome Brunet @ 2025-05-14 7:52 UTC (permalink / raw) To: Jian Hu Cc: Xianwei Zhao, Chuan Liu, Neil Armstrong, Kevin Hilman, Stephen Boyd, Michael Turquette, Dmitry Rokosov, robh+dt, Rob Herring, devicetree, linux-clk, linux-amlogic, linux-kernel, linux-arm-kernel On Fri 09 May 2025 at 07:48, Jian Hu <jian.hu@amlogic.com> wrote: > Add PLL clock controller driver for the Amlogic T7 SoC family. > > Signed-off-by: Jian Hu <jian.hu@amlogic.com> > --- > drivers/clk/meson/Kconfig | 14 + > drivers/clk/meson/Makefile | 1 + > drivers/clk/meson/t7-pll.c | 1193 ++++++++++++++++++++++++++++++++++++ > 3 files changed, 1208 insertions(+) > create mode 100644 drivers/clk/meson/t7-pll.c > > diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig > index be2e3a5f8336..8bb4f26a86ed 100644 > --- a/drivers/clk/meson/Kconfig > +++ b/drivers/clk/meson/Kconfig > @@ -202,4 +202,18 @@ config COMMON_CLK_S4_PERIPHERALS > help > Support for the peripherals clock controller on Amlogic S805X2 and S905Y4 > devices, AKA S4. Say Y if you want S4 peripherals clock controller to work. > + > +config COMMON_CLK_T7_PLL > + tristate "Amlogic T7 SoC PLL controller support" > + depends on ARM64 > + default y > + select COMMON_CLK_MESON_REGMAP > + select COMMON_CLK_MESON_CLKC_UTILS > + select COMMON_CLK_MESON_PLL > + imply COMMON_CLK_SCMI > + help > + Support for the PLL clock controller on Amlogic A311D2 based > + device, AKA T7. PLLs are required by most peripheral to operate > + Say Y if you are a T7 based device. > + > endmenu > diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile > index bc56a47931c1..646257694c34 100644 > --- a/drivers/clk/meson/Makefile > +++ b/drivers/clk/meson/Makefile > @@ -27,3 +27,4 @@ obj-$(CONFIG_COMMON_CLK_G12A) += g12a.o g12a-aoclk.o > obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o meson8-ddr.o > obj-$(CONFIG_COMMON_CLK_S4_PLL) += s4-pll.o > obj-$(CONFIG_COMMON_CLK_S4_PERIPHERALS) += s4-peripherals.o > +obj-$(CONFIG_COMMON_CLK_T7_PLL) += t7-pll.o > diff --git a/drivers/clk/meson/t7-pll.c b/drivers/clk/meson/t7-pll.c > new file mode 100644 > index 000000000000..d2ec45d5e783 > --- /dev/null > +++ b/drivers/clk/meson/t7-pll.c > @@ -0,0 +1,1193 @@ > +// SPDX-License-Identifier: (GPL-2.0-only OR MIT) > +/* > + * Copyright (C) 2024 Amlogic, Inc. All rights reserved. > + * Author: Jian Hu <jian.hu@amlogic.com> > + */ > + > +#include <linux/clk-provider.h> > +#include <linux/platform_device.h> > +#include "clk-regmap.h" > +#include "clk-pll.h" > +#include "clk-mpll.h" > +#include "meson-clkc-utils.h" > +#include "meson-eeclk.h" > +#include <dt-bindings/clock/amlogic,t7-pll-clkc.h> > + > +#define ANACTRL_GP0PLL_CTRL0 0x00 > +#define ANACTRL_GP0PLL_CTRL1 0x04 > +#define ANACTRL_GP0PLL_CTRL2 0x08 > +#define ANACTRL_GP0PLL_CTRL3 0x0c > +#define ANACTRL_GP0PLL_CTRL4 0x10 > +#define ANACTRL_GP0PLL_CTRL5 0x14 > +#define ANACTRL_GP0PLL_CTRL6 0x18 > +#define ANACTRL_GP0PLL_STS 0x1c > + > +#define ANACTRL_GP1PLL_CTRL0 0x00 > +#define ANACTRL_GP1PLL_CTRL1 0x04 > +#define ANACTRL_GP1PLL_CTRL2 0x08 > +#define ANACTRL_GP1PLL_CTRL3 0x0c > +#define ANACTRL_GP1PLL_STS 0x1c > + > +#define ANACTRL_HIFIPLL_CTRL0 0x00 > +#define ANACTRL_HIFIPLL_CTRL1 0x04 > +#define ANACTRL_HIFIPLL_CTRL2 0x08 > +#define ANACTRL_HIFIPLL_CTRL3 0x0c > +#define ANACTRL_HIFIPLL_CTRL4 0x10 > +#define ANACTRL_HIFIPLL_CTRL5 0x14 > +#define ANACTRL_HIFIPLL_CTRL6 0x18 > +#define ANACTRL_HIFIPLL_STS 0x1c > + > +#define ANACTRL_PCIEPLL_CTRL0 0x00 > +#define ANACTRL_PCIEPLL_CTRL1 0x04 > +#define ANACTRL_PCIEPLL_CTRL2 0x08 > +#define ANACTRL_PCIEPLL_CTRL3 0x0c > +#define ANACTRL_PCIEPLL_CTRL4 0x10 > +#define ANACTRL_PCIEPLL_CTRL5 0x14 > +#define ANACTRL_PCIEPLL_STS 0x18 > + > +#define ANACTRL_MPLL_CTRL0 0x00 > +#define ANACTRL_MPLL_CTRL1 0x04 > +#define ANACTRL_MPLL_CTRL2 0x08 > +#define ANACTRL_MPLL_CTRL3 0x0c > +#define ANACTRL_MPLL_CTRL4 0x10 > +#define ANACTRL_MPLL_CTRL5 0x14 > +#define ANACTRL_MPLL_CTRL6 0x18 > +#define ANACTRL_MPLL_CTRL7 0x1c > +#define ANACTRL_MPLL_CTRL8 0x20 > +#define ANACTRL_MPLL_STS 0x24 > + > +#define ANACTRL_HDMIPLL_CTRL0 0x00 > +#define ANACTRL_HDMIPLL_CTRL1 0x04 > +#define ANACTRL_HDMIPLL_CTRL2 0x08 > +#define ANACTRL_HDMIPLL_CTRL3 0x0c > +#define ANACTRL_HDMIPLL_CTRL4 0x10 > +#define ANACTRL_HDMIPLL_CTRL5 0x14 > +#define ANACTRL_HDMIPLL_CTRL6 0x18 > +#define ANACTRL_HDMIPLL_STS 0x1c > + > +#define ANACTRL_MCLK_PLL_CNTL0 0x00 > +#define ANACTRL_MCLK_PLL_CNTL1 0x04 > +#define ANACTRL_MCLK_PLL_CNTL2 0x08 > +#define ANACTRL_MCLK_PLL_CNTL3 0x0c > +#define ANACTRL_MCLK_PLL_CNTL4 0x10 > +#define ANACTRL_MCLK_PLL_STS 0x14 > + > +static const struct pll_mult_range t7_media_pll_mult_range = { > + .min = 125, > + .max = 250, > +}; > + > +static const struct reg_sequence t7_gp0_init_regs[] = { > + { .reg = ANACTRL_GP0PLL_CTRL1, .def = 0x00000000 }, > + { .reg = ANACTRL_GP0PLL_CTRL2, .def = 0x00000000 }, > + { .reg = ANACTRL_GP0PLL_CTRL3, .def = 0x48681c00 }, > + { .reg = ANACTRL_GP0PLL_CTRL4, .def = 0x88770290 }, > + { .reg = ANACTRL_GP0PLL_CTRL5, .def = 0x3927200a }, > + { .reg = ANACTRL_GP0PLL_CTRL6, .def = 0x56540000 }, > +}; > + > +static struct clk_regmap t7_gp0_pll_dco = { > + .data = &(struct meson_clk_pll_data){ > + .en = { > + .reg_off = ANACTRL_GP0PLL_CTRL0, > + .shift = 28, > + .width = 1, > + }, > + .m = { > + .reg_off = ANACTRL_GP0PLL_CTRL0, > + .shift = 0, > + .width = 8, > + }, > + .n = { > + .reg_off = ANACTRL_GP0PLL_CTRL0, > + .shift = 10, > + .width = 5, > + }, > + .l = { > + .reg_off = ANACTRL_GP0PLL_STS, > + .shift = 31, > + .width = 1, > + }, > + .rst = { > + .reg_off = ANACTRL_GP0PLL_CTRL0, > + .shift = 29, > + .width = 1, > + }, > + .range = &t7_media_pll_mult_range, > + .init_regs = t7_gp0_init_regs, > + .init_count = ARRAY_SIZE(t7_gp0_init_regs), > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "t7_gp0_pll_dco", > + .ops = &meson_clk_pll_ops, > + .parent_data = &(const struct clk_parent_data) { > + .fw_name = "in0", > + }, > + .num_parents = 1, > + }, > +}; > + > +static struct clk_regmap t7_gp0_pll = { > + .data = &(struct clk_regmap_div_data){ > + .offset = ANACTRL_GP0PLL_CTRL0, > + .shift = 16, > + .width = 3, > + .flags = CLK_DIVIDER_POWER_OF_TWO, > + }, > + .hw.init = &(struct clk_init_data) { > + .name = "t7_gp0_pll", > + .ops = &clk_regmap_divider_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &t7_gp0_pll_dco.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +/* > + * The gp1 pll IP is different with gp0 pll, the PLL DCO range is > + * 1.6GHZ - 3.2GHZ, and the reg_sequence is short > + */ > +static const struct pll_mult_range t7_gp1_pll_mult_range = { > + .min = 67, > + .max = 133, > +}; > + > +static const struct reg_sequence t7_gp1_init_regs[] = { > + { .reg = ANACTRL_GP1PLL_CTRL1, .def = 0x1420500f }, > + { .reg = ANACTRL_GP1PLL_CTRL2, .def = 0x00023001 }, > + { .reg = ANACTRL_GP1PLL_CTRL3, .def = 0x00000000 }, > +}; > + > +static struct clk_regmap t7_gp1_pll_dco = { > + .data = &(struct meson_clk_pll_data){ > + .en = { > + .reg_off = ANACTRL_GP1PLL_CTRL0, > + .shift = 28, > + .width = 1, > + }, > + .m = { > + .reg_off = ANACTRL_GP1PLL_CTRL0, > + .shift = 0, > + .width = 8, > + }, > + .n = { > + .reg_off = ANACTRL_GP1PLL_CTRL0, > + .shift = 16, > + .width = 5, > + }, > + .l = { > + .reg_off = ANACTRL_GP1PLL_STS, > + .shift = 31, > + .width = 1, > + }, > + .rst = { > + .reg_off = ANACTRL_GP1PLL_CTRL0, > + .shift = 29, > + .width = 1, > + }, > + .range = &t7_gp1_pll_mult_range, > + .init_regs = t7_gp1_init_regs, > + .init_count = ARRAY_SIZE(t7_gp1_init_regs), > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "t7_gp1_pll_dco", > + .ops = &meson_clk_pll_ops, > + .parent_data = &(const struct clk_parent_data) { > + .fw_name = "in0", > + }, > + .num_parents = 1, > + }, > +}; > + > +static struct clk_regmap t7_gp1_pll = { > + .data = &(struct clk_regmap_div_data){ > + .offset = ANACTRL_GP1PLL_CTRL0, > + .shift = 12, > + .width = 3, > + .flags = CLK_DIVIDER_POWER_OF_TWO, > + }, > + .hw.init = &(struct clk_init_data) { > + .name = "t7_gp1_pll", > + .ops = &clk_regmap_divider_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &t7_gp1_pll_dco.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static const struct reg_sequence t7_hifi_init_regs[] = { > + { .reg = ANACTRL_HIFIPLL_CTRL1, .def = 0x00000000 }, > + { .reg = ANACTRL_HIFIPLL_CTRL2, .def = 0x00000000 }, > + { .reg = ANACTRL_HIFIPLL_CTRL3, .def = 0x6a285c00 }, > + { .reg = ANACTRL_HIFIPLL_CTRL4, .def = 0x65771290 }, > + { .reg = ANACTRL_HIFIPLL_CTRL5, .def = 0x3927200a }, > + { .reg = ANACTRL_HIFIPLL_CTRL6, .def = 0x56540000 } > +}; > + > +static struct clk_regmap t7_hifi_pll_dco = { > + .data = &(struct meson_clk_pll_data){ > + .en = { > + .reg_off = ANACTRL_HIFIPLL_CTRL0, > + .shift = 28, > + .width = 1, > + }, > + .m = { > + .reg_off = ANACTRL_HIFIPLL_CTRL0, > + .shift = 0, > + .width = 8, > + }, > + .n = { > + .reg_off = ANACTRL_HIFIPLL_CTRL0, > + .shift = 10, > + .width = 5, > + }, > + .l = { > + .reg_off = ANACTRL_HIFIPLL_STS, > + .shift = 31, > + .width = 1, > + }, > + .rst = { > + .reg_off = ANACTRL_HIFIPLL_CTRL0, > + .shift = 29, > + .width = 1, > + }, > + .range = &t7_media_pll_mult_range, > + .init_regs = t7_hifi_init_regs, > + .init_count = ARRAY_SIZE(t7_hifi_init_regs), > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "t7_hifi_pll_dco", > + .ops = &meson_clk_pll_ops, > + .parent_data = &(const struct clk_parent_data) { > + .fw_name = "in0", > + }, > + .num_parents = 1, > + }, > +}; > + > +static struct clk_regmap t7_hifi_pll = { > + .data = &(struct clk_regmap_div_data){ > + .offset = ANACTRL_HIFIPLL_CTRL0, > + .shift = 16, > + .width = 2, > + .flags = CLK_DIVIDER_POWER_OF_TWO, > + }, > + .hw.init = &(struct clk_init_data) { > + .name = "t7_hifi_pll", > + .ops = &clk_regmap_divider_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &t7_hifi_pll_dco.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +/* > + * The T7 PCIE PLL is fined tuned to deliver a very precise > + * 100MHz reference clock for the PCIe Analog PHY, and thus requires > + * a strict register sequence to enable the PLL. > + */ It looks to me like something we are dragging from soc to soc that could be folded in the regular PLL with some effort ... just saying. > +static const struct reg_sequence t7_pcie_pll_init_regs[] = { > + { .reg = ANACTRL_PCIEPLL_CTRL0, .def = 0x200c04c8 }, > + { .reg = ANACTRL_PCIEPLL_CTRL0, .def = 0x300c04c8 }, > + { .reg = ANACTRL_PCIEPLL_CTRL1, .def = 0x30000000 }, > + { .reg = ANACTRL_PCIEPLL_CTRL2, .def = 0x00001100 }, > + { .reg = ANACTRL_PCIEPLL_CTRL3, .def = 0x10058e00 }, > + { .reg = ANACTRL_PCIEPLL_CTRL4, .def = 0x000100c0 }, > + { .reg = ANACTRL_PCIEPLL_CTRL5, .def = 0x68000048 }, > + { .reg = ANACTRL_PCIEPLL_CTRL5, .def = 0x68000068, .delay_us = 20 }, > + { .reg = ANACTRL_PCIEPLL_CTRL4, .def = 0x008100c0, .delay_us = 20 }, > + { .reg = ANACTRL_PCIEPLL_CTRL0, .def = 0x340c04c8 }, > + { .reg = ANACTRL_PCIEPLL_CTRL0, .def = 0x140c04c8, .delay_us = 20 }, > + { .reg = ANACTRL_PCIEPLL_CTRL2, .def = 0x00001000 } > +}; > + > +static struct clk_regmap t7_pcie_pll_dco = { > + .data = &(struct meson_clk_pll_data){ > + .en = { > + .reg_off = ANACTRL_PCIEPLL_CTRL0, > + .shift = 28, > + .width = 1, > + }, > + .m = { > + .reg_off = ANACTRL_PCIEPLL_CTRL0, > + .shift = 0, > + .width = 8, > + }, > + .n = { > + .reg_off = ANACTRL_PCIEPLL_CTRL0, > + .shift = 10, > + .width = 5, > + }, > + .l = { > + .reg_off = ANACTRL_PCIEPLL_CTRL0, > + .shift = 31, > + .width = 1, > + }, > + .rst = { > + .reg_off = ANACTRL_PCIEPLL_CTRL0, > + .shift = 29, > + .width = 1, > + }, > + .init_regs = t7_pcie_pll_init_regs, > + .init_count = ARRAY_SIZE(t7_pcie_pll_init_regs), > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "t7_pcie_pll_dco", > + .ops = &meson_clk_pcie_pll_ops, > + .parent_data = &(const struct clk_parent_data) { > + .fw_name = "in0", > + }, > + .num_parents = 1, > + }, > +}; > + > +static struct clk_fixed_factor t7_pcie_pll_dco_div2 = { > + .mult = 1, > + .div = 2, > + .hw.init = &(struct clk_init_data){ > + .name = "t7_pcie_pll_dco_div2", > + .ops = &clk_fixed_factor_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &t7_pcie_pll_dco.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap t7_pcie_pll_od = { > + .data = &(struct clk_regmap_div_data){ > + .offset = ANACTRL_PCIEPLL_CTRL0, > + .shift = 16, > + .width = 5, > + .flags = CLK_DIVIDER_ONE_BASED | > + CLK_DIVIDER_ALLOW_ZERO, What's the behaviour of the divider on zero then ? > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "t7_pcie_pll_od", > + .ops = &clk_regmap_divider_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &t7_pcie_pll_dco_div2.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_fixed_factor t7_pcie_pll = { > + .mult = 1, > + .div = 2, > + .hw.init = &(struct clk_init_data){ > + .name = "t7_pcie_pll", > + .ops = &clk_fixed_factor_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &t7_pcie_pll_od.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_fixed_factor t7_mpll_prediv = { > + .mult = 1, > + .div = 2, > + .hw.init = &(struct clk_init_data){ > + .name = "t7_mpll_prediv", > + .ops = &clk_fixed_factor_ops, > + .parent_data = &(const struct clk_parent_data) { > + .fw_name = "in0", > + }, > + .num_parents = 1, > + }, > +}; > + > +static const struct reg_sequence t7_mpll0_init_regs[] = { > + { .reg = ANACTRL_MPLL_CTRL2, .def = 0x40000033 } > +}; > + > +static struct clk_regmap t7_mpll0_div = { > + .data = &(struct meson_clk_mpll_data){ > + .sdm = { > + .reg_off = ANACTRL_MPLL_CTRL1, > + .shift = 0, > + .width = 14, > + }, > + .sdm_en = { > + .reg_off = ANACTRL_MPLL_CTRL1, > + .shift = 30, > + .width = 1, > + }, > + .n2 = { > + .reg_off = ANACTRL_MPLL_CTRL1, > + .shift = 20, > + .width = 9, > + }, > + .ssen = { > + .reg_off = ANACTRL_MPLL_CTRL1, > + .shift = 29, > + .width = 1, > + }, > + .init_regs = t7_mpll0_init_regs, > + .init_count = ARRAY_SIZE(t7_mpll0_init_regs), > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "t7_mpll0_div", > + .ops = &meson_clk_mpll_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &t7_mpll_prediv.hw > + }, > + .num_parents = 1, > + }, > +}; > + > +static struct clk_regmap t7_mpll0 = { > + .data = &(struct clk_regmap_gate_data){ > + .offset = ANACTRL_MPLL_CTRL1, > + .bit_idx = 31, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "t7_mpll0", > + .ops = &clk_regmap_gate_ops, > + .parent_hws = (const struct clk_hw *[]) { &t7_mpll0_div.hw }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static const struct reg_sequence t7_mpll1_init_regs[] = { > + { .reg = ANACTRL_MPLL_CTRL4, .def = 0x40000033 } > +}; > + > +static struct clk_regmap t7_mpll1_div = { > + .data = &(struct meson_clk_mpll_data){ > + .sdm = { > + .reg_off = ANACTRL_MPLL_CTRL3, > + .shift = 0, > + .width = 14, > + }, > + .sdm_en = { > + .reg_off = ANACTRL_MPLL_CTRL3, > + .shift = 30, > + .width = 1, > + }, > + .n2 = { > + .reg_off = ANACTRL_MPLL_CTRL3, > + .shift = 20, > + .width = 9, > + }, > + .ssen = { > + .reg_off = ANACTRL_MPLL_CTRL3, > + .shift = 29, > + .width = 1, > + }, > + .init_regs = t7_mpll1_init_regs, > + .init_count = ARRAY_SIZE(t7_mpll1_init_regs), > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "t7_mpll1_div", > + .ops = &meson_clk_mpll_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &t7_mpll_prediv.hw > + }, > + .num_parents = 1, > + }, > +}; > + > +static struct clk_regmap t7_mpll1 = { > + .data = &(struct clk_regmap_gate_data){ > + .offset = ANACTRL_MPLL_CTRL3, > + .bit_idx = 31, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "t7_mpll1", > + .ops = &clk_regmap_gate_ops, > + .parent_hws = (const struct clk_hw *[]) { &t7_mpll1_div.hw }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static const struct reg_sequence t7_mpll2_init_regs[] = { > + { .reg = ANACTRL_MPLL_CTRL6, .def = 0x40000033 } > +}; > + > +static struct clk_regmap t7_mpll2_div = { > + .data = &(struct meson_clk_mpll_data){ > + .sdm = { > + .reg_off = ANACTRL_MPLL_CTRL5, > + .shift = 0, > + .width = 14, > + }, > + .sdm_en = { > + .reg_off = ANACTRL_MPLL_CTRL5, > + .shift = 30, > + .width = 1, > + }, > + .n2 = { > + .reg_off = ANACTRL_MPLL_CTRL5, > + .shift = 20, > + .width = 9, > + }, > + .ssen = { > + .reg_off = ANACTRL_MPLL_CTRL5, > + .shift = 29, > + .width = 1, > + }, > + .init_regs = t7_mpll2_init_regs, > + .init_count = ARRAY_SIZE(t7_mpll2_init_regs), > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "t7_mpll2_div", > + .ops = &meson_clk_mpll_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &t7_mpll_prediv.hw > + }, > + .num_parents = 1, > + }, > +}; > + > +static struct clk_regmap t7_mpll2 = { > + .data = &(struct clk_regmap_gate_data){ > + .offset = ANACTRL_MPLL_CTRL5, > + .bit_idx = 31, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "t7_mpll2", > + .ops = &clk_regmap_gate_ops, > + .parent_hws = (const struct clk_hw *[]) { &t7_mpll2_div.hw }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static const struct reg_sequence t7_mpll3_init_regs[] = { > + { .reg = ANACTRL_MPLL_CTRL8, .def = 0x40000033 } > +}; > + > +static struct clk_regmap t7_mpll3_div = { > + .data = &(struct meson_clk_mpll_data){ > + .sdm = { > + .reg_off = ANACTRL_MPLL_CTRL7, > + .shift = 0, > + .width = 14, > + }, > + .sdm_en = { > + .reg_off = ANACTRL_MPLL_CTRL7, > + .shift = 30, > + .width = 1, > + }, > + .n2 = { > + .reg_off = ANACTRL_MPLL_CTRL7, > + .shift = 20, > + .width = 9, > + }, > + .ssen = { > + .reg_off = ANACTRL_MPLL_CTRL7, > + .shift = 29, > + .width = 1, > + }, > + .init_regs = t7_mpll3_init_regs, > + .init_count = ARRAY_SIZE(t7_mpll3_init_regs), > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "t7_mpll3_div", > + .ops = &meson_clk_mpll_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &t7_mpll_prediv.hw > + }, > + .num_parents = 1, > + }, > +}; > + > +static struct clk_regmap t7_mpll3 = { > + .data = &(struct clk_regmap_gate_data){ > + .offset = ANACTRL_MPLL_CTRL7, > + .bit_idx = 31, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "t7_mpll3", > + .ops = &clk_regmap_gate_ops, > + .parent_hws = (const struct clk_hw *[]) { &t7_mpll3_div.hw }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static const struct reg_sequence t7_hdmi_init_regs[] = { > + { .reg = ANACTRL_HDMIPLL_CTRL1, .def = 0x00000000 }, > + { .reg = ANACTRL_HDMIPLL_CTRL2, .def = 0x00000000 }, > + { .reg = ANACTRL_HDMIPLL_CTRL3, .def = 0x6a28dc00 }, > + { .reg = ANACTRL_HDMIPLL_CTRL4, .def = 0x65771290 }, > + { .reg = ANACTRL_HDMIPLL_CTRL5, .def = 0x39272000 }, > + { .reg = ANACTRL_HDMIPLL_CTRL6, .def = 0x56540000 } > +}; > + > +static struct clk_regmap t7_hdmi_pll_dco = { > + .data = &(struct meson_clk_pll_data){ > + .en = { > + .reg_off = ANACTRL_HDMIPLL_CTRL0, > + .shift = 28, > + .width = 1, > + }, > + .m = { > + .reg_off = ANACTRL_HDMIPLL_CTRL0, > + .shift = 0, > + .width = 9, > + }, > + .n = { > + .reg_off = ANACTRL_HDMIPLL_CTRL0, > + .shift = 10, > + .width = 5, > + }, > + .l = { > + .reg_off = ANACTRL_HDMIPLL_CTRL0, > + .shift = 31, > + .width = 1, > + }, > + .rst = { > + .reg_off = ANACTRL_HDMIPLL_CTRL0, > + .shift = 29, > + .width = 1, > + }, > + .range = &t7_media_pll_mult_range, > + .init_regs = t7_hdmi_init_regs, > + .init_count = ARRAY_SIZE(t7_hdmi_init_regs), > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "t7_hdmi_pll_dco", > + .ops = &meson_clk_pll_ops, > + .parent_data = (const struct clk_parent_data []) { > + { .fw_name = "in0", } > + }, > + .num_parents = 1, > + }, > +}; > + > +static struct clk_regmap t7_hdmi_pll_od = { > + .data = &(struct clk_regmap_div_data){ > + .offset = ANACTRL_HDMIPLL_CTRL0, > + .shift = 16, > + .width = 4, > + .flags = CLK_DIVIDER_POWER_OF_TWO, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "t7_hdmi_pll_od", > + .ops = &clk_regmap_divider_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &t7_hdmi_pll_dco.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap t7_hdmi_pll = { > + .data = &(struct clk_regmap_div_data){ > + .offset = ANACTRL_HDMIPLL_CTRL0, > + .shift = 20, > + .width = 2, > + .flags = CLK_DIVIDER_POWER_OF_TWO, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "t7_hdmi_pll", > + .ops = &clk_regmap_divider_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &t7_hdmi_pll_od.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static const struct pll_mult_range t7_mclk_pll_mult_range = { > + .min = 67, > + .max = 133, > +}; > + > +static const struct reg_sequence t7_mclk_init_regs[] = { > + { .reg = ANACTRL_MCLK_PLL_CNTL1, .def = 0x1470500f }, > + { .reg = ANACTRL_MCLK_PLL_CNTL2, .def = 0x00023041 }, > + { .reg = ANACTRL_MCLK_PLL_CNTL3, .def = 0x18180000 }, > + { .reg = ANACTRL_MCLK_PLL_CNTL4, .def = 0x00180303 }, > + { .reg = ANACTRL_MCLK_PLL_CNTL2, .def = 0x00023001, .delay_us = 20 } What is this bit that you need to clear after the init sequence ? Any chance this maps to something the driver already has ? Doing init really belong on the init sequence - done at init only ? > +}; > + > +static struct clk_regmap t7_mclk_pll_dco = { > + .data = &(struct meson_clk_pll_data){ > + .en = { > + .reg_off = ANACTRL_MCLK_PLL_CNTL0, > + .shift = 28, > + .width = 1, > + }, > + .m = { > + .reg_off = ANACTRL_MCLK_PLL_CNTL0, > + .shift = 0, > + .width = 8, > + }, > + .n = { > + .reg_off = ANACTRL_MCLK_PLL_CNTL0, > + .shift = 16, > + .width = 5, > + }, > + .l = { > + .reg_off = ANACTRL_MCLK_PLL_CNTL0, > + .shift = 31, > + .width = 1, > + }, > + .rst = { > + .reg_off = ANACTRL_MCLK_PLL_CNTL0, > + .shift = 29, > + .width = 1, > + }, > + .range = &t7_mclk_pll_mult_range, > + .init_regs = t7_mclk_init_regs, > + .init_count = ARRAY_SIZE(t7_mclk_init_regs), > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "t7_mclk_pll_dco", > + .ops = &meson_clk_pll_ops, > + .parent_data = &(const struct clk_parent_data) { > + .fw_name = "in0", > + }, > + .num_parents = 1, > + }, > +}; > + > +/* max div is 16 */ > +static const struct clk_div_table t7_mclk_div[] = { > + { .val = 0, .div = 1 }, > + { .val = 1, .div = 2 }, > + { .val = 2, .div = 4 }, > + { .val = 3, .div = 8 }, > + { .val = 4, .div = 16 }, > + { /* sentinel */ } > +}; > + > +static struct clk_regmap t7_mclk_pre_od = { > + .data = &(struct clk_regmap_div_data){ > + .offset = ANACTRL_MCLK_PLL_CNTL0, > + .shift = 12, > + .width = 3, > + .table = t7_mclk_div, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "t7_mclk_pre_od", > + .ops = &clk_regmap_divider_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &t7_mclk_pll_dco.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap t7_mclk_pll = { > + .data = &(struct clk_regmap_div_data){ > + .offset = ANACTRL_MCLK_PLL_CNTL4, > + .shift = 16, > + .width = 5, > + .flags = CLK_DIVIDER_ONE_BASED, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "t7_mclk_pll", > + .ops = &clk_regmap_divider_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &t7_mclk_pre_od.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap t7_mclk_0_sel = { > + .data = &(struct clk_regmap_mux_data){ > + .offset = ANACTRL_MCLK_PLL_CNTL4, > + .mask = 0x3, > + .shift = 4, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "t7_mclk_0_sel", > + .ops = &clk_regmap_mux_ops, > + .parent_data = (const struct clk_parent_data []) { > + { .hw = &t7_mclk_pll.hw }, > + { .fw_name = "in1", }, > + { .fw_name = "in2", }, > + }, > + .num_parents = 3, > + }, > +}; > + > +static struct clk_fixed_factor t7_mclk_0_div2 = { > + .mult = 1, > + .div = 2, > + .hw.init = &(struct clk_init_data){ > + .name = "t7_mclk_0_div2", > + .ops = &clk_fixed_factor_ops, > + .parent_hws = (const struct clk_hw *[]) { &t7_mclk_0_sel.hw }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap t7_mclk_0_pre = { > + .data = &(struct clk_regmap_gate_data){ > + .offset = ANACTRL_MCLK_PLL_CNTL4, > + .bit_idx = 2, > + }, > + .hw.init = &(struct clk_init_data) { > + .name = "t7_mclk_0_pre", > + .ops = &clk_regmap_gate_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &t7_mclk_0_div2.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap t7_mclk_0 = { > + .data = &(struct clk_regmap_gate_data){ > + .offset = ANACTRL_MCLK_PLL_CNTL4, > + .bit_idx = 0, > + }, > + .hw.init = &(struct clk_init_data) { > + .name = "t7_mclk_0", > + .ops = &clk_regmap_gate_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &t7_mclk_0_pre.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap t7_mclk_1_sel = { > + .data = &(struct clk_regmap_mux_data){ > + .offset = ANACTRL_MCLK_PLL_CNTL4, > + .mask = 0x3, > + .shift = 12, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "t7_mclk_1_sel", > + .ops = &clk_regmap_mux_ops, > + .parent_data = (const struct clk_parent_data []) { > + { .hw = &t7_mclk_pll.hw }, > + { .fw_name = "in1", }, > + { .fw_name = "in2", }, > + }, > + .num_parents = 3, > + }, > +}; > + > +static struct clk_fixed_factor t7_mclk_1_div2 = { > + .mult = 1, > + .div = 2, > + .hw.init = &(struct clk_init_data){ > + .name = "t7_mclk_1_div2", > + .ops = &clk_fixed_factor_ops, > + .parent_hws = (const struct clk_hw *[]) { &t7_mclk_1_sel.hw }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap t7_mclk_1_pre = { > + .data = &(struct clk_regmap_gate_data){ > + .offset = ANACTRL_MCLK_PLL_CNTL4, > + .bit_idx = 10, > + }, > + .hw.init = &(struct clk_init_data) { > + .name = "t7_mclk_1_pre", > + .ops = &clk_regmap_gate_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &t7_mclk_1_div2.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap t7_mclk_1 = { > + .data = &(struct clk_regmap_gate_data){ > + .offset = ANACTRL_MCLK_PLL_CNTL4, > + .bit_idx = 8, > + }, > + .hw.init = &(struct clk_init_data) { > + .name = "t7_mclk_1", > + .ops = &clk_regmap_gate_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &t7_mclk_1_pre.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_hw *t7_gp0_hw_clks[] = { > + [CLKID_GP0_PLL_DCO] = &t7_gp0_pll_dco.hw, > + [CLKID_GP0_PLL] = &t7_gp0_pll.hw, > +}; > + > +static struct clk_hw *t7_gp1_hw_clks[] = { > + [CLKID_GP1_PLL_DCO] = &t7_gp1_pll_dco.hw, > + [CLKID_GP1_PLL] = &t7_gp1_pll.hw, > +}; > + > +static struct clk_hw *t7_hifi_hw_clks[] = { > + [CLKID_HIFI_PLL_DCO] = &t7_hifi_pll_dco.hw, > + [CLKID_HIFI_PLL] = &t7_hifi_pll.hw, > +}; > + > +static struct clk_hw *t7_pcie_hw_clks[] = { > + [CLKID_PCIE_PLL_DCO] = &t7_pcie_pll_dco.hw, > + [CLKID_PCIE_PLL_DCO_DIV2] = &t7_pcie_pll_dco_div2.hw, > + [CLKID_PCIE_PLL_OD] = &t7_pcie_pll_od.hw, > + [CLKID_PCIE_PLL] = &t7_pcie_pll.hw, > +}; > + > +static struct clk_hw *t7_mpll_hw_clks[] = { > + [CLKID_MPLL_PREDIV] = &t7_mpll_prediv.hw, > + [CLKID_MPLL0_DIV] = &t7_mpll0_div.hw, > + [CLKID_MPLL0] = &t7_mpll0.hw, > + [CLKID_MPLL1_DIV] = &t7_mpll1_div.hw, > + [CLKID_MPLL1] = &t7_mpll1.hw, > + [CLKID_MPLL2_DIV] = &t7_mpll2_div.hw, > + [CLKID_MPLL2] = &t7_mpll2.hw, > + [CLKID_MPLL3_DIV] = &t7_mpll3_div.hw, > + [CLKID_MPLL3] = &t7_mpll3.hw, > +}; > + > +static struct clk_hw *t7_hdmi_hw_clks[] = { > + [CLKID_HDMI_PLL_DCO] = &t7_hdmi_pll_dco.hw, > + [CLKID_HDMI_PLL_OD] = &t7_hdmi_pll_od.hw, > + [CLKID_HDMI_PLL] = &t7_hdmi_pll.hw, > +}; > + > +static struct clk_hw *t7_mclk_hw_clks[] = { > + [CLKID_MCLK_PLL_DCO] = &t7_mclk_pll_dco.hw, > + [CLKID_MCLK_PRE] = &t7_mclk_pre_od.hw, > + [CLKID_MCLK_PLL] = &t7_mclk_pll.hw, > + [CLKID_MCLK_0_SEL] = &t7_mclk_0_sel.hw, > + [CLKID_MCLK_0_DIV2] = &t7_mclk_0_div2.hw, > + [CLKID_MCLK_0_PRE] = &t7_mclk_0_pre.hw, > + [CLKID_MCLK_0] = &t7_mclk_0.hw, > + [CLKID_MCLK_1_SEL] = &t7_mclk_1_sel.hw, > + [CLKID_MCLK_1_DIV2] = &t7_mclk_1_div2.hw, > + [CLKID_MCLK_1_PRE] = &t7_mclk_1_pre.hw, > + [CLKID_MCLK_1] = &t7_mclk_1.hw, > +}; > + > +static struct clk_regmap *const t7_gp0_regmaps[] = { > + &t7_gp0_pll_dco, > + &t7_gp0_pll, > +}; > + > +static struct clk_regmap *const t7_gp1_regmaps[] = { > + &t7_gp1_pll_dco, > + &t7_gp1_pll, > +}; > + > +static struct clk_regmap *const t7_hifi_regmaps[] = { > + &t7_hifi_pll_dco, > + &t7_hifi_pll, > +}; > + > +static struct clk_regmap *const t7_pcie_regmaps[] = { > + &t7_pcie_pll_dco, > + &t7_pcie_pll_od, > +}; > + > +static struct clk_regmap *const t7_mpll_regmaps[] = { > + &t7_mpll0_div, > + &t7_mpll0, > + &t7_mpll1_div, > + &t7_mpll1, > + &t7_mpll2_div, > + &t7_mpll2, > + &t7_mpll3_div, > + &t7_mpll3, > +}; > + > +static struct clk_regmap *const t7_hdmi_regmaps[] = { > + &t7_hdmi_pll_dco, > + &t7_hdmi_pll_od, > + &t7_hdmi_pll, > +}; > + > +static struct clk_regmap *const t7_mclk_regmaps[] = { > + &t7_mclk_pll_dco, > + &t7_mclk_pre_od, > + &t7_mclk_pll, > + &t7_mclk_0_sel, > + &t7_mclk_0_pre, > + &t7_mclk_0, > + &t7_mclk_1_sel, > + &t7_mclk_1_pre, > + &t7_mclk_1, > +}; > + > +static const struct regmap_config t7_clkc_regmap_config = { > + .reg_bits = 32, > + .val_bits = 32, > + .reg_stride = 4, > +}; > + > +static int amlogic_t7_pll_probe(struct platform_device *pdev) > +{ > + struct device *dev = &pdev->dev; > + const struct meson_eeclkc_data *data; > + void __iomem *base; > + struct regmap *map; > + int i, ret; > + > + data = of_device_get_match_data(&pdev->dev); > + if (!data) > + return -EINVAL; > + > + base = devm_platform_ioremap_resource(pdev, 0); > + if (IS_ERR(base)) > + return PTR_ERR(base); > + > + map = devm_regmap_init_mmio(dev, base, &t7_clkc_regmap_config); > + if (IS_ERR(map)) > + return PTR_ERR(map); > + > + /* Populate regmap for the regmap backed clocks */ > + for (i = 0; i < data->regmap_clk_num; i++) > + data->regmap_clks[i]->map = map; > + > + if (data->init_count) > + regmap_multi_reg_write(map, data->init_regs, > + data->init_count); > + > + /* Register clocks */ > + for (i = 0; i < data->hw_clks.num; i++) { > + ret = devm_clk_hw_register(dev, data->hw_clks.hws[i]); > + if (ret) > + return ret; > + } > + > + return devm_of_clk_add_hw_provider(dev, meson_clk_hw_get, (void *)&data->hw_clks); > +} > + > +static const struct meson_eeclkc_data t7_gp0_data = { > + .regmap_clks = t7_gp0_regmaps, > + .regmap_clk_num = ARRAY_SIZE(t7_gp0_regmaps), > + .hw_clks = { > + .hws = t7_gp0_hw_clks, > + .num = ARRAY_SIZE(t7_gp0_hw_clks), > + }, > +}; > + > +static const struct meson_eeclkc_data t7_gp1_data = { > + .regmap_clks = t7_gp1_regmaps, > + .regmap_clk_num = ARRAY_SIZE(t7_gp1_regmaps), > + .hw_clks = { > + .hws = t7_gp1_hw_clks, > + .num = ARRAY_SIZE(t7_gp1_hw_clks), > + }, > +}; > + > +static const struct meson_eeclkc_data t7_hifi_data = { > + .regmap_clks = t7_hifi_regmaps, > + .regmap_clk_num = ARRAY_SIZE(t7_hifi_regmaps), > + .hw_clks = { > + .hws = t7_hifi_hw_clks, > + .num = ARRAY_SIZE(t7_hifi_hw_clks), > + }, > +}; > + > +static const struct meson_eeclkc_data t7_pcie_data = { > + .regmap_clks = t7_pcie_regmaps, > + .regmap_clk_num = ARRAY_SIZE(t7_pcie_regmaps), > + .hw_clks = { > + .hws = t7_pcie_hw_clks, > + .num = ARRAY_SIZE(t7_pcie_hw_clks), > + }, > +}; > + > +static const struct reg_sequence mpll_init_regs[] = { > + { .reg = ANACTRL_MPLL_CTRL0, .def = 0x00000543 } > +}; > + > +static const struct meson_eeclkc_data t7_mpll_data = { > + .regmap_clks = t7_mpll_regmaps, > + .regmap_clk_num = ARRAY_SIZE(t7_mpll_regmaps), > + .init_regs = mpll_init_regs, > + .init_count = ARRAY_SIZE(mpll_init_regs), > + .hw_clks = { > + .hws = t7_mpll_hw_clks, > + .num = ARRAY_SIZE(t7_mpll_hw_clks), > + }, > +}; > + > +static const struct meson_eeclkc_data t7_hdmi_data = { > + .regmap_clks = t7_hdmi_regmaps, > + .regmap_clk_num = ARRAY_SIZE(t7_hdmi_regmaps), > + .hw_clks = { > + .hws = t7_hdmi_hw_clks, > + .num = ARRAY_SIZE(t7_hdmi_hw_clks), > + }, > +}; > + > +static const struct meson_eeclkc_data t7_mclk_data = { > + .regmap_clks = t7_mclk_regmaps, > + .regmap_clk_num = ARRAY_SIZE(t7_mclk_regmaps), > + .hw_clks = { > + .hws = t7_mclk_hw_clks, > + .num = ARRAY_SIZE(t7_mclk_hw_clks), > + }, > +}; > + > +static const struct of_device_id t7_pll_clkc_match_table[] = { > + { > + .compatible = "amlogic,t7-pll-gp0", > + .data = &t7_gp0_data, > + }, > + { }, { please > + .compatible = "amlogic,t7-pll-gp1", > + .data = &t7_gp1_data, > + }, > + { > + .compatible = "amlogic,t7-pll-hifi", > + .data = &t7_hifi_data, > + }, > + { > + .compatible = "amlogic,t7-pll-pcie", > + .data = &t7_pcie_data, > + }, > + { > + .compatible = "amlogic,t7-mpll", > + .data = &t7_mpll_data, > + }, > + { > + .compatible = "amlogic,t7-pll-hdmi", > + .data = &t7_hdmi_data, > + }, > + { > + .compatible = "amlogic,t7-pll-mclk", > + .data = &t7_mclk_data, > + }, > + {} > +}; > +MODULE_DEVICE_TABLE(of, t7_pll_clkc_match_table); > + > +static struct platform_driver t7_pll_clkc_driver = { > + .probe = amlogic_t7_pll_probe, > + .driver = { > + .name = "t7-pll-clkc", > + .of_match_table = t7_pll_clkc_match_table, > + }, > +}; > + > +MODULE_DESCRIPTION("Amlogic T7 PLL Clock Controller driver"); > +module_platform_driver(t7_pll_clkc_driver); > +MODULE_AUTHOR("Jian Hu <jian.hu@amlogic.com>"); > +MODULE_LICENSE("GPL"); > +MODULE_IMPORT_NS("CLK_MESON"); -- Jerome ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v3 4/6] clk: meson: t7: add support for the T7 SoC PLL clock 2025-05-14 7:52 ` Jerome Brunet @ 2025-06-12 13:02 ` Jian Hu 2025-06-16 16:27 ` Jerome Brunet 0 siblings, 1 reply; 19+ messages in thread From: Jian Hu @ 2025-06-12 13:02 UTC (permalink / raw) To: Jerome Brunet Cc: Xianwei Zhao, Chuan Liu, Neil Armstrong, Kevin Hilman, Stephen Boyd, Michael Turquette, Dmitry Rokosov, robh+dt, Rob Herring, devicetree, linux-clk, linux-amlogic, linux-kernel, linux-arm-kernel Hi, Jerome Thanks for your review. and sorry for late reply. On 2025/5/14 15:52, Jerome Brunet wrote: > [ EXTERNAL EMAIL ] > > On Fri 09 May 2025 at 07:48, Jian Hu<jian.hu@amlogic.com> wrote: > >> Add PLL clock controller driver for the Amlogic T7 SoC family. >> >> Signed-off-by: Jian Hu<jian.hu@amlogic.com> >> --- >> drivers/clk/meson/Kconfig | 14 + >> drivers/clk/meson/Makefile | 1 + >> drivers/clk/meson/t7-pll.c | 1193 ++++++++++++++++++++++++++++++++++++ >> 3 files changed, 1208 insertions(+) >> create mode 100644 drivers/clk/meson/t7-pll.c >> >> diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig >> index be2e3a5f8336..8bb4f26a86ed 100644 >> --- a/drivers/clk/meson/Kconfig >> +++ b/drivers/clk/meson/Kconfig >> @@ -202,4 +202,18 @@ config COMMON_CLK_S4_PERIPHERALS >> help >> Support for the peripherals clock controller on Amlogic S805X2 and S905Y4 >> devices, AKA S4. Say Y if you want S4 peripherals clock controller to work. >> + >> +config COMMON_CLK_T7_PLL >> + tristate "Amlogic T7 SoC PLL controller support" >> + depends on ARM64 >> + default y >> + select COMMON_CLK_MESON_REGMAP >> + select COMMON_CLK_MESON_CLKC_UTILS >> + select COMMON_CLK_MESON_PLL >> + imply COMMON_CLK_SCMI >> + help >> + Support for the PLL clock controller on Amlogic A311D2 based >> + device, AKA T7. PLLs are required by most peripheral to operate >> + Say Y if you are a T7 based device. >> + >> endmenu >> diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile >> index bc56a47931c1..646257694c34 100644 >> --- a/drivers/clk/meson/Makefile >> +++ b/drivers/clk/meson/Makefile >> @@ -27,3 +27,4 @@ obj-$(CONFIG_COMMON_CLK_G12A) += g12a.o g12a-aoclk.o >> obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o meson8-ddr.o >> obj-$(CONFIG_COMMON_CLK_S4_PLL) += s4-pll.o >> obj-$(CONFIG_COMMON_CLK_S4_PERIPHERALS) += s4-peripherals.o >> +obj-$(CONFIG_COMMON_CLK_T7_PLL) += t7-pll.o >> diff --git a/drivers/clk/meson/t7-pll.c b/drivers/clk/meson/t7-pll.c >> new file mode 100644 >> index 000000000000..d2ec45d5e783 >> --- /dev/null >> +++ b/drivers/clk/meson/t7-pll.c >> @@ -0,0 +1,1193 @@ >> +// SPDX-License-Identifier: (GPL-2.0-only OR MIT) >> +/* >> + * Copyright (C) 2024 Amlogic, Inc. All rights reserved. >> + * Author: Jian Hu<jian.hu@amlogic.com> >> + */ >> + >> +#include <linux/clk-provider.h> >> +#include <linux/platform_device.h> >> +#include "clk-regmap.h" >> +#include "clk-pll.h" >> +#include "clk-mpll.h" >> +#include "meson-clkc-utils.h" >> +#include "meson-eeclk.h" >> +#include <dt-bindings/clock/amlogic,t7-pll-clkc.h> >> + >> +#define ANACTRL_GP0PLL_CTRL0 0x00 >> +#define ANACTRL_GP0PLL_CTRL1 0x04 >> +#define ANACTRL_GP0PLL_CTRL2 0x08 >> +#define ANACTRL_GP0PLL_CTRL3 0x0c >> +#define ANACTRL_GP0PLL_CTRL4 0x10 >> +#define ANACTRL_GP0PLL_CTRL5 0x14 >> +#define ANACTRL_GP0PLL_CTRL6 0x18 >> +#define ANACTRL_GP0PLL_STS 0x1c >> + >> +#define ANACTRL_GP1PLL_CTRL0 0x00 >> +#define ANACTRL_GP1PLL_CTRL1 0x04 >> +#define ANACTRL_GP1PLL_CTRL2 0x08 >> +#define ANACTRL_GP1PLL_CTRL3 0x0c >> +#define ANACTRL_GP1PLL_STS 0x1c >> + >> +#define ANACTRL_HIFIPLL_CTRL0 0x00 >> +#define ANACTRL_HIFIPLL_CTRL1 0x04 >> +#define ANACTRL_HIFIPLL_CTRL2 0x08 >> +#define ANACTRL_HIFIPLL_CTRL3 0x0c >> +#define ANACTRL_HIFIPLL_CTRL4 0x10 >> +#define ANACTRL_HIFIPLL_CTRL5 0x14 >> +#define ANACTRL_HIFIPLL_CTRL6 0x18 >> +#define ANACTRL_HIFIPLL_STS 0x1c >> + >> +#define ANACTRL_PCIEPLL_CTRL0 0x00 >> +#define ANACTRL_PCIEPLL_CTRL1 0x04 >> +#define ANACTRL_PCIEPLL_CTRL2 0x08 >> +#define ANACTRL_PCIEPLL_CTRL3 0x0c >> +#define ANACTRL_PCIEPLL_CTRL4 0x10 >> +#define ANACTRL_PCIEPLL_CTRL5 0x14 >> +#define ANACTRL_PCIEPLL_STS 0x18 >> + >> +#define ANACTRL_MPLL_CTRL0 0x00 >> +#define ANACTRL_MPLL_CTRL1 0x04 >> +#define ANACTRL_MPLL_CTRL2 0x08 >> +#define ANACTRL_MPLL_CTRL3 0x0c >> +#define ANACTRL_MPLL_CTRL4 0x10 >> +#define ANACTRL_MPLL_CTRL5 0x14 >> +#define ANACTRL_MPLL_CTRL6 0x18 >> +#define ANACTRL_MPLL_CTRL7 0x1c >> +#define ANACTRL_MPLL_CTRL8 0x20 >> +#define ANACTRL_MPLL_STS 0x24 >> + >> +#define ANACTRL_HDMIPLL_CTRL0 0x00 >> +#define ANACTRL_HDMIPLL_CTRL1 0x04 >> +#define ANACTRL_HDMIPLL_CTRL2 0x08 >> +#define ANACTRL_HDMIPLL_CTRL3 0x0c >> +#define ANACTRL_HDMIPLL_CTRL4 0x10 >> +#define ANACTRL_HDMIPLL_CTRL5 0x14 >> +#define ANACTRL_HDMIPLL_CTRL6 0x18 >> +#define ANACTRL_HDMIPLL_STS 0x1c >> + >> +#define ANACTRL_MCLK_PLL_CNTL0 0x00 >> +#define ANACTRL_MCLK_PLL_CNTL1 0x04 >> +#define ANACTRL_MCLK_PLL_CNTL2 0x08 >> +#define ANACTRL_MCLK_PLL_CNTL3 0x0c >> +#define ANACTRL_MCLK_PLL_CNTL4 0x10 >> +#define ANACTRL_MCLK_PLL_STS 0x14 >> + >> +static const struct pll_mult_range t7_media_pll_mult_range = { >> + .min = 125, >> + .max = 250, >> +}; >> + >> +static const struct reg_sequence t7_gp0_init_regs[] = { >> + { .reg = ANACTRL_GP0PLL_CTRL1, .def = 0x00000000 }, >> + { .reg = ANACTRL_GP0PLL_CTRL2, .def = 0x00000000 }, >> + { .reg = ANACTRL_GP0PLL_CTRL3, .def = 0x48681c00 }, >> + { .reg = ANACTRL_GP0PLL_CTRL4, .def = 0x88770290 }, >> + { .reg = ANACTRL_GP0PLL_CTRL5, .def = 0x3927200a }, >> + { .reg = ANACTRL_GP0PLL_CTRL6, .def = 0x56540000 }, >> +}; >> + >> +static struct clk_regmap t7_gp0_pll_dco = { >> + .data = &(struct meson_clk_pll_data){ >> + .en = { >> + .reg_off = ANACTRL_GP0PLL_CTRL0, >> + .shift = 28, >> + .width = 1, >> + }, >> + .m = { >> + .reg_off = ANACTRL_GP0PLL_CTRL0, >> + .shift = 0, >> + .width = 8, >> + }, >> + .n = { >> + .reg_off = ANACTRL_GP0PLL_CTRL0, >> + .shift = 10, >> + .width = 5, >> + }, >> + .l = { >> + .reg_off = ANACTRL_GP0PLL_STS, >> + .shift = 31, >> + .width = 1, >> + }, >> + .rst = { >> + .reg_off = ANACTRL_GP0PLL_CTRL0, >> + .shift = 29, >> + .width = 1, >> + }, >> + .range = &t7_media_pll_mult_range, >> + .init_regs = t7_gp0_init_regs, >> + .init_count = ARRAY_SIZE(t7_gp0_init_regs), >> + }, >> + .hw.init = &(struct clk_init_data){ >> + .name = "t7_gp0_pll_dco", >> + .ops = &meson_clk_pll_ops, >> + .parent_data = &(const struct clk_parent_data) { >> + .fw_name = "in0", >> + }, >> + .num_parents = 1, >> + }, >> +}; >> + >> +static struct clk_regmap t7_gp0_pll = { >> + .data = &(struct clk_regmap_div_data){ >> + .offset = ANACTRL_GP0PLL_CTRL0, >> + .shift = 16, >> + .width = 3, >> + .flags = CLK_DIVIDER_POWER_OF_TWO, >> + }, >> + .hw.init = &(struct clk_init_data) { >> + .name = "t7_gp0_pll", >> + .ops = &clk_regmap_divider_ops, >> + .parent_hws = (const struct clk_hw *[]) { >> + &t7_gp0_pll_dco.hw >> + }, >> + .num_parents = 1, >> + .flags = CLK_SET_RATE_PARENT, >> + }, >> +}; >> + >> +/* >> + * The gp1 pll IP is different with gp0 pll, the PLL DCO range is >> + * 1.6GHZ - 3.2GHZ, and the reg_sequence is short >> + */ >> +static const struct pll_mult_range t7_gp1_pll_mult_range = { >> + .min = 67, >> + .max = 133, >> +}; >> + >> +static const struct reg_sequence t7_gp1_init_regs[] = { >> + { .reg = ANACTRL_GP1PLL_CTRL1, .def = 0x1420500f }, >> + { .reg = ANACTRL_GP1PLL_CTRL2, .def = 0x00023001 }, >> + { .reg = ANACTRL_GP1PLL_CTRL3, .def = 0x00000000 }, >> +}; >> + >> +static struct clk_regmap t7_gp1_pll_dco = { >> + .data = &(struct meson_clk_pll_data){ >> + .en = { >> + .reg_off = ANACTRL_GP1PLL_CTRL0, >> + .shift = 28, >> + .width = 1, >> + }, >> + .m = { >> + .reg_off = ANACTRL_GP1PLL_CTRL0, >> + .shift = 0, >> + .width = 8, >> + }, >> + .n = { >> + .reg_off = ANACTRL_GP1PLL_CTRL0, >> + .shift = 16, >> + .width = 5, >> + }, >> + .l = { >> + .reg_off = ANACTRL_GP1PLL_STS, >> + .shift = 31, >> + .width = 1, >> + }, >> + .rst = { >> + .reg_off = ANACTRL_GP1PLL_CTRL0, >> + .shift = 29, >> + .width = 1, >> + }, >> + .range = &t7_gp1_pll_mult_range, >> + .init_regs = t7_gp1_init_regs, >> + .init_count = ARRAY_SIZE(t7_gp1_init_regs), >> + }, >> + .hw.init = &(struct clk_init_data){ >> + .name = "t7_gp1_pll_dco", >> + .ops = &meson_clk_pll_ops, >> + .parent_data = &(const struct clk_parent_data) { >> + .fw_name = "in0", >> + }, >> + .num_parents = 1, >> + }, >> +}; >> + >> +static struct clk_regmap t7_gp1_pll = { >> + .data = &(struct clk_regmap_div_data){ >> + .offset = ANACTRL_GP1PLL_CTRL0, >> + .shift = 12, >> + .width = 3, >> + .flags = CLK_DIVIDER_POWER_OF_TWO, >> + }, >> + .hw.init = &(struct clk_init_data) { >> + .name = "t7_gp1_pll", >> + .ops = &clk_regmap_divider_ops, >> + .parent_hws = (const struct clk_hw *[]) { >> + &t7_gp1_pll_dco.hw >> + }, >> + .num_parents = 1, >> + .flags = CLK_SET_RATE_PARENT, >> + }, >> +}; >> + >> +static const struct reg_sequence t7_hifi_init_regs[] = { >> + { .reg = ANACTRL_HIFIPLL_CTRL1, .def = 0x00000000 }, >> + { .reg = ANACTRL_HIFIPLL_CTRL2, .def = 0x00000000 }, >> + { .reg = ANACTRL_HIFIPLL_CTRL3, .def = 0x6a285c00 }, >> + { .reg = ANACTRL_HIFIPLL_CTRL4, .def = 0x65771290 }, >> + { .reg = ANACTRL_HIFIPLL_CTRL5, .def = 0x3927200a }, >> + { .reg = ANACTRL_HIFIPLL_CTRL6, .def = 0x56540000 } >> +}; >> + >> +static struct clk_regmap t7_hifi_pll_dco = { >> + .data = &(struct meson_clk_pll_data){ >> + .en = { >> + .reg_off = ANACTRL_HIFIPLL_CTRL0, >> + .shift = 28, >> + .width = 1, >> + }, >> + .m = { >> + .reg_off = ANACTRL_HIFIPLL_CTRL0, >> + .shift = 0, >> + .width = 8, >> + }, >> + .n = { >> + .reg_off = ANACTRL_HIFIPLL_CTRL0, >> + .shift = 10, >> + .width = 5, >> + }, >> + .l = { >> + .reg_off = ANACTRL_HIFIPLL_STS, >> + .shift = 31, >> + .width = 1, >> + }, >> + .rst = { >> + .reg_off = ANACTRL_HIFIPLL_CTRL0, >> + .shift = 29, >> + .width = 1, >> + }, >> + .range = &t7_media_pll_mult_range, >> + .init_regs = t7_hifi_init_regs, >> + .init_count = ARRAY_SIZE(t7_hifi_init_regs), >> + }, >> + .hw.init = &(struct clk_init_data){ >> + .name = "t7_hifi_pll_dco", >> + .ops = &meson_clk_pll_ops, >> + .parent_data = &(const struct clk_parent_data) { >> + .fw_name = "in0", >> + }, >> + .num_parents = 1, >> + }, >> +}; >> + >> +static struct clk_regmap t7_hifi_pll = { >> + .data = &(struct clk_regmap_div_data){ >> + .offset = ANACTRL_HIFIPLL_CTRL0, >> + .shift = 16, >> + .width = 2, >> + .flags = CLK_DIVIDER_POWER_OF_TWO, >> + }, >> + .hw.init = &(struct clk_init_data) { >> + .name = "t7_hifi_pll", >> + .ops = &clk_regmap_divider_ops, >> + .parent_hws = (const struct clk_hw *[]) { >> + &t7_hifi_pll_dco.hw >> + }, >> + .num_parents = 1, >> + .flags = CLK_SET_RATE_PARENT, >> + }, >> +}; >> + >> +/* >> + * The T7 PCIE PLL is fined tuned to deliver a very precise >> + * 100MHz reference clock for the PCIe Analog PHY, and thus requires >> + * a strict register sequence to enable the PLL. >> + */ > It looks to me like something we are dragging from soc to soc that could > be folded in the regular PLL with some effort ... just saying. > >> +static const struct reg_sequence t7_pcie_pll_init_regs[] = { >> + { .reg = ANACTRL_PCIEPLL_CTRL0, .def = 0x200c04c8 }, >> + { .reg = ANACTRL_PCIEPLL_CTRL0, .def = 0x300c04c8 }, >> + { .reg = ANACTRL_PCIEPLL_CTRL1, .def = 0x30000000 }, >> + { .reg = ANACTRL_PCIEPLL_CTRL2, .def = 0x00001100 }, >> + { .reg = ANACTRL_PCIEPLL_CTRL3, .def = 0x10058e00 }, >> + { .reg = ANACTRL_PCIEPLL_CTRL4, .def = 0x000100c0 }, >> + { .reg = ANACTRL_PCIEPLL_CTRL5, .def = 0x68000048 }, >> + { .reg = ANACTRL_PCIEPLL_CTRL5, .def = 0x68000068, .delay_us = 20 }, >> + { .reg = ANACTRL_PCIEPLL_CTRL4, .def = 0x008100c0, .delay_us = 20 }, >> + { .reg = ANACTRL_PCIEPLL_CTRL0, .def = 0x340c04c8 }, >> + { .reg = ANACTRL_PCIEPLL_CTRL0, .def = 0x140c04c8, .delay_us = 20 }, >> + { .reg = ANACTRL_PCIEPLL_CTRL2, .def = 0x00001000 } >> +}; >> + >> +static struct clk_regmap t7_pcie_pll_dco = { >> + .data = &(struct meson_clk_pll_data){ >> + .en = { >> + .reg_off = ANACTRL_PCIEPLL_CTRL0, >> + .shift = 28, >> + .width = 1, >> + }, >> + .m = { >> + .reg_off = ANACTRL_PCIEPLL_CTRL0, >> + .shift = 0, >> + .width = 8, >> + }, >> + .n = { >> + .reg_off = ANACTRL_PCIEPLL_CTRL0, >> + .shift = 10, >> + .width = 5, >> + }, >> + .l = { >> + .reg_off = ANACTRL_PCIEPLL_CTRL0, >> + .shift = 31, >> + .width = 1, >> + }, >> + .rst = { >> + .reg_off = ANACTRL_PCIEPLL_CTRL0, >> + .shift = 29, >> + .width = 1, >> + }, >> + .init_regs = t7_pcie_pll_init_regs, >> + .init_count = ARRAY_SIZE(t7_pcie_pll_init_regs), >> + }, >> + .hw.init = &(struct clk_init_data){ >> + .name = "t7_pcie_pll_dco", >> + .ops = &meson_clk_pcie_pll_ops, >> + .parent_data = &(const struct clk_parent_data) { >> + .fw_name = "in0", >> + }, >> + .num_parents = 1, >> + }, >> +}; >> + >> +static struct clk_fixed_factor t7_pcie_pll_dco_div2 = { >> + .mult = 1, >> + .div = 2, >> + .hw.init = &(struct clk_init_data){ >> + .name = "t7_pcie_pll_dco_div2", >> + .ops = &clk_fixed_factor_ops, >> + .parent_hws = (const struct clk_hw *[]) { >> + &t7_pcie_pll_dco.hw >> + }, >> + .num_parents = 1, >> + .flags = CLK_SET_RATE_PARENT, >> + }, >> +}; >> + >> +static struct clk_regmap t7_pcie_pll_od = { >> + .data = &(struct clk_regmap_div_data){ >> + .offset = ANACTRL_PCIEPLL_CTRL0, >> + .shift = 16, >> + .width = 5, >> + .flags = CLK_DIVIDER_ONE_BASED | >> + CLK_DIVIDER_ALLOW_ZERO, > What's the behaviour of the divider on zero then ? If there is no CLK_DIVDER_ALLOW_ZERO, there is a warning when registering t7_pcie_pll_od. like this: ------------[ cut here ]------------ WARNING: CPU: 1 PID: 1 at drivers/clk/clk-divider.c:140 divider_recalc_rate+0xfc/0x100 pcie_pll_od: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set Modules linked in: CPU: 1 PID: 1 Comm: swapper/0 Not tainted 5.4.283-09976-ga803e94eed88-dirty #91 Hardware name: tm2_t962e2_ab311 (DT) Call trace: [ffffffc020003750+ 64][<ffffffc0100e3e3c>] dump_backtrace+0x0/0x1e4 [ffffffc020003790+ 32][<ffffffc0100e4044>] show_stack+0x24/0x34 [ffffffc0200037b0+ 96][<ffffffc01130a2e8>] dump_stack+0xbc/0x108 [ffffffc020003810+ 144][<ffffffc01010c484>] __warn+0xf4/0x1b8 [ffffffc0200038a0+ 64][<ffffffc01010c5f4>] warn_slowpath_fmt+0xac/0xc8 [ffffffc0200038e0+ 64][<ffffffc01061d364>] divider_recalc_rate+0xfc/0x100 [ffffffc020003920+ 80][<ffffffc010624e84>] clk_regmap_div_recalc_rate+0x74/0x88 [ffffffc020003970+ 96][<ffffffc010616a54>] __clk_register+0x62c/0xb78 so add it to avoid the warning. >> + }, >> + .hw.init = &(struct clk_init_data){ >> + .name = "t7_pcie_pll_od", >> + .ops = &clk_regmap_divider_ops, >> + .parent_hws = (const struct clk_hw *[]) { >> + &t7_pcie_pll_dco_div2.hw >> + }, >> + .num_parents = 1, >> + .flags = CLK_SET_RATE_PARENT, >> + }, >> +}; >> + >> +static struct clk_fixed_factor t7_pcie_pll = { >> + .mult = 1, >> + .div = 2, >> + .hw.init = &(struct clk_init_data){ >> + .name = "t7_pcie_pll", >> + .ops = &clk_fixed_factor_ops, >> + .parent_hws = (const struct clk_hw *[]) { >> + &t7_pcie_pll_od.hw >> + }, >> + .num_parents = 1, >> + .flags = CLK_SET_RATE_PARENT, >> + }, >> +}; >> + >> +static struct clk_fixed_factor t7_mpll_prediv = { >> + .mult = 1, >> + .div = 2, >> + .hw.init = &(struct clk_init_data){ >> + .name = "t7_mpll_prediv", >> + .ops = &clk_fixed_factor_ops, >> + .parent_data = &(const struct clk_parent_data) { >> + .fw_name = "in0", >> + }, >> + .num_parents = 1, >> + }, >> +}; >> + >> +static const struct reg_sequence t7_mpll0_init_regs[] = { >> + { .reg = ANACTRL_MPLL_CTRL2, .def = 0x40000033 } >> +}; >> + >> +static struct clk_regmap t7_mpll0_div = { >> + .data = &(struct meson_clk_mpll_data){ >> + .sdm = { >> + .reg_off = ANACTRL_MPLL_CTRL1, >> + .shift = 0, >> + .width = 14, >> + }, >> + .sdm_en = { >> + .reg_off = ANACTRL_MPLL_CTRL1, >> + .shift = 30, >> + .width = 1, >> + }, >> + .n2 = { >> + .reg_off = ANACTRL_MPLL_CTRL1, >> + .shift = 20, >> + .width = 9, >> + }, >> + .ssen = { >> + .reg_off = ANACTRL_MPLL_CTRL1, >> + .shift = 29, >> + .width = 1, >> + }, >> + .init_regs = t7_mpll0_init_regs, >> + .init_count = ARRAY_SIZE(t7_mpll0_init_regs), >> + }, >> + .hw.init = &(struct clk_init_data){ >> + .name = "t7_mpll0_div", >> + .ops = &meson_clk_mpll_ops, >> + .parent_hws = (const struct clk_hw *[]) { >> + &t7_mpll_prediv.hw >> + }, >> + .num_parents = 1, >> + }, >> +}; >> + >> +static struct clk_regmap t7_mpll0 = { >> + .data = &(struct clk_regmap_gate_data){ >> + .offset = ANACTRL_MPLL_CTRL1, >> + .bit_idx = 31, >> + }, >> + .hw.init = &(struct clk_init_data){ >> + .name = "t7_mpll0", >> + .ops = &clk_regmap_gate_ops, >> + .parent_hws = (const struct clk_hw *[]) { &t7_mpll0_div.hw }, >> + .num_parents = 1, >> + .flags = CLK_SET_RATE_PARENT, >> + }, >> +}; >> + >> +static const struct reg_sequence t7_mpll1_init_regs[] = { >> + { .reg = ANACTRL_MPLL_CTRL4, .def = 0x40000033 } >> +}; >> + >> +static struct clk_regmap t7_mpll1_div = { >> + .data = &(struct meson_clk_mpll_data){ >> + .sdm = { >> + .reg_off = ANACTRL_MPLL_CTRL3, >> + .shift = 0, >> + .width = 14, >> + }, >> + .sdm_en = { >> + .reg_off = ANACTRL_MPLL_CTRL3, >> + .shift = 30, >> + .width = 1, >> + }, >> + .n2 = { >> + .reg_off = ANACTRL_MPLL_CTRL3, >> + .shift = 20, >> + .width = 9, >> + }, >> + .ssen = { >> + .reg_off = ANACTRL_MPLL_CTRL3, >> + .shift = 29, >> + .width = 1, >> + }, >> + .init_regs = t7_mpll1_init_regs, >> + .init_count = ARRAY_SIZE(t7_mpll1_init_regs), >> + }, >> + .hw.init = &(struct clk_init_data){ >> + .name = "t7_mpll1_div", >> + .ops = &meson_clk_mpll_ops, >> + .parent_hws = (const struct clk_hw *[]) { >> + &t7_mpll_prediv.hw >> + }, >> + .num_parents = 1, >> + }, >> +}; >> + >> +static struct clk_regmap t7_mpll1 = { >> + .data = &(struct clk_regmap_gate_data){ >> + .offset = ANACTRL_MPLL_CTRL3, >> + .bit_idx = 31, >> + }, >> + .hw.init = &(struct clk_init_data){ >> + .name = "t7_mpll1", >> + .ops = &clk_regmap_gate_ops, >> + .parent_hws = (const struct clk_hw *[]) { &t7_mpll1_div.hw }, >> + .num_parents = 1, >> + .flags = CLK_SET_RATE_PARENT, >> + }, >> +}; >> + >> +static const struct reg_sequence t7_mpll2_init_regs[] = { >> + { .reg = ANACTRL_MPLL_CTRL6, .def = 0x40000033 } >> +}; >> + >> +static struct clk_regmap t7_mpll2_div = { >> + .data = &(struct meson_clk_mpll_data){ >> + .sdm = { >> + .reg_off = ANACTRL_MPLL_CTRL5, >> + .shift = 0, >> + .width = 14, >> + }, >> + .sdm_en = { >> + .reg_off = ANACTRL_MPLL_CTRL5, >> + .shift = 30, >> + .width = 1, >> + }, >> + .n2 = { >> + .reg_off = ANACTRL_MPLL_CTRL5, >> + .shift = 20, >> + .width = 9, >> + }, >> + .ssen = { >> + .reg_off = ANACTRL_MPLL_CTRL5, >> + .shift = 29, >> + .width = 1, >> + }, >> + .init_regs = t7_mpll2_init_regs, >> + .init_count = ARRAY_SIZE(t7_mpll2_init_regs), >> + }, >> + .hw.init = &(struct clk_init_data){ >> + .name = "t7_mpll2_div", >> + .ops = &meson_clk_mpll_ops, >> + .parent_hws = (const struct clk_hw *[]) { >> + &t7_mpll_prediv.hw >> + }, >> + .num_parents = 1, >> + }, >> +}; >> + >> +static struct clk_regmap t7_mpll2 = { >> + .data = &(struct clk_regmap_gate_data){ >> + .offset = ANACTRL_MPLL_CTRL5, >> + .bit_idx = 31, >> + }, >> + .hw.init = &(struct clk_init_data){ >> + .name = "t7_mpll2", >> + .ops = &clk_regmap_gate_ops, >> + .parent_hws = (const struct clk_hw *[]) { &t7_mpll2_div.hw }, >> + .num_parents = 1, >> + .flags = CLK_SET_RATE_PARENT, >> + }, >> +}; >> + >> +static const struct reg_sequence t7_mpll3_init_regs[] = { >> + { .reg = ANACTRL_MPLL_CTRL8, .def = 0x40000033 } >> +}; >> + >> +static struct clk_regmap t7_mpll3_div = { >> + .data = &(struct meson_clk_mpll_data){ >> + .sdm = { >> + .reg_off = ANACTRL_MPLL_CTRL7, >> + .shift = 0, >> + .width = 14, >> + }, >> + .sdm_en = { >> + .reg_off = ANACTRL_MPLL_CTRL7, >> + .shift = 30, >> + .width = 1, >> + }, >> + .n2 = { >> + .reg_off = ANACTRL_MPLL_CTRL7, >> + .shift = 20, >> + .width = 9, >> + }, >> + .ssen = { >> + .reg_off = ANACTRL_MPLL_CTRL7, >> + .shift = 29, >> + .width = 1, >> + }, >> + .init_regs = t7_mpll3_init_regs, >> + .init_count = ARRAY_SIZE(t7_mpll3_init_regs), >> + }, >> + .hw.init = &(struct clk_init_data){ >> + .name = "t7_mpll3_div", >> + .ops = &meson_clk_mpll_ops, >> + .parent_hws = (const struct clk_hw *[]) { >> + &t7_mpll_prediv.hw >> + }, >> + .num_parents = 1, >> + }, >> +}; >> + >> +static struct clk_regmap t7_mpll3 = { >> + .data = &(struct clk_regmap_gate_data){ >> + .offset = ANACTRL_MPLL_CTRL7, >> + .bit_idx = 31, >> + }, >> + .hw.init = &(struct clk_init_data){ >> + .name = "t7_mpll3", >> + .ops = &clk_regmap_gate_ops, >> + .parent_hws = (const struct clk_hw *[]) { &t7_mpll3_div.hw }, >> + .num_parents = 1, >> + .flags = CLK_SET_RATE_PARENT, >> + }, >> +}; >> + >> +static const struct reg_sequence t7_hdmi_init_regs[] = { >> + { .reg = ANACTRL_HDMIPLL_CTRL1, .def = 0x00000000 }, >> + { .reg = ANACTRL_HDMIPLL_CTRL2, .def = 0x00000000 }, >> + { .reg = ANACTRL_HDMIPLL_CTRL3, .def = 0x6a28dc00 }, >> + { .reg = ANACTRL_HDMIPLL_CTRL4, .def = 0x65771290 }, >> + { .reg = ANACTRL_HDMIPLL_CTRL5, .def = 0x39272000 }, >> + { .reg = ANACTRL_HDMIPLL_CTRL6, .def = 0x56540000 } >> +}; >> + >> +static struct clk_regmap t7_hdmi_pll_dco = { >> + .data = &(struct meson_clk_pll_data){ >> + .en = { >> + .reg_off = ANACTRL_HDMIPLL_CTRL0, >> + .shift = 28, >> + .width = 1, >> + }, >> + .m = { >> + .reg_off = ANACTRL_HDMIPLL_CTRL0, >> + .shift = 0, >> + .width = 9, >> + }, >> + .n = { >> + .reg_off = ANACTRL_HDMIPLL_CTRL0, >> + .shift = 10, >> + .width = 5, >> + }, >> + .l = { >> + .reg_off = ANACTRL_HDMIPLL_CTRL0, >> + .shift = 31, >> + .width = 1, >> + }, >> + .rst = { >> + .reg_off = ANACTRL_HDMIPLL_CTRL0, >> + .shift = 29, >> + .width = 1, >> + }, >> + .range = &t7_media_pll_mult_range, >> + .init_regs = t7_hdmi_init_regs, >> + .init_count = ARRAY_SIZE(t7_hdmi_init_regs), >> + }, >> + .hw.init = &(struct clk_init_data){ >> + .name = "t7_hdmi_pll_dco", >> + .ops = &meson_clk_pll_ops, >> + .parent_data = (const struct clk_parent_data []) { >> + { .fw_name = "in0", } >> + }, >> + .num_parents = 1, >> + }, >> +}; >> + >> +static struct clk_regmap t7_hdmi_pll_od = { >> + .data = &(struct clk_regmap_div_data){ >> + .offset = ANACTRL_HDMIPLL_CTRL0, >> + .shift = 16, >> + .width = 4, >> + .flags = CLK_DIVIDER_POWER_OF_TWO, >> + }, >> + .hw.init = &(struct clk_init_data){ >> + .name = "t7_hdmi_pll_od", >> + .ops = &clk_regmap_divider_ops, >> + .parent_hws = (const struct clk_hw *[]) { >> + &t7_hdmi_pll_dco.hw >> + }, >> + .num_parents = 1, >> + .flags = CLK_SET_RATE_PARENT, >> + }, >> +}; >> + >> +static struct clk_regmap t7_hdmi_pll = { >> + .data = &(struct clk_regmap_div_data){ >> + .offset = ANACTRL_HDMIPLL_CTRL0, >> + .shift = 20, >> + .width = 2, >> + .flags = CLK_DIVIDER_POWER_OF_TWO, >> + }, >> + .hw.init = &(struct clk_init_data){ >> + .name = "t7_hdmi_pll", >> + .ops = &clk_regmap_divider_ops, >> + .parent_hws = (const struct clk_hw *[]) { >> + &t7_hdmi_pll_od.hw >> + }, >> + .num_parents = 1, >> + .flags = CLK_SET_RATE_PARENT, >> + }, >> +}; >> + >> +static const struct pll_mult_range t7_mclk_pll_mult_range = { >> + .min = 67, >> + .max = 133, >> +}; >> + >> +static const struct reg_sequence t7_mclk_init_regs[] = { >> + { .reg = ANACTRL_MCLK_PLL_CNTL1, .def = 0x1470500f }, >> + { .reg = ANACTRL_MCLK_PLL_CNTL2, .def = 0x00023041 }, >> + { .reg = ANACTRL_MCLK_PLL_CNTL3, .def = 0x18180000 }, >> + { .reg = ANACTRL_MCLK_PLL_CNTL4, .def = 0x00180303 }, >> + { .reg = ANACTRL_MCLK_PLL_CNTL2, .def = 0x00023001, .delay_us = 20 } > What is this bit that you need to clear after the init sequence ? > Any chance this maps to something the driver already has ? Doing init > really belong on the init sequence - done at init only ? the bit 6 in CNTL2 is used to control pll lock detect module. it avoids lock bit false triggering. It is lock detect bit. the PLL lock sequence is: 1. enable bit, pll reset bit, lock detect bit is 0 as default 2. set pll reset bit = 1 3. set pll enable bit =1 4. set lock detect bit = 1 5. set pll reset bit = 0 6. set lock detect bit = 0 7.check the pll is locked by lock bit. I will remove the last one, and left the second init reg(0x00023001). And change the callback meson_clk_pll_enable in clk-pll.c. So it does A1. It works well for HIFI PLL on A1 board with Linux-6.14.0 . static int meson_clk_pll_enable(struct clk_hw *hw) { struct clk_regmap *clk = to_clk_regmap(hw); struct meson_clk_pll_data *pll = meson_clk_pll_data(clk); /* do nothing if the PLL is already enabled */ if (clk_hw_is_enabled(hw)) return 0; /* Make sure the pll is in reset */ if (MESON_PARM_APPLICABLE(&pll->rst)) meson_parm_write(clk->map, &pll->rst, 1); /* Enable the pll */ meson_parm_write(clk->map, &pll->en, 1); if (MESON_PARM_APPLICABLE(&pll->l_detect)) { meson_parm_write(clk->map, &pll->l_detect, 1); /* Take the pll out reset */ if (MESON_PARM_APPLICABLE(&pll->rst)) meson_parm_write(clk->map, &pll->rst, 0); /* * Compared with the previous SoCs, self-adaption current module * is newly added for A1, keep the new power-on sequence to enable the * PLL. The sequence is: * 1. enable the pll, delay for 10us * 2. enable the pll self-adaption current module, delay for 40us * 3. release the lock detect bit */ if (MESON_PARM_APPLICABLE(&pll->current_en)) { udelay(10); meson_parm_write(clk->map, &pll->current_en, 1); udelay(40); } if (MESON_PARM_APPLICABLE(&pll->l_detect)) { meson_parm_write(clk->map, &pll->l_detect, 0); if (meson_clk_pll_wait_lock(hw)) return -EIO; return 0; } >> +}; >> + >> +static struct clk_regmap t7_mclk_pll_dco = { >> + .data = &(struct meson_clk_pll_data){ >> + .en = { >> + .reg_off = ANACTRL_MCLK_PLL_CNTL0, >> + .shift = 28, >> + .width = 1, >> + }, >> + .m = { >> + .reg_off = ANACTRL_MCLK_PLL_CNTL0, >> + .shift = 0, >> + .width = 8, >> + }, >> + .n = { >> + .reg_off = ANACTRL_MCLK_PLL_CNTL0, >> + .shift = 16, >> + .width = 5, >> + }, >> + .l = { >> + .reg_off = ANACTRL_MCLK_PLL_CNTL0, >> + .shift = 31, >> + .width = 1, >> + }, >> + .rst = { >> + .reg_off = ANACTRL_MCLK_PLL_CNTL0, >> + .shift = 29, >> + .width = 1, >> + }, >> + .range = &t7_mclk_pll_mult_range, >> + .init_regs = t7_mclk_init_regs, >> + .init_count = ARRAY_SIZE(t7_mclk_init_regs), >> + }, >> + .hw.init = &(struct clk_init_data){ >> + .name = "t7_mclk_pll_dco", >> + .ops = &meson_clk_pll_ops, >> + .parent_data = &(const struct clk_parent_data) { >> + .fw_name = "in0", >> + }, >> + .num_parents = 1, >> + }, >> +}; >> + >> +/* max div is 16 */ >> +static const struct clk_div_table t7_mclk_div[] = { >> + { .val = 0, .div = 1 }, >> + { .val = 1, .div = 2 }, >> + { .val = 2, .div = 4 }, >> + { .val = 3, .div = 8 }, >> + { .val = 4, .div = 16 }, >> + { /* sentinel */ } >> +}; >> + >> +static struct clk_regmap t7_mclk_pre_od = { >> + .data = &(struct clk_regmap_div_data){ >> + .offset = ANACTRL_MCLK_PLL_CNTL0, >> + .shift = 12, >> + .width = 3, >> + .table = t7_mclk_div, >> + }, >> + .hw.init = &(struct clk_init_data){ >> + .name = "t7_mclk_pre_od", >> + .ops = &clk_regmap_divider_ops, >> + .parent_hws = (const struct clk_hw *[]) { >> + &t7_mclk_pll_dco.hw >> + }, >> + .num_parents = 1, >> + .flags = CLK_SET_RATE_PARENT, >> + }, >> +}; >> + >> +static struct clk_regmap t7_mclk_pll = { >> + .data = &(struct clk_regmap_div_data){ >> + .offset = ANACTRL_MCLK_PLL_CNTL4, >> + .shift = 16, >> + .width = 5, >> + .flags = CLK_DIVIDER_ONE_BASED, >> + }, >> + .hw.init = &(struct clk_init_data){ >> + .name = "t7_mclk_pll", >> + .ops = &clk_regmap_divider_ops, >> + .parent_hws = (const struct clk_hw *[]) { >> + &t7_mclk_pre_od.hw >> + }, >> + .num_parents = 1, >> + .flags = CLK_SET_RATE_PARENT, >> + }, >> +}; >> + >> +static struct clk_regmap t7_mclk_0_sel = { >> + .data = &(struct clk_regmap_mux_data){ >> + .offset = ANACTRL_MCLK_PLL_CNTL4, >> + .mask = 0x3, >> + .shift = 4, >> + }, >> + .hw.init = &(struct clk_init_data){ >> + .name = "t7_mclk_0_sel", >> + .ops = &clk_regmap_mux_ops, >> + .parent_data = (const struct clk_parent_data []) { >> + { .hw = &t7_mclk_pll.hw }, >> + { .fw_name = "in1", }, >> + { .fw_name = "in2", }, >> + }, >> + .num_parents = 3, >> + }, >> +}; >> + >> +static struct clk_fixed_factor t7_mclk_0_div2 = { >> + .mult = 1, >> + .div = 2, >> + .hw.init = &(struct clk_init_data){ >> + .name = "t7_mclk_0_div2", >> + .ops = &clk_fixed_factor_ops, >> + .parent_hws = (const struct clk_hw *[]) { &t7_mclk_0_sel.hw }, >> + .num_parents = 1, >> + .flags = CLK_SET_RATE_PARENT, >> + }, >> +}; >> + >> +static struct clk_regmap t7_mclk_0_pre = { >> + .data = &(struct clk_regmap_gate_data){ >> + .offset = ANACTRL_MCLK_PLL_CNTL4, >> + .bit_idx = 2, >> + }, >> + .hw.init = &(struct clk_init_data) { >> + .name = "t7_mclk_0_pre", >> + .ops = &clk_regmap_gate_ops, >> + .parent_hws = (const struct clk_hw *[]) { >> + &t7_mclk_0_div2.hw >> + }, >> + .num_parents = 1, >> + .flags = CLK_SET_RATE_PARENT, >> + }, >> +}; >> + >> +static struct clk_regmap t7_mclk_0 = { >> + .data = &(struct clk_regmap_gate_data){ >> + .offset = ANACTRL_MCLK_PLL_CNTL4, >> + .bit_idx = 0, >> + }, >> + .hw.init = &(struct clk_init_data) { >> + .name = "t7_mclk_0", >> + .ops = &clk_regmap_gate_ops, >> + .parent_hws = (const struct clk_hw *[]) { >> + &t7_mclk_0_pre.hw >> + }, >> + .num_parents = 1, >> + .flags = CLK_SET_RATE_PARENT, >> + }, >> +}; >> + >> +static struct clk_regmap t7_mclk_1_sel = { >> + .data = &(struct clk_regmap_mux_data){ >> + .offset = ANACTRL_MCLK_PLL_CNTL4, >> + .mask = 0x3, >> + .shift = 12, >> + }, >> + .hw.init = &(struct clk_init_data){ >> + .name = "t7_mclk_1_sel", >> + .ops = &clk_regmap_mux_ops, >> + .parent_data = (const struct clk_parent_data []) { >> + { .hw = &t7_mclk_pll.hw }, >> + { .fw_name = "in1", }, >> + { .fw_name = "in2", }, >> + }, >> + .num_parents = 3, >> + }, >> +}; >> + >> +static struct clk_fixed_factor t7_mclk_1_div2 = { >> + .mult = 1, >> + .div = 2, >> + .hw.init = &(struct clk_init_data){ >> + .name = "t7_mclk_1_div2", >> + .ops = &clk_fixed_factor_ops, >> + .parent_hws = (const struct clk_hw *[]) { &t7_mclk_1_sel.hw }, >> + .num_parents = 1, >> + .flags = CLK_SET_RATE_PARENT, >> + }, >> +}; >> + >> +static struct clk_regmap t7_mclk_1_pre = { >> + .data = &(struct clk_regmap_gate_data){ >> + .offset = ANACTRL_MCLK_PLL_CNTL4, >> + .bit_idx = 10, >> + }, >> + .hw.init = &(struct clk_init_data) { >> + .name = "t7_mclk_1_pre", >> + .ops = &clk_regmap_gate_ops, >> + .parent_hws = (const struct clk_hw *[]) { >> + &t7_mclk_1_div2.hw >> + }, >> + .num_parents = 1, >> + .flags = CLK_SET_RATE_PARENT, >> + }, >> +}; >> + >> +static struct clk_regmap t7_mclk_1 = { >> + .data = &(struct clk_regmap_gate_data){ >> + .offset = ANACTRL_MCLK_PLL_CNTL4, >> + .bit_idx = 8, >> + }, >> + .hw.init = &(struct clk_init_data) { >> + .name = "t7_mclk_1", >> + .ops = &clk_regmap_gate_ops, >> + .parent_hws = (const struct clk_hw *[]) { >> + &t7_mclk_1_pre.hw >> + }, >> + .num_parents = 1, >> + .flags = CLK_SET_RATE_PARENT, >> + }, >> +}; >> + >> +static struct clk_hw *t7_gp0_hw_clks[] = { >> + [CLKID_GP0_PLL_DCO] = &t7_gp0_pll_dco.hw, >> + [CLKID_GP0_PLL] = &t7_gp0_pll.hw, >> +}; >> + >> +static struct clk_hw *t7_gp1_hw_clks[] = { >> + [CLKID_GP1_PLL_DCO] = &t7_gp1_pll_dco.hw, >> + [CLKID_GP1_PLL] = &t7_gp1_pll.hw, >> +}; >> + >> +static struct clk_hw *t7_hifi_hw_clks[] = { >> + [CLKID_HIFI_PLL_DCO] = &t7_hifi_pll_dco.hw, >> + [CLKID_HIFI_PLL] = &t7_hifi_pll.hw, >> +}; >> + >> +static struct clk_hw *t7_pcie_hw_clks[] = { >> + [CLKID_PCIE_PLL_DCO] = &t7_pcie_pll_dco.hw, >> + [CLKID_PCIE_PLL_DCO_DIV2] = &t7_pcie_pll_dco_div2.hw, >> + [CLKID_PCIE_PLL_OD] = &t7_pcie_pll_od.hw, >> + [CLKID_PCIE_PLL] = &t7_pcie_pll.hw, >> +}; >> + >> +static struct clk_hw *t7_mpll_hw_clks[] = { >> + [CLKID_MPLL_PREDIV] = &t7_mpll_prediv.hw, >> + [CLKID_MPLL0_DIV] = &t7_mpll0_div.hw, >> + [CLKID_MPLL0] = &t7_mpll0.hw, >> + [CLKID_MPLL1_DIV] = &t7_mpll1_div.hw, >> + [CLKID_MPLL1] = &t7_mpll1.hw, >> + [CLKID_MPLL2_DIV] = &t7_mpll2_div.hw, >> + [CLKID_MPLL2] = &t7_mpll2.hw, >> + [CLKID_MPLL3_DIV] = &t7_mpll3_div.hw, >> + [CLKID_MPLL3] = &t7_mpll3.hw, >> +}; >> + >> +static struct clk_hw *t7_hdmi_hw_clks[] = { >> + [CLKID_HDMI_PLL_DCO] = &t7_hdmi_pll_dco.hw, >> + [CLKID_HDMI_PLL_OD] = &t7_hdmi_pll_od.hw, >> + [CLKID_HDMI_PLL] = &t7_hdmi_pll.hw, >> +}; >> + >> +static struct clk_hw *t7_mclk_hw_clks[] = { >> + [CLKID_MCLK_PLL_DCO] = &t7_mclk_pll_dco.hw, >> + [CLKID_MCLK_PRE] = &t7_mclk_pre_od.hw, >> + [CLKID_MCLK_PLL] = &t7_mclk_pll.hw, >> + [CLKID_MCLK_0_SEL] = &t7_mclk_0_sel.hw, >> + [CLKID_MCLK_0_DIV2] = &t7_mclk_0_div2.hw, >> + [CLKID_MCLK_0_PRE] = &t7_mclk_0_pre.hw, >> + [CLKID_MCLK_0] = &t7_mclk_0.hw, >> + [CLKID_MCLK_1_SEL] = &t7_mclk_1_sel.hw, >> + [CLKID_MCLK_1_DIV2] = &t7_mclk_1_div2.hw, >> + [CLKID_MCLK_1_PRE] = &t7_mclk_1_pre.hw, >> + [CLKID_MCLK_1] = &t7_mclk_1.hw, >> +}; >> + >> +static struct clk_regmap *const t7_gp0_regmaps[] = { >> + &t7_gp0_pll_dco, >> + &t7_gp0_pll, >> +}; >> + >> +static struct clk_regmap *const t7_gp1_regmaps[] = { >> + &t7_gp1_pll_dco, >> + &t7_gp1_pll, >> +}; >> + >> +static struct clk_regmap *const t7_hifi_regmaps[] = { >> + &t7_hifi_pll_dco, >> + &t7_hifi_pll, >> +}; >> + >> +static struct clk_regmap *const t7_pcie_regmaps[] = { >> + &t7_pcie_pll_dco, >> + &t7_pcie_pll_od, >> +}; >> + >> +static struct clk_regmap *const t7_mpll_regmaps[] = { >> + &t7_mpll0_div, >> + &t7_mpll0, >> + &t7_mpll1_div, >> + &t7_mpll1, >> + &t7_mpll2_div, >> + &t7_mpll2, >> + &t7_mpll3_div, >> + &t7_mpll3, >> +}; >> + >> +static struct clk_regmap *const t7_hdmi_regmaps[] = { >> + &t7_hdmi_pll_dco, >> + &t7_hdmi_pll_od, >> + &t7_hdmi_pll, >> +}; >> + >> +static struct clk_regmap *const t7_mclk_regmaps[] = { >> + &t7_mclk_pll_dco, >> + &t7_mclk_pre_od, >> + &t7_mclk_pll, >> + &t7_mclk_0_sel, >> + &t7_mclk_0_pre, >> + &t7_mclk_0, >> + &t7_mclk_1_sel, >> + &t7_mclk_1_pre, >> + &t7_mclk_1, >> +}; >> + >> +static const struct regmap_config t7_clkc_regmap_config = { >> + .reg_bits = 32, >> + .val_bits = 32, >> + .reg_stride = 4, >> +}; >> + >> +static int amlogic_t7_pll_probe(struct platform_device *pdev) >> +{ >> + struct device *dev = &pdev->dev; >> + const struct meson_eeclkc_data *data; >> + void __iomem *base; >> + struct regmap *map; >> + int i, ret; >> + >> + data = of_device_get_match_data(&pdev->dev); >> + if (!data) >> + return -EINVAL; >> + >> + base = devm_platform_ioremap_resource(pdev, 0); >> + if (IS_ERR(base)) >> + return PTR_ERR(base); >> + >> + map = devm_regmap_init_mmio(dev, base, &t7_clkc_regmap_config); >> + if (IS_ERR(map)) >> + return PTR_ERR(map); >> + >> + /* Populate regmap for the regmap backed clocks */ >> + for (i = 0; i < data->regmap_clk_num; i++) >> + data->regmap_clks[i]->map = map; >> + >> + if (data->init_count) >> + regmap_multi_reg_write(map, data->init_regs, >> + data->init_count); >> + >> + /* Register clocks */ >> + for (i = 0; i < data->hw_clks.num; i++) { >> + ret = devm_clk_hw_register(dev, data->hw_clks.hws[i]); >> + if (ret) >> + return ret; >> + } >> + >> + return devm_of_clk_add_hw_provider(dev, meson_clk_hw_get, (void *)&data->hw_clks); >> +} >> + >> +static const struct meson_eeclkc_data t7_gp0_data = { >> + .regmap_clks = t7_gp0_regmaps, >> + .regmap_clk_num = ARRAY_SIZE(t7_gp0_regmaps), >> + .hw_clks = { >> + .hws = t7_gp0_hw_clks, >> + .num = ARRAY_SIZE(t7_gp0_hw_clks), >> + }, >> +}; >> + >> +static const struct meson_eeclkc_data t7_gp1_data = { >> + .regmap_clks = t7_gp1_regmaps, >> + .regmap_clk_num = ARRAY_SIZE(t7_gp1_regmaps), >> + .hw_clks = { >> + .hws = t7_gp1_hw_clks, >> + .num = ARRAY_SIZE(t7_gp1_hw_clks), >> + }, >> +}; >> + >> +static const struct meson_eeclkc_data t7_hifi_data = { >> + .regmap_clks = t7_hifi_regmaps, >> + .regmap_clk_num = ARRAY_SIZE(t7_hifi_regmaps), >> + .hw_clks = { >> + .hws = t7_hifi_hw_clks, >> + .num = ARRAY_SIZE(t7_hifi_hw_clks), >> + }, >> +}; >> + >> +static const struct meson_eeclkc_data t7_pcie_data = { >> + .regmap_clks = t7_pcie_regmaps, >> + .regmap_clk_num = ARRAY_SIZE(t7_pcie_regmaps), >> + .hw_clks = { >> + .hws = t7_pcie_hw_clks, >> + .num = ARRAY_SIZE(t7_pcie_hw_clks), >> + }, >> +}; >> + >> +static const struct reg_sequence mpll_init_regs[] = { >> + { .reg = ANACTRL_MPLL_CTRL0, .def = 0x00000543 } >> +}; >> + >> +static const struct meson_eeclkc_data t7_mpll_data = { >> + .regmap_clks = t7_mpll_regmaps, >> + .regmap_clk_num = ARRAY_SIZE(t7_mpll_regmaps), >> + .init_regs = mpll_init_regs, >> + .init_count = ARRAY_SIZE(mpll_init_regs), >> + .hw_clks = { >> + .hws = t7_mpll_hw_clks, >> + .num = ARRAY_SIZE(t7_mpll_hw_clks), >> + }, >> +}; >> + >> +static const struct meson_eeclkc_data t7_hdmi_data = { >> + .regmap_clks = t7_hdmi_regmaps, >> + .regmap_clk_num = ARRAY_SIZE(t7_hdmi_regmaps), >> + .hw_clks = { >> + .hws = t7_hdmi_hw_clks, >> + .num = ARRAY_SIZE(t7_hdmi_hw_clks), >> + }, >> +}; >> + >> +static const struct meson_eeclkc_data t7_mclk_data = { >> + .regmap_clks = t7_mclk_regmaps, >> + .regmap_clk_num = ARRAY_SIZE(t7_mclk_regmaps), >> + .hw_clks = { >> + .hws = t7_mclk_hw_clks, >> + .num = ARRAY_SIZE(t7_mclk_hw_clks), >> + }, >> +}; >> + >> +static const struct of_device_id t7_pll_clkc_match_table[] = { >> + { >> + .compatible = "amlogic,t7-pll-gp0", >> + .data = &t7_gp0_data, >> + }, >> + { > }, { please ok, add compatible and data in one line is better. + { .compatible = "amlogic,t7-pll-gp0", .data = &t7_gp0_data, }, + { .compatible = "amlogic,t7-pll-gp1", .data = &t7_gp1_data, }, + { .compatible = "amlogic,t7-pll-hifi", .data = &t7_hifi_data, }, + { .compatible = "amlogic,t7-pll-pcie", .data = &t7_pcie_data, }, + { .compatible = "amlogic,t7-mpll", .data = &t7_mpll_data, }, + { .compatible = "amlogic,t7-pll-hdmi", .data = &t7_hdmi_data, }, + { .compatible = "amlogic,t7-pll-mclk", .data = &t7_mclk_data, }, >> + .compatible = "amlogic,t7-pll-gp1", >> + .data = &t7_gp1_data, >> + }, >> + { >> + .compatible = "amlogic,t7-pll-hifi", >> + .data = &t7_hifi_data, >> + }, >> + { >> + .compatible = "amlogic,t7-pll-pcie", >> + .data = &t7_pcie_data, >> + }, >> + { >> + .compatible = "amlogic,t7-mpll", >> + .data = &t7_mpll_data, >> + }, >> + { >> + .compatible = "amlogic,t7-pll-hdmi", >> + .data = &t7_hdmi_data, >> + }, >> + { >> + .compatible = "amlogic,t7-pll-mclk", >> + .data = &t7_mclk_data, >> + }, >> + {} >> +}; >> +MODULE_DEVICE_TABLE(of, t7_pll_clkc_match_table); >> + >> +static struct platform_driver t7_pll_clkc_driver = { >> + .probe = amlogic_t7_pll_probe, >> + .driver = { >> + .name = "t7-pll-clkc", >> + .of_match_table = t7_pll_clkc_match_table, >> + }, >> +}; >> + >> +MODULE_DESCRIPTION("Amlogic T7 PLL Clock Controller driver"); >> +module_platform_driver(t7_pll_clkc_driver); >> +MODULE_AUTHOR("Jian Hu<jian.hu@amlogic.com>"); >> +MODULE_LICENSE("GPL"); >> +MODULE_IMPORT_NS("CLK_MESON"); > -- > Jerome ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v3 4/6] clk: meson: t7: add support for the T7 SoC PLL clock 2025-06-12 13:02 ` Jian Hu @ 2025-06-16 16:27 ` Jerome Brunet 2025-06-25 2:52 ` Jian Hu 0 siblings, 1 reply; 19+ messages in thread From: Jerome Brunet @ 2025-06-16 16:27 UTC (permalink / raw) To: Jian Hu Cc: Xianwei Zhao, Chuan Liu, Neil Armstrong, Kevin Hilman, Stephen Boyd, Michael Turquette, Dmitry Rokosov, robh+dt, Rob Herring, devicetree, linux-clk, linux-amlogic, linux-kernel, linux-arm-kernel On Thu 12 Jun 2025 at 21:02, Jian Hu <jian.hu@amlogic.com> wrote: >>> + >>> +static struct clk_regmap t7_pcie_pll_od = { >>> + .data = &(struct clk_regmap_div_data){ >>> + .offset = ANACTRL_PCIEPLL_CTRL0, >>> + .shift = 16, >>> + .width = 5, >>> + .flags = CLK_DIVIDER_ONE_BASED | >>> + CLK_DIVIDER_ALLOW_ZERO, >> What's the behaviour of the divider on zero then ? > > > If there is no CLK_DIVDER_ALLOW_ZERO, there is a warning when registering > t7_pcie_pll_od. > > like this: > > ------------[ cut here ]------------ > WARNING: CPU: 1 PID: 1 at drivers/clk/clk-divider.c:140 > divider_recalc_rate+0xfc/0x100 > pcie_pll_od: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set > Modules linked in: > CPU: 1 PID: 1 Comm: swapper/0 Not tainted > 5.4.283-09976-ga803e94eed88-dirty #91 > Hardware name: tm2_t962e2_ab311 (DT) > Call trace: > [ffffffc020003750+ 64][<ffffffc0100e3e3c>] dump_backtrace+0x0/0x1e4 > [ffffffc020003790+ 32][<ffffffc0100e4044>] show_stack+0x24/0x34 > [ffffffc0200037b0+ 96][<ffffffc01130a2e8>] dump_stack+0xbc/0x108 > [ffffffc020003810+ 144][<ffffffc01010c484>] __warn+0xf4/0x1b8 > [ffffffc0200038a0+ 64][<ffffffc01010c5f4>] warn_slowpath_fmt+0xac/0xc8 > [ffffffc0200038e0+ 64][<ffffffc01061d364>] divider_recalc_rate+0xfc/0x100 > [ffffffc020003920+ 80][<ffffffc010624e84>] > clk_regmap_div_recalc_rate+0x74/0x88 > [ffffffc020003970+ 96][<ffffffc010616a54>] __clk_register+0x62c/0xb78 > > so add it to avoid the warning. That does not really answer my question ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v3 4/6] clk: meson: t7: add support for the T7 SoC PLL clock 2025-06-16 16:27 ` Jerome Brunet @ 2025-06-25 2:52 ` Jian Hu 2025-06-25 7:46 ` Jerome Brunet 0 siblings, 1 reply; 19+ messages in thread From: Jian Hu @ 2025-06-25 2:52 UTC (permalink / raw) To: Jerome Brunet Cc: Xianwei Zhao, Chuan Liu, Neil Armstrong, Kevin Hilman, Stephen Boyd, Michael Turquette, Dmitry Rokosov, robh+dt, Rob Herring, devicetree, linux-clk, linux-amlogic, linux-kernel, linux-arm-kernel On 2025/6/17 0:27, Jerome Brunet wrote: > [ EXTERNAL EMAIL ] > > On Thu 12 Jun 2025 at 21:02, Jian Hu <jian.hu@amlogic.com> wrote: > >>>> + >>>> +static struct clk_regmap t7_pcie_pll_od = { >>>> + .data = &(struct clk_regmap_div_data){ >>>> + .offset = ANACTRL_PCIEPLL_CTRL0, >>>> + .shift = 16, >>>> + .width = 5, >>>> + .flags = CLK_DIVIDER_ONE_BASED | >>>> + CLK_DIVIDER_ALLOW_ZERO, >>> What's the behaviour of the divider on zero then ? >> >> If there is no CLK_DIVDER_ALLOW_ZERO, there is a warning when registering >> t7_pcie_pll_od. >> >> like this: >> >> ------------[ cut here ]------------ >> WARNING: CPU: 1 PID: 1 at drivers/clk/clk-divider.c:140 >> divider_recalc_rate+0xfc/0x100 >> pcie_pll_od: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set >> Modules linked in: >> CPU: 1 PID: 1 Comm: swapper/0 Not tainted >> 5.4.283-09976-ga803e94eed88-dirty #91 >> Hardware name: tm2_t962e2_ab311 (DT) >> Call trace: >> [ffffffc020003750+ 64][<ffffffc0100e3e3c>] dump_backtrace+0x0/0x1e4 >> [ffffffc020003790+ 32][<ffffffc0100e4044>] show_stack+0x24/0x34 >> [ffffffc0200037b0+ 96][<ffffffc01130a2e8>] dump_stack+0xbc/0x108 >> [ffffffc020003810+ 144][<ffffffc01010c484>] __warn+0xf4/0x1b8 >> [ffffffc0200038a0+ 64][<ffffffc01010c5f4>] warn_slowpath_fmt+0xac/0xc8 >> [ffffffc0200038e0+ 64][<ffffffc01061d364>] divider_recalc_rate+0xfc/0x100 >> [ffffffc020003920+ 80][<ffffffc010624e84>] >> clk_regmap_div_recalc_rate+0x74/0x88 >> [ffffffc020003970+ 96][<ffffffc010616a54>] __clk_register+0x62c/0xb78 >> >> so add it to avoid the warning. > That does not really answer my question Sorry, I did not get you before. I have set OD to 0. And measure pcie frequency, It is 37.5Mhz. 4800Mhz/2/32/2=37.5Mhz, and the OD equal zero means divided by 32 in fact. Here is the test result: devm 0xfe008140 32 0xD40C04C8 cat /sys/kernel/debug/meson-clk-msr/measure_summary | grep pcie [16] pcie_clk_inp 37500000 +/1 3125HZ the OD divider is N crossover. it is one based. and It's possible to go from 1 to 31 crossovers. ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v3 4/6] clk: meson: t7: add support for the T7 SoC PLL clock 2025-06-25 2:52 ` Jian Hu @ 2025-06-25 7:46 ` Jerome Brunet 2025-07-03 3:42 ` Jian Hu 0 siblings, 1 reply; 19+ messages in thread From: Jerome Brunet @ 2025-06-25 7:46 UTC (permalink / raw) To: Jian Hu Cc: Xianwei Zhao, Chuan Liu, Neil Armstrong, Kevin Hilman, Stephen Boyd, Michael Turquette, Dmitry Rokosov, robh+dt, Rob Herring, devicetree, linux-clk, linux-amlogic, linux-kernel, linux-arm-kernel On Wed 25 Jun 2025 at 10:52, Jian Hu <jian.hu@amlogic.com> wrote: > On 2025/6/17 0:27, Jerome Brunet wrote: >> [ EXTERNAL EMAIL ] >> >> On Thu 12 Jun 2025 at 21:02, Jian Hu <jian.hu@amlogic.com> wrote: >> >>>>> + >>>>> +static struct clk_regmap t7_pcie_pll_od = { >>>>> + .data = &(struct clk_regmap_div_data){ >>>>> + .offset = ANACTRL_PCIEPLL_CTRL0, >>>>> + .shift = 16, >>>>> + .width = 5, >>>>> + .flags = CLK_DIVIDER_ONE_BASED | >>>>> + CLK_DIVIDER_ALLOW_ZERO, >>>> What's the behaviour of the divider on zero then ? >>> >>> If there is no CLK_DIVDER_ALLOW_ZERO, there is a warning when registering >>> t7_pcie_pll_od. >>> >>> like this: >>> >>> ------------[ cut here ]------------ >>> WARNING: CPU: 1 PID: 1 at drivers/clk/clk-divider.c:140 >>> divider_recalc_rate+0xfc/0x100 >>> pcie_pll_od: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set >>> Modules linked in: >>> CPU: 1 PID: 1 Comm: swapper/0 Not tainted >>> 5.4.283-09976-ga803e94eed88-dirty #91 >>> Hardware name: tm2_t962e2_ab311 (DT) >>> Call trace: >>> [ffffffc020003750+ 64][<ffffffc0100e3e3c>] dump_backtrace+0x0/0x1e4 >>> [ffffffc020003790+ 32][<ffffffc0100e4044>] show_stack+0x24/0x34 >>> [ffffffc0200037b0+ 96][<ffffffc01130a2e8>] dump_stack+0xbc/0x108 >>> [ffffffc020003810+ 144][<ffffffc01010c484>] __warn+0xf4/0x1b8 >>> [ffffffc0200038a0+ 64][<ffffffc01010c5f4>] warn_slowpath_fmt+0xac/0xc8 >>> [ffffffc0200038e0+ 64][<ffffffc01061d364>] divider_recalc_rate+0xfc/0x100 >>> [ffffffc020003920+ 80][<ffffffc010624e84>] >>> clk_regmap_div_recalc_rate+0x74/0x88 >>> [ffffffc020003970+ 96][<ffffffc010616a54>] __clk_register+0x62c/0xb78 >>> >>> so add it to avoid the warning. >> That does not really answer my question > > > Sorry, I did not get you before. > > I have set OD to 0. And measure pcie frequency, It is 37.5Mhz. > > 4800Mhz/2/32/2=37.5Mhz, and the OD equal zero means divided by 32 in fact. > CLK_DIVIDER_MAX_AT_ZERO maybe ? > Here is the test result: > > devm 0xfe008140 32 > > 0xD40C04C8 > > cat /sys/kernel/debug/meson-clk-msr/measure_summary | grep pcie > > [16] pcie_clk_inp 37500000 +/1 3125HZ > > > the OD divider is N crossover. it is one based. > > and It's possible to go from 1 to 31 crossovers. -- Jerome ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v3 4/6] clk: meson: t7: add support for the T7 SoC PLL clock 2025-06-25 7:46 ` Jerome Brunet @ 2025-07-03 3:42 ` Jian Hu 0 siblings, 0 replies; 19+ messages in thread From: Jian Hu @ 2025-07-03 3:42 UTC (permalink / raw) To: Jerome Brunet Cc: Xianwei Zhao, Chuan Liu, Neil Armstrong, Kevin Hilman, Stephen Boyd, Michael Turquette, Dmitry Rokosov, robh+dt, Rob Herring, devicetree, linux-clk, linux-amlogic, linux-kernel, linux-arm-kernel On 2025/6/25 15:46, Jerome Brunet wrote: > [ EXTERNAL EMAIL ] > > On Wed 25 Jun 2025 at 10:52, Jian Hu <jian.hu@amlogic.com> wrote: > >> On 2025/6/17 0:27, Jerome Brunet wrote: >>> [ EXTERNAL EMAIL ] >>> >>> On Thu 12 Jun 2025 at 21:02, Jian Hu <jian.hu@amlogic.com> wrote: >>> >>>>>> + >>>>>> +static struct clk_regmap t7_pcie_pll_od = { >>>>>> + .data = &(struct clk_regmap_div_data){ >>>>>> + .offset = ANACTRL_PCIEPLL_CTRL0, >>>>>> + .shift = 16, >>>>>> + .width = 5, >>>>>> + .flags = CLK_DIVIDER_ONE_BASED | >>>>>> + CLK_DIVIDER_ALLOW_ZERO, >>>>> What's the behaviour of the divider on zero then ? >>>> If there is no CLK_DIVDER_ALLOW_ZERO, there is a warning when registering >>>> t7_pcie_pll_od. >>>> >>>> like this: >>>> >>>> ------------[ cut here ]------------ >>>> WARNING: CPU: 1 PID: 1 at drivers/clk/clk-divider.c:140 >>>> divider_recalc_rate+0xfc/0x100 >>>> pcie_pll_od: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set >>>> Modules linked in: >>>> CPU: 1 PID: 1 Comm: swapper/0 Not tainted >>>> 5.4.283-09976-ga803e94eed88-dirty #91 >>>> Hardware name: tm2_t962e2_ab311 (DT) >>>> Call trace: >>>> [ffffffc020003750+ 64][<ffffffc0100e3e3c>] dump_backtrace+0x0/0x1e4 >>>> [ffffffc020003790+ 32][<ffffffc0100e4044>] show_stack+0x24/0x34 >>>> [ffffffc0200037b0+ 96][<ffffffc01130a2e8>] dump_stack+0xbc/0x108 >>>> [ffffffc020003810+ 144][<ffffffc01010c484>] __warn+0xf4/0x1b8 >>>> [ffffffc0200038a0+ 64][<ffffffc01010c5f4>] warn_slowpath_fmt+0xac/0xc8 >>>> [ffffffc0200038e0+ 64][<ffffffc01061d364>] divider_recalc_rate+0xfc/0x100 >>>> [ffffffc020003920+ 80][<ffffffc010624e84>] >>>> clk_regmap_div_recalc_rate+0x74/0x88 >>>> [ffffffc020003970+ 96][<ffffffc010616a54>] __clk_register+0x62c/0xb78 >>>> >>>> so add it to avoid the warning. >>> That does not really answer my question >> >> Sorry, I did not get you before. >> >> I have set OD to 0. And measure pcie frequency, It is 37.5Mhz. >> >> 4800Mhz/2/32/2=37.5Mhz, and the OD equal zero means divided by 32 in fact. >> > CLK_DIVIDER_MAX_AT_ZERO maybe ? You are right, CLK_DIVIDER_MAX_AT_ZERO makes sense here. its width is 5, and the divisor is 2^5 = 32. I will add CLK_DIVIDER_MAX_AT_ZERO and remove CLK_DIVIDER_ALLOW_ZERO in the next version. >> Here is the test result: >> >> devm 0xfe008140 32 >> >> 0xD40C04C8 >> >> cat /sys/kernel/debug/meson-clk-msr/measure_summary | grep pcie >> >> [16] pcie_clk_inp 37500000 +/1 3125HZ >> >> >> the OD divider is N crossover. it is one based. >> >> and It's possible to go from 1 to 31 crossovers. > -- > Jerome ^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v3 5/6] clk: meson: add MESON_PCLK_V2 for sys gate clock 2025-05-09 7:48 [PATCH v3 0/6] add support for T7 family clock controller Jian Hu ` (3 preceding siblings ...) 2025-05-09 7:48 ` [PATCH v3 4/6] clk: meson: t7: add support for the T7 SoC PLL clock Jian Hu @ 2025-05-09 7:48 ` Jian Hu 2025-05-14 7:39 ` Jerome Brunet 2025-05-09 7:48 ` [PATCH v3 6/6] clk: meson: t7: add t7 clock peripherals controller driver Jian Hu 5 siblings, 1 reply; 19+ messages in thread From: Jian Hu @ 2025-05-09 7:48 UTC (permalink / raw) To: Jerome Brunet, Xianwei Zhao, Chuan Liu, Neil Armstrong, Kevin Hilman, Stephen Boyd, Michael Turquette, Dmitry Rokosov, robh+dt, Rob Herring Cc: Jian Hu, devicetree, linux-clk, linux-amlogic, linux-kernel, linux-arm-kernel A new MESON_PCLK_V2 macro is introduced for the sys gate clock. Its parent is an SCMI clock. It belongs to another clock controller, and the parent configuration is different from that of MESON_PCLK. This avoids new macro definition in the peripheral clock driver. Signed-off-by: Jian Hu <jian.hu@amlogic.com> --- drivers/clk/meson/clk-regmap.h | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/drivers/clk/meson/clk-regmap.h b/drivers/clk/meson/clk-regmap.h index e365312da54e..61b8fc2d875f 100644 --- a/drivers/clk/meson/clk-regmap.h +++ b/drivers/clk/meson/clk-regmap.h @@ -134,4 +134,28 @@ struct clk_regmap _name = { \ #define MESON_PCLK_RO(_name, _reg, _bit, _pname) \ __MESON_PCLK(_name, _reg, _bit, &clk_regmap_gate_ro_ops, _pname) + +#define __MESON_PCLK_V2(_name, _reg, _bit, _ops, _pname) \ +struct clk_regmap _name = { \ + .data = &(struct clk_regmap_gate_data){ \ + .offset = (_reg), \ + .bit_idx = (_bit), \ + }, \ + .hw.init = &(struct clk_init_data) { \ + .name = #_name, \ + .ops = _ops, \ + .parent_data = &(const struct clk_parent_data) { \ + .fw_name = #_pname, \ + }, \ + .num_parents = 1, \ + .flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED), \ + }, \ +} + +#define MESON_PCLK_V2(_name, _reg, _bit, _pname) \ + __MESON_PCLK_V2(_name, _reg, _bit, &clk_regmap_gate_ops, _pname) + +#define MESON_PCLK_RO_V2(_name, _reg, _bit, _pname) \ + __MESON_PCLK_V2(_name, _reg, _bit, &clk_regmap_gate_ro_ops, _pname) + #endif /* __CLK_REGMAP_H */ -- 2.47.1 ^ permalink raw reply related [flat|nested] 19+ messages in thread
* Re: [PATCH v3 5/6] clk: meson: add MESON_PCLK_V2 for sys gate clock 2025-05-09 7:48 ` [PATCH v3 5/6] clk: meson: add MESON_PCLK_V2 for sys gate clock Jian Hu @ 2025-05-14 7:39 ` Jerome Brunet [not found] ` <ea83e375-7088-4047-92f1-31d0e7c2c331@amlogic.com> 2025-06-20 9:21 ` Jian Hu 0 siblings, 2 replies; 19+ messages in thread From: Jerome Brunet @ 2025-05-14 7:39 UTC (permalink / raw) To: Jian Hu Cc: Xianwei Zhao, Chuan Liu, Neil Armstrong, Kevin Hilman, Stephen Boyd, Michael Turquette, Dmitry Rokosov, robh+dt, Rob Herring, devicetree, linux-clk, linux-amlogic, linux-kernel, linux-arm-kernel On Fri 09 May 2025 at 07:48, Jian Hu <jian.hu@amlogic.com> wrote: > A new MESON_PCLK_V2 macro is introduced for the sys gate clock. Its parent > is an SCMI clock. It belongs to another clock controller, and the parent > configuration is different from that of MESON_PCLK. This avoids new macro > definition in the peripheral clock driver. > > Signed-off-by: Jian Hu <jian.hu@amlogic.com> > --- > drivers/clk/meson/clk-regmap.h | 24 ++++++++++++++++++++++++ > 1 file changed, 24 insertions(+) > > diff --git a/drivers/clk/meson/clk-regmap.h b/drivers/clk/meson/clk-regmap.h > index e365312da54e..61b8fc2d875f 100644 > --- a/drivers/clk/meson/clk-regmap.h > +++ b/drivers/clk/meson/clk-regmap.h This file is not meant for amlogic specific stuff. I know some found their way in regardless but that's being fixed > @@ -134,4 +134,28 @@ struct clk_regmap _name = { \ > > #define MESON_PCLK_RO(_name, _reg, _bit, _pname) \ > __MESON_PCLK(_name, _reg, _bit, &clk_regmap_gate_ro_ops, _pname) > + > +#define __MESON_PCLK_V2(_name, _reg, _bit, _ops, _pname) \ > +struct clk_regmap _name = { \ > + .data = &(struct clk_regmap_gate_data){ \ > + .offset = (_reg), \ > + .bit_idx = (_bit), \ > + }, \ > + .hw.init = &(struct clk_init_data) { \ > + .name = #_name, \ > + .ops = _ops, \ > + .parent_data = &(const struct clk_parent_data) { \ > + .fw_name = #_pname, \ > + }, \ > + .num_parents = 1, \ > + .flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED), \ > + }, \ > +} The proliferation of those macros has been going on for far too long, add using CLK_IGNORE_UNUSED inside is certainly a mistake I won't repeat. This will be part of more general clean-up that currently depends on a this [1] patch to go further. You'll have to be patient. [1]: https://lore.kernel.org/r/20250417-clk-hw-get-helpers-v1-0-7743e509612a@baylibre.com > + > +#define MESON_PCLK_V2(_name, _reg, _bit, _pname) \ > + __MESON_PCLK_V2(_name, _reg, _bit, &clk_regmap_gate_ops, _pname) > + > +#define MESON_PCLK_RO_V2(_name, _reg, _bit, _pname) \ > + __MESON_PCLK_V2(_name, _reg, _bit, &clk_regmap_gate_ro_ops, _pname) > + > #endif /* __CLK_REGMAP_H */ -- Jerome ^ permalink raw reply [flat|nested] 19+ messages in thread
[parent not found: <ea83e375-7088-4047-92f1-31d0e7c2c331@amlogic.com>]
* Re: [PATCH v3 5/6] clk: meson: add MESON_PCLK_V2 for sys gate clock [not found] ` <ea83e375-7088-4047-92f1-31d0e7c2c331@amlogic.com> @ 2025-06-16 16:28 ` Jerome Brunet 0 siblings, 0 replies; 19+ messages in thread From: Jerome Brunet @ 2025-06-16 16:28 UTC (permalink / raw) To: Jian Hu Cc: Xianwei Zhao, Chuan Liu, Neil Armstrong, Kevin Hilman, Stephen Boyd, Michael Turquette, Dmitry Rokosov, robh+dt, Rob Herring, devicetree, linux-clk, linux-amlogic, linux-kernel, linux-arm-kernel On Fri 13 Jun 2025 at 13:35, Jian Hu <jian.hu@amlogic.com> wrote: > On 2025/5/14 15:39, Jerome Brunet wrote: > > [ EXTERNAL EMAIL ] Please fix your mailer, can't read that reply > > On Fri 09 May 2025 at 07:48, Jian Hu <jian.hu@amlogic.com> wrote: > > A new MESON_PCLK_V2 macro is introduced for the sys gate clock. Its parent > is an SCMI clock. It belongs to another clock controller, and the parent > configuration is different from that of MESON_PCLK. This avoids new macro > definition in the peripheral clock driver. > > Signed-off-by: Jian Hu <jian.hu@amlogic.com> > --- > drivers/clk/meson/clk-regmap.h | 24 ++++++++++++++++++++++++ > 1 file changed, 24 insertions(+) > > diff --git a/drivers/clk/meson/clk-regmap.h b/drivers/clk/meson/clk-regmap.h > index e365312da54e..61b8fc2d875f 100644 > --- a/drivers/clk/meson/clk-regmap.h > +++ b/drivers/clk/meson/clk-regmap.h > > > This file is not meant for amlogic specific stuff. I know some found > their way in regardless but that's being fixed > > I found macro MESON_PCLK is used in G12A/MESON8B/GXBB/S4. > > you mean the macro will be fixed? and use something else instead. > > > @@ -134,4 +134,28 @@ struct clk_regmap _name = { \ > > #define MESON_PCLK_RO(_name, _reg, _bit, _pname) \ > __MESON_PCLK(_name, _reg, _bit, &clk_regmap_gate_ro_ops, _pname) > + > +#define __MESON_PCLK_V2(_name, _reg, _bit, _ops, _pname) \ > +struct clk_regmap _name = { \ > + .data = &(struct clk_regmap_gate_data){ \ > + .offset = (_reg), \ > + .bit_idx = (_bit), \ > + }, \ > + .hw.init = &(struct clk_init_data) { \ > + .name = #_name, \ > + .ops = _ops, \ > + .parent_data = &(const struct clk_parent_data) { \ > + .fw_name = #_pname, \ > + }, \ > + .num_parents = 1, \ > + .flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED), \ > + }, \ > +} > > > The proliferation of those macros has been going on for far too long, > add using CLK_IGNORE_UNUSED inside is certainly a mistake I won't > repeat. > > This will be part of more general clean-up that currently depends on a > this [1] patch to go further. You'll have to be patient. > > [1]: https://lore.kernel.org/r/20250417-clk-hw-get-helpers-v1-0-7743e509612a@baylibre.com > > OK, CLK_IGNORE_UNUSED is added for all gate clocks. it is better to remove it. and wait for your patch merged. > > And quote your comments in v2. the T7_CLK_GATE is newly added in T7 Peripheral driver in v2. > > If I understand you correctly. A common macro should be added for it and remove T7_CLK_GATE. > > So I add a common macro in clk-regmap.h, and it can be used for different SoCs. > > MESON_PCLK and MESON_PCLK_V2 difference is a clocks's parent defination. > > the sys gate clock parent is in another clock controller. So parent_data member is need for it. > > and parent_hw member is for previous SoCs which clock and parent clock are in one clock controller. > > How should we deal with it. > > 1.Add the macro in T7 Perpheral driver. > > 2.Or add a common macro for parent_data, and where the macro should be placed? > > --- > >> +#define T7_CLK_GATE(_name, _reg, _bit, _fw_name, _flags) \ > > See, redefining the peripheral once again ... something all the SoCs > uses with minor variation. > >> +struct clk_regmap _name = { \ >> + .data = &(struct clk_regmap_gate_data){ \ >> + .offset = (_reg), \ >> + .bit_idx = (_bit), \ >> + }, \ >> + .hw.init = &(struct clk_init_data) { \ >> + .name = #_name, \ > > There is an exception in the naming convention for peripheral clocks. > > The name is soc id prefixed in most SoC. It is these pointless minor > diff that makes factorisation difficult. > >> + .ops = &clk_regmap_gate_ops, \ >> + .parent_data = &(const struct clk_parent_data) { \ >> + .fw_name = #_fw_name, \ >> + }, \ >> + .num_parents = 1, \ >> + .flags = (_flags), \ >> + }, \ > > --- > > > + > +#define MESON_PCLK_V2(_name, _reg, _bit, _pname) \ > + __MESON_PCLK_V2(_name, _reg, _bit, &clk_regmap_gate_ops, _pname) > + > +#define MESON_PCLK_RO_V2(_name, _reg, _bit, _pname) \ > + __MESON_PCLK_V2(_name, _reg, _bit, &clk_regmap_gate_ro_ops, _pname) > + > #endif /* __CLK_REGMAP_H */ -- Jerome ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v3 5/6] clk: meson: add MESON_PCLK_V2 for sys gate clock 2025-05-14 7:39 ` Jerome Brunet [not found] ` <ea83e375-7088-4047-92f1-31d0e7c2c331@amlogic.com> @ 2025-06-20 9:21 ` Jian Hu 1 sibling, 0 replies; 19+ messages in thread From: Jian Hu @ 2025-06-20 9:21 UTC (permalink / raw) To: Jerome Brunet Cc: Xianwei Zhao, Chuan Liu, Neil Armstrong, Kevin Hilman, Stephen Boyd, Michael Turquette, Dmitry Rokosov, robh+dt, Rob Herring, devicetree, linux-clk, linux-amlogic, linux-kernel, linux-arm-kernel Resend it because it refused to receive html messages. On 2025/5/14 15:39, Jerome Brunet wrote: > [ EXTERNAL EMAIL ] > > On Fri 09 May 2025 at 07:48, Jian Hu <jian.hu@amlogic.com> wrote: > >> A new MESON_PCLK_V2 macro is introduced for the sys gate clock. Its parent >> is an SCMI clock. It belongs to another clock controller, and the parent >> configuration is different from that of MESON_PCLK. This avoids new macro >> definition in the peripheral clock driver. >> >> Signed-off-by: Jian Hu <jian.hu@amlogic.com> >> --- >> drivers/clk/meson/clk-regmap.h | 24 ++++++++++++++++++++++++ >> 1 file changed, 24 insertions(+) >> >> diff --git a/drivers/clk/meson/clk-regmap.h b/drivers/clk/meson/clk-regmap.h >> index e365312da54e..61b8fc2d875f 100644 >> --- a/drivers/clk/meson/clk-regmap.h >> +++ b/drivers/clk/meson/clk-regmap.h > This file is not meant for amlogic specific stuff. I know some found > their way in regardless but that's being fixed OK, I found macro MESON_PCLK is used in G12A/MESON8B/GXBB/S4. New macro is needed for T7 . >> @@ -134,4 +134,28 @@ struct clk_regmap _name = { \ >> >> #define MESON_PCLK_RO(_name, _reg, _bit, _pname) \ >> __MESON_PCLK(_name, _reg, _bit, &clk_regmap_gate_ro_ops, _pname) >> + >> +#define __MESON_PCLK_V2(_name, _reg, _bit, _ops, _pname) \ >> +struct clk_regmap _name = { \ >> + .data = &(struct clk_regmap_gate_data){ \ >> + .offset = (_reg), \ >> + .bit_idx = (_bit), \ >> + }, \ >> + .hw.init = &(struct clk_init_data) { \ >> + .name = #_name, \ >> + .ops = _ops, \ >> + .parent_data = &(const struct clk_parent_data) { \ >> + .fw_name = #_pname, \ >> + }, \ >> + .num_parents = 1, \ >> + .flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED), \ >> + }, \ >> +} > The proliferation of those macros has been going on for far too long, > add using CLK_IGNORE_UNUSED inside is certainly a mistake I won't > repeat. > > This will be part of more general clean-up that currently depends on a > this [1] patch to go further. You'll have to be patient. > > [1]: https://lore.kernel.org/r/20250417-clk-hw-get-helpers-v1-0-7743e509612a@baylibre.com OK, CLK_IGNORE_UNUSED is added for all gate clocks. And quote your comments in v2. the T7_CLK_GATE is newly added in T7 Peripheral driver in v2. If I understand you correctly. A common macro should be added for it and remove T7_CLK_GATE. So I add a common macro in clk-regmap.h, and it can be used for different SoCs. MESON_PCLK and MESON_PCLK_V2 difference is a clocks's parent defination. the sys gate clock parent is in another clock controller. So parent_data member is needed for it. and parent_hw member is for previous SoCs which clock and parent clock are in one clock controller. How should we deal with it. 1.Add the macro in T7 Perpheral driver. 2.Or add a common macro for parent_data, and where the macro should be placed? maybe put it in meson-clkc-utils.h? >> + >> +#define MESON_PCLK_V2(_name, _reg, _bit, _pname) \ >> + __MESON_PCLK_V2(_name, _reg, _bit, &clk_regmap_gate_ops, _pname) >> + >> +#define MESON_PCLK_RO_V2(_name, _reg, _bit, _pname) \ >> + __MESON_PCLK_V2(_name, _reg, _bit, &clk_regmap_gate_ro_ops, _pname) >> + >> #endif /* __CLK_REGMAP_H */ > -- > Jerome ^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v3 6/6] clk: meson: t7: add t7 clock peripherals controller driver 2025-05-09 7:48 [PATCH v3 0/6] add support for T7 family clock controller Jian Hu ` (4 preceding siblings ...) 2025-05-09 7:48 ` [PATCH v3 5/6] clk: meson: add MESON_PCLK_V2 for sys gate clock Jian Hu @ 2025-05-09 7:48 ` Jian Hu 2025-05-14 8:00 ` Jerome Brunet 5 siblings, 1 reply; 19+ messages in thread From: Jian Hu @ 2025-05-09 7:48 UTC (permalink / raw) To: Jerome Brunet, Xianwei Zhao, Chuan Liu, Neil Armstrong, Kevin Hilman, Stephen Boyd, Michael Turquette, Dmitry Rokosov, robh+dt, Rob Herring Cc: Jian Hu, devicetree, linux-clk, linux-amlogic, linux-kernel, linux-arm-kernel Add Peripheral clock controller driver for the Amlogic T7 SoC family. Signed-off-by: Jian Hu <jian.hu@amlogic.com> --- drivers/clk/meson/Kconfig | 13 + drivers/clk/meson/Makefile | 1 + drivers/clk/meson/t7-peripherals.c | 2359 ++++++++++++++++++++++++++++ 3 files changed, 2373 insertions(+) create mode 100644 drivers/clk/meson/t7-peripherals.c diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig index 8bb4f26a86ed..e32faa24c760 100644 --- a/drivers/clk/meson/Kconfig +++ b/drivers/clk/meson/Kconfig @@ -216,4 +216,17 @@ config COMMON_CLK_T7_PLL device, AKA T7. PLLs are required by most peripheral to operate Say Y if you are a T7 based device. +config COMMON_CLK_T7_PERIPHERALS + tristate "Amlogic T7 SoC peripherals clock controller support" + depends on ARM64 + default y + select COMMON_CLK_MESON_REGMAP + select COMMON_CLK_MESON_CLKC_UTILS + select COMMON_CLK_MESON_DUALDIV + imply COMMON_CLK_SCMI + imply COMMON_CLK_T7_PLL + help + Support for the Peripherals clock controller on Amlogic A311D2 based + device, AKA T7. Peripherals are required by most peripheral to operate + Say Y if you are a T7 based device. endmenu diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile index 646257694c34..6fef3188af30 100644 --- a/drivers/clk/meson/Makefile +++ b/drivers/clk/meson/Makefile @@ -28,3 +28,4 @@ obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o meson8-ddr.o obj-$(CONFIG_COMMON_CLK_S4_PLL) += s4-pll.o obj-$(CONFIG_COMMON_CLK_S4_PERIPHERALS) += s4-peripherals.o obj-$(CONFIG_COMMON_CLK_T7_PLL) += t7-pll.o +obj-$(CONFIG_COMMON_CLK_T7_PERIPHERALS) += t7-peripherals.o diff --git a/drivers/clk/meson/t7-peripherals.c b/drivers/clk/meson/t7-peripherals.c new file mode 100644 index 000000000000..9a0681183eee --- /dev/null +++ b/drivers/clk/meson/t7-peripherals.c @@ -0,0 +1,2359 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR MIT) +/* + * Copyright (C) 2024 Amlogic, Inc. All rights reserved. + * Author: Jian Hu <jian.hu@amlogic.com> + */ + +#include <linux/clk-provider.h> +#include <linux/platform_device.h> +#include "clk-dualdiv.h" +#include "clk-regmap.h" +#include "meson-clkc-utils.h" +#include <dt-bindings/clock/amlogic,t7-peripherals-clkc.h> + +#define CLKCTRL_RTC_BY_OSCIN_CTRL0 0x8 +#define CLKCTRL_RTC_BY_OSCIN_CTRL1 0xc +#define CLKCTRL_RTC_CTRL 0x10 +#define CLKCTRL_SYS_CLK_CTRL0 0x40 +#define CLKCTRL_SYS_CLK_EN0_REG0 0x44 +#define CLKCTRL_SYS_CLK_EN0_REG1 0x48 +#define CLKCTRL_SYS_CLK_EN0_REG2 0x4c +#define CLKCTRL_SYS_CLK_EN0_REG3 0x50 +#define CLKCTRL_CECA_CTRL0 0x88 +#define CLKCTRL_CECA_CTRL1 0x8c +#define CLKCTRL_CECB_CTRL0 0x90 +#define CLKCTRL_CECB_CTRL1 0x94 +#define CLKCTRL_SC_CLK_CTRL 0x98 +#define CLKCTRL_DSPA_CLK_CTRL0 0x9c +#define CLKCTRL_DSPB_CLK_CTRL0 0xa0 +#define CLKCTRL_CLK12_24_CTRL 0xa8 +#define CLKCTRL_ANAKIN_CLK_CTRL 0xac +#define CLKCTRL_MIPI_CSI_PHY_CLK_CTRL 0x10c +#define CLKCTRL_MIPI_ISP_CLK_CTRL 0x110 +#define CLKCTRL_TS_CLK_CTRL 0x158 +#define CLKCTRL_MALI_CLK_CTRL 0x15c +#define CLKCTRL_ETH_CLK_CTRL 0x164 +#define CLKCTRL_NAND_CLK_CTRL 0x168 +#define CLKCTRL_SD_EMMC_CLK_CTRL 0x16c +#define CLKCTRL_SPICC_CLK_CTRL 0x174 +#define CLKCTRL_SAR_CLK_CTRL0 0x17c +#define CLKCTRL_PWM_CLK_AB_CTRL 0x180 +#define CLKCTRL_PWM_CLK_CD_CTRL 0x184 +#define CLKCTRL_PWM_CLK_EF_CTRL 0x188 +#define CLKCTRL_PWM_CLK_AO_AB_CTRL 0x1a0 +#define CLKCTRL_PWM_CLK_AO_CD_CTRL 0x1a4 +#define CLKCTRL_PWM_CLK_AO_EF_CTRL 0x1a8 +#define CLKCTRL_PWM_CLK_AO_GH_CTRL 0x1ac +#define CLKCTRL_SPICC_CLK_CTRL1 0x1c0 +#define CLKCTRL_SPICC_CLK_CTRL2 0x1c4 + +static struct clk_regmap t7_rtc_32k_in = { + .data = &(struct clk_regmap_gate_data){ + .offset = CLKCTRL_RTC_BY_OSCIN_CTRL0, + .bit_idx = 31, + }, + .hw.init = &(struct clk_init_data) { + .name = "t7_rtc_32k_in", + .ops = &clk_regmap_gate_ops, + .parent_data = &(const struct clk_parent_data) { + .fw_name = "xtal", + }, + .num_parents = 1, + }, +}; + +static const struct meson_clk_dualdiv_param t7_clk_32k_div_table[] = { + { + .n1 = 733, .m1 = 8, + .n2 = 732, .m2 = 11, + .dual = 1, + }, + {} +}; + +static struct clk_regmap t7_rtc_32k_div = { + .data = &(struct meson_clk_dualdiv_data){ + .n1 = { + .reg_off = CLKCTRL_RTC_BY_OSCIN_CTRL0, + .shift = 0, + .width = 12, + }, + .n2 = { + .reg_off = CLKCTRL_RTC_BY_OSCIN_CTRL0, + .shift = 12, + .width = 12, + }, + .m1 = { + .reg_off = CLKCTRL_RTC_BY_OSCIN_CTRL1, + .shift = 0, + .width = 12, + }, + .m2 = { + .reg_off = CLKCTRL_RTC_BY_OSCIN_CTRL1, + .shift = 12, + .width = 12, + }, + .dual = { + .reg_off = CLKCTRL_RTC_BY_OSCIN_CTRL0, + .shift = 28, + .width = 1, + }, + .table = t7_clk_32k_div_table, + }, + .hw.init = &(struct clk_init_data){ + .name = "t7_rtc_32k_div", + .ops = &meson_clk_dualdiv_ops, + .parent_hws = (const struct clk_hw *[]) { + &t7_rtc_32k_in.hw + }, + .num_parents = 1, + }, +}; + +static struct clk_regmap t7_rtc_32k_force_sel = { + .data = &(struct clk_regmap_mux_data) { + .offset = CLKCTRL_RTC_BY_OSCIN_CTRL1, + .mask = 0x1, + .shift = 24, + }, + .hw.init = &(struct clk_init_data){ + .name = "t7_rtc_32k_force_sel", + .ops = &clk_regmap_mux_ops, + .parent_hws = (const struct clk_hw *[]) { + &t7_rtc_32k_div.hw, + &t7_rtc_32k_in.hw, + }, + .num_parents = 2, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_rtc_32k_out = { + .data = &(struct clk_regmap_gate_data){ + .offset = CLKCTRL_RTC_BY_OSCIN_CTRL0, + .bit_idx = 30, + }, + .hw.init = &(struct clk_init_data) { + .name = "t7_rtc_32k_out", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &t7_rtc_32k_force_sel.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_rtc_32k_mux0_0 = { + .data = &(struct clk_regmap_mux_data) { + .offset = CLKCTRL_RTC_CTRL, + .mask = 0x1, + .shift = 0, + }, + .hw.init = &(struct clk_init_data){ + .name = "t7_rtc_32k_mux0_0", + .ops = &clk_regmap_mux_ops, + .parent_data = (const struct clk_parent_data []) { + { .fw_name = "xtal", }, + { .hw = &t7_rtc_32k_out.hw }, + }, + .num_parents = 2, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_rtc_32k_mux0_1 = { + .data = &(struct clk_regmap_mux_data) { + .offset = CLKCTRL_RTC_CTRL, + .mask = 0x1, + .shift = 0, + }, + .hw.init = &(struct clk_init_data){ + .name = "t7_rtc_32k_mux0_1", + .ops = &clk_regmap_mux_ops, + .parent_data = (const struct clk_parent_data []) { + { .fw_name = "pad", }, + { .fw_name = "xtal", }, + }, + .num_parents = 2, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_rtc = { + .data = &(struct clk_regmap_mux_data) { + .offset = CLKCTRL_RTC_CTRL, + .mask = 0x1, + .shift = 1, + }, + .hw.init = &(struct clk_init_data){ + .name = "t7_rtc", + .ops = &clk_regmap_mux_ops, + .parent_hws = (const struct clk_hw *[]) { + &t7_rtc_32k_mux0_0.hw, + &t7_rtc_32k_mux0_1.hw, + }, + .num_parents = 2, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_ceca_32k_in = { + .data = &(struct clk_regmap_gate_data){ + .offset = CLKCTRL_CECA_CTRL0, + .bit_idx = 31, + }, + .hw.init = &(struct clk_init_data) { + .name = "t7_ceca_32k_in", + .ops = &clk_regmap_gate_ops, + .parent_data = &(const struct clk_parent_data) { + .fw_name = "xtal", + }, + .num_parents = 1, + }, +}; + +static struct clk_regmap t7_ceca_32k_div = { + .data = &(struct meson_clk_dualdiv_data){ + .n1 = { + .reg_off = CLKCTRL_CECA_CTRL0, + .shift = 0, + .width = 12, + }, + .n2 = { + .reg_off = CLKCTRL_CECA_CTRL0, + .shift = 12, + .width = 12, + }, + .m1 = { + .reg_off = CLKCTRL_CECA_CTRL1, + .shift = 0, + .width = 12, + }, + .m2 = { + .reg_off = CLKCTRL_CECA_CTRL1, + .shift = 12, + .width = 12, + }, + .dual = { + .reg_off = CLKCTRL_CECA_CTRL0, + .shift = 28, + .width = 1, + }, + .table = t7_clk_32k_div_table, + }, + .hw.init = &(struct clk_init_data){ + .name = "t7_ceca_32k_div", + .ops = &meson_clk_dualdiv_ops, + .parent_hws = (const struct clk_hw *[]) { + &t7_ceca_32k_in.hw + }, + .num_parents = 1, + }, +}; + +static struct clk_regmap t7_ceca_32k_sel_pre = { + .data = &(struct clk_regmap_mux_data) { + .offset = CLKCTRL_CECA_CTRL1, + .mask = 0x1, + .shift = 24, + }, + .hw.init = &(struct clk_init_data){ + .name = "t7_ceca_32k_sel_pre", + .ops = &clk_regmap_mux_ops, + .parent_hws = (const struct clk_hw *[]) { + &t7_ceca_32k_div.hw, + &t7_ceca_32k_in.hw, + }, + .num_parents = 2, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_ceca_32k_sel = { + .data = &(struct clk_regmap_mux_data) { + .offset = CLKCTRL_CECA_CTRL1, + .mask = 0x1, + .shift = 31, + }, + .hw.init = &(struct clk_init_data){ + .name = "t7_ceca_32k_sel", + .ops = &clk_regmap_mux_ops, + .parent_hws = (const struct clk_hw *[]) { + &t7_ceca_32k_sel_pre.hw, + &t7_rtc.hw, + }, + .num_parents = 2, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_ceca_32k_out = { + .data = &(struct clk_regmap_gate_data){ + .offset = CLKCTRL_CECA_CTRL0, + .bit_idx = 30, + }, + .hw.init = &(struct clk_init_data){ + .name = "t7_ceca_32k_out", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &t7_ceca_32k_sel.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_cecb_32k_in = { + .data = &(struct clk_regmap_gate_data){ + .offset = CLKCTRL_CECB_CTRL0, + .bit_idx = 31, + }, + .hw.init = &(struct clk_init_data) { + .name = "t7_cecb_32k_in", + .ops = &clk_regmap_gate_ops, + .parent_data = &(const struct clk_parent_data) { + .fw_name = "xtal", + }, + .num_parents = 1, + }, +}; + +static struct clk_regmap t7_cecb_32k_div = { + .data = &(struct meson_clk_dualdiv_data){ + .n1 = { + .reg_off = CLKCTRL_CECB_CTRL0, + .shift = 0, + .width = 12, + }, + .n2 = { + .reg_off = CLKCTRL_CECB_CTRL0, + .shift = 12, + .width = 12, + }, + .m1 = { + .reg_off = CLKCTRL_CECB_CTRL1, + .shift = 0, + .width = 12, + }, + .m2 = { + .reg_off = CLKCTRL_CECB_CTRL1, + .shift = 12, + .width = 12, + }, + .dual = { + .reg_off = CLKCTRL_CECB_CTRL0, + .shift = 28, + .width = 1, + }, + .table = t7_clk_32k_div_table, + }, + .hw.init = &(struct clk_init_data){ + .name = "t7_cecb_32k_div", + .ops = &meson_clk_dualdiv_ops, + .parent_hws = (const struct clk_hw *[]) { + &t7_cecb_32k_in.hw + }, + .num_parents = 1, + }, +}; + +static struct clk_regmap t7_cecb_32k_sel_pre = { + .data = &(struct clk_regmap_mux_data) { + .offset = CLKCTRL_CECB_CTRL1, + .mask = 0x1, + .shift = 24, + }, + .hw.init = &(struct clk_init_data){ + .name = "t7_cecb_32k_sel_pre", + .ops = &clk_regmap_mux_ops, + .parent_hws = (const struct clk_hw *[]) { + &t7_cecb_32k_div.hw, + &t7_cecb_32k_in.hw, + }, + .num_parents = 2, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_cecb_32k_sel = { + .data = &(struct clk_regmap_mux_data) { + .offset = CLKCTRL_CECB_CTRL1, + .mask = 0x1, + .shift = 31, + }, + .hw.init = &(struct clk_init_data){ + .name = "t7_cecb_32k_sel", + .ops = &clk_regmap_mux_ops, + .parent_hws = (const struct clk_hw *[]) { + &t7_cecb_32k_sel_pre.hw, + &t7_rtc.hw, + }, + .num_parents = 2, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_cecb_32k_out = { + .data = &(struct clk_regmap_gate_data){ + .offset = CLKCTRL_CECB_CTRL0, + .bit_idx = 30, + }, + .hw.init = &(struct clk_init_data){ + .name = "t7_cecb_32k_out", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &t7_cecb_32k_sel.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +/* Smartcard Clock */ +static const struct clk_parent_data t7_sc_parents[] = { + { .fw_name = "fdiv4", }, + { .fw_name = "fdiv3", }, + { .fw_name = "fdiv5", }, + { .fw_name = "xtal", }, +}; + +static struct clk_regmap t7_sc_sel = { + .data = &(struct clk_regmap_mux_data){ + .offset = CLKCTRL_SC_CLK_CTRL, + .mask = 0x3, + .shift = 9, + }, + .hw.init = &(struct clk_init_data){ + .name = "t7_sc_sel", + .ops = &clk_regmap_mux_ops, + .parent_data = t7_sc_parents, + .num_parents = ARRAY_SIZE(t7_sc_parents), + }, +}; + +static struct clk_regmap t7_sc_div = { + .data = &(struct clk_regmap_div_data){ + .offset = CLKCTRL_SC_CLK_CTRL, + .shift = 0, + .width = 8, + }, + .hw.init = &(struct clk_init_data){ + .name = "t7_sc_div", + .ops = &clk_regmap_divider_ops, + .parent_hws = (const struct clk_hw *[]) { + &t7_sc_sel.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_sc = { + .data = &(struct clk_regmap_gate_data){ + .offset = CLKCTRL_SC_CLK_CTRL, + .bit_idx = 8, + }, + .hw.init = &(struct clk_init_data) { + .name = "t7_sc", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &t7_sc_div.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +/* + * The DSPA/B IP is clocked by two identical clocks (dspa/b_a and dspa/b_b) + * muxed by a glitch-free switch. + */ +static const struct clk_parent_data t7_dsp_ab_parent_data[] = { + { .fw_name = "xtal", }, + { .fw_name = "fdiv2p5", }, + { .fw_name = "fdiv3", }, + { .fw_name = "fdiv5", }, + { .fw_name = "hifi", }, + { .fw_name = "fdiv4", }, + { .fw_name = "fdiv7", }, + { .hw = &t7_rtc.hw }, +}; + +static struct clk_regmap t7_dspa_a_sel = { + .data = &(struct clk_regmap_mux_data){ + .offset = CLKCTRL_DSPA_CLK_CTRL0, + .mask = 0x7, + .shift = 10, + }, + .hw.init = &(struct clk_init_data){ + .name = "t7_dspa_a_sel", + .ops = &clk_regmap_mux_ops, + .parent_data = t7_dsp_ab_parent_data, + .num_parents = ARRAY_SIZE(t7_dsp_ab_parent_data), + }, +}; + +static struct clk_regmap t7_dspa_a_div = { + .data = &(struct clk_regmap_div_data){ + .offset = CLKCTRL_DSPA_CLK_CTRL0, + .shift = 0, + .width = 10, + }, + .hw.init = &(struct clk_init_data){ + .name = "t7_dspa_a_div", + .ops = &clk_regmap_divider_ops, + .parent_hws = (const struct clk_hw *[]) { + &t7_dspa_a_sel.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_dspa_a = { + .data = &(struct clk_regmap_gate_data){ + .offset = CLKCTRL_DSPA_CLK_CTRL0, + .bit_idx = 13, + }, + .hw.init = &(struct clk_init_data) { + .name = "t7_dspa_a", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &t7_dspa_a_div.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_dspa_b_sel = { + .data = &(struct clk_regmap_mux_data){ + .offset = CLKCTRL_DSPA_CLK_CTRL0, + .mask = 0x7, + .shift = 26, + }, + .hw.init = &(struct clk_init_data){ + .name = "t7_dspa_b_sel", + .ops = &clk_regmap_mux_ops, + .parent_data = t7_dsp_ab_parent_data, + .num_parents = ARRAY_SIZE(t7_dsp_ab_parent_data), + }, +}; + +static struct clk_regmap t7_dspa_b_div = { + .data = &(struct clk_regmap_div_data){ + .offset = CLKCTRL_DSPA_CLK_CTRL0, + .shift = 16, + .width = 10, + }, + .hw.init = &(struct clk_init_data){ + .name = "t7_dspa_b_div", + .ops = &clk_regmap_divider_ops, + .parent_hws = (const struct clk_hw *[]) { + &t7_dspa_b_sel.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_dspa_b = { + .data = &(struct clk_regmap_gate_data){ + .offset = CLKCTRL_DSPA_CLK_CTRL0, + .bit_idx = 29, + }, + .hw.init = &(struct clk_init_data) { + .name = "t7_dspa_b", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &t7_dspa_b_div.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_dspa = { + .data = &(struct clk_regmap_mux_data){ + .offset = CLKCTRL_DSPA_CLK_CTRL0, + .mask = 0x1, + .shift = 15, + }, + .hw.init = &(struct clk_init_data){ + .name = "t7_dspa", + .ops = &clk_regmap_mux_ops, + .parent_hws = (const struct clk_hw *[]) { + &t7_dspa_a.hw, + &t7_dspa_b.hw, + }, + .num_parents = 2, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_dspb_a_sel = { + .data = &(struct clk_regmap_mux_data){ + .offset = CLKCTRL_DSPB_CLK_CTRL0, + .mask = 0x7, + .shift = 10, + }, + .hw.init = &(struct clk_init_data){ + .name = "t7_dspb_a_sel", + .ops = &clk_regmap_mux_ops, + .parent_data = t7_dsp_ab_parent_data, + .num_parents = ARRAY_SIZE(t7_dsp_ab_parent_data), + }, +}; + +static struct clk_regmap t7_dspb_a_div = { + .data = &(struct clk_regmap_div_data){ + .offset = CLKCTRL_DSPB_CLK_CTRL0, + .shift = 0, + .width = 10, + }, + .hw.init = &(struct clk_init_data){ + .name = "t7_dspb_a_div", + .ops = &clk_regmap_divider_ops, + .parent_hws = (const struct clk_hw *[]) { + &t7_dspb_a_sel.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_dspb_a = { + .data = &(struct clk_regmap_gate_data){ + .offset = CLKCTRL_DSPB_CLK_CTRL0, + .bit_idx = 13, + }, + .hw.init = &(struct clk_init_data) { + .name = "t7_dspb_a", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &t7_dspb_a_div.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_dspb_b_sel = { + .data = &(struct clk_regmap_mux_data){ + .offset = CLKCTRL_DSPB_CLK_CTRL0, + .mask = 0x7, + .shift = 26, + }, + .hw.init = &(struct clk_init_data){ + .name = "t7_dspb_b_sel", + .ops = &clk_regmap_mux_ops, + .parent_data = t7_dsp_ab_parent_data, + .num_parents = ARRAY_SIZE(t7_dsp_ab_parent_data), + }, +}; + +static struct clk_regmap t7_dspb_b_div = { + .data = &(struct clk_regmap_div_data){ + .offset = CLKCTRL_DSPB_CLK_CTRL0, + .shift = 16, + .width = 10, + }, + .hw.init = &(struct clk_init_data){ + .name = "t7_dspb_b_div", + .ops = &clk_regmap_divider_ops, + .parent_hws = (const struct clk_hw *[]) { + &t7_dspb_b_sel.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_dspb_b = { + .data = &(struct clk_regmap_gate_data){ + .offset = CLKCTRL_DSPB_CLK_CTRL0, + .bit_idx = 29, + }, + .hw.init = &(struct clk_init_data) { + .name = "t7_dspb_b", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &t7_dspb_b_div.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_dspb = { + .data = &(struct clk_regmap_mux_data){ + .offset = CLKCTRL_DSPB_CLK_CTRL0, + .mask = 0x1, + .shift = 15, + }, + .hw.init = &(struct clk_init_data){ + .name = "t7_dspb", + .ops = &clk_regmap_mux_ops, + .parent_hws = (const struct clk_hw *[]) { + &t7_dspb_a.hw, + &t7_dspb_b.hw, + }, + .num_parents = 2, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_clk_24m = { + .data = &(struct clk_regmap_gate_data){ + .offset = CLKCTRL_CLK12_24_CTRL, + .bit_idx = 11, + }, + .hw.init = &(struct clk_init_data) { + .name = "t7_24m", + .ops = &clk_regmap_gate_ops, + .parent_data = &(const struct clk_parent_data) { + .fw_name = "xtal", + }, + .num_parents = 1, + }, +}; + +static struct clk_fixed_factor t7_clk_24m_div2 = { + .mult = 1, + .div = 2, + .hw.init = &(struct clk_init_data){ + .name = "t7_24m_div2", + .ops = &clk_fixed_factor_ops, + .parent_hws = (const struct clk_hw *[]) { + &t7_clk_24m.hw + }, + .num_parents = 1, + }, +}; + +static struct clk_regmap t7_clk_12m = { + .data = &(struct clk_regmap_gate_data){ + .offset = CLKCTRL_CLK12_24_CTRL, + .bit_idx = 10, + }, + .hw.init = &(struct clk_init_data) { + .name = "t7_12m", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &t7_clk_24m_div2.hw + }, + .num_parents = 1, + }, +}; + +static struct clk_regmap t7_fdiv2_divn_pre = { + .data = &(struct clk_regmap_div_data){ + .offset = CLKCTRL_CLK12_24_CTRL, + .shift = 0, + .width = 8, + }, + .hw.init = &(struct clk_init_data){ + .name = "t7_fdiv2_divn_pre", + .ops = &clk_regmap_divider_ops, + .parent_data = &(const struct clk_parent_data) { + .fw_name = "fdiv2", + }, + .num_parents = 1, + }, +}; + +static struct clk_regmap t7_fdiv2_divn = { + .data = &(struct clk_regmap_gate_data){ + .offset = CLKCTRL_CLK12_24_CTRL, + .bit_idx = 12, + }, + .hw.init = &(struct clk_init_data){ + .name = "t7_fdiv2_divn", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &t7_fdiv2_divn_pre.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +/* + * The NNA IP is clocked by two identical clocks (anakin_0 and anakin_1) + * muxed by a glitch-free switch. + */ +static const struct clk_parent_data t7_anakin_parent_data[] = { + { .fw_name = "fdiv4", }, + { .fw_name = "fdiv3", }, + { .fw_name = "fdiv5", }, + { .fw_name = "fdiv2", }, + { .fw_name = "vid_pll0", }, + { .fw_name = "mpll1", }, + { .fw_name = "mpll2", }, + { .fw_name = "fdiv2p5", }, +}; + +static struct clk_regmap t7_anakin_0_sel = { + .data = &(struct clk_regmap_mux_data){ + .offset = CLKCTRL_ANAKIN_CLK_CTRL, + .mask = 0x7, + .shift = 9, + }, + .hw.init = &(struct clk_init_data){ + .name = "t7_anakin_0_sel", + .ops = &clk_regmap_mux_ops, + .parent_data = t7_anakin_parent_data, + .num_parents = ARRAY_SIZE(t7_anakin_parent_data), + }, +}; + +static struct clk_regmap t7_anakin_0_div = { + .data = &(struct clk_regmap_div_data){ + .offset = CLKCTRL_ANAKIN_CLK_CTRL, + .shift = 0, + .width = 7, + }, + .hw.init = &(struct clk_init_data){ + .name = "t7_anakin_0_div", + .ops = &clk_regmap_divider_ops, + .parent_hws = (const struct clk_hw *[]) { + &t7_anakin_0_sel.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_anakin_0 = { + .data = &(struct clk_regmap_gate_data){ + .offset = CLKCTRL_ANAKIN_CLK_CTRL, + .bit_idx = 8, + }, + .hw.init = &(struct clk_init_data) { + .name = "t7_anakin_0", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { &t7_anakin_0_div.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_anakin_1_sel = { + .data = &(struct clk_regmap_mux_data){ + .offset = CLKCTRL_ANAKIN_CLK_CTRL, + .mask = 0x7, + .shift = 25, + }, + .hw.init = &(struct clk_init_data){ + .name = "t7_anakin_1_sel", + .ops = &clk_regmap_mux_ops, + .parent_data = t7_anakin_parent_data, + .num_parents = ARRAY_SIZE(t7_anakin_parent_data), + }, +}; + +static struct clk_regmap t7_anakin_1_div = { + .data = &(struct clk_regmap_div_data){ + .offset = CLKCTRL_ANAKIN_CLK_CTRL, + .shift = 16, + .width = 7, + }, + .hw.init = &(struct clk_init_data){ + .name = "t7_anakin_1_div", + .ops = &clk_regmap_divider_ops, + .parent_hws = (const struct clk_hw *[]) { + &t7_anakin_1_sel.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_anakin_1 = { + .data = &(struct clk_regmap_gate_data){ + .offset = CLKCTRL_ANAKIN_CLK_CTRL, + .bit_idx = 24, + }, + .hw.init = &(struct clk_init_data) { + .name = "t7_anakin_1", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &t7_anakin_1_div.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_anakin = { + .data = &(struct clk_regmap_mux_data){ + .offset = CLKCTRL_ANAKIN_CLK_CTRL, + .mask = 1, + .shift = 31, + }, + .hw.init = &(struct clk_init_data){ + .name = "t7_anakin_sel", + .ops = &clk_regmap_mux_ops, + .parent_hws = (const struct clk_hw *[]) { + &t7_anakin_0.hw, + &t7_anakin_1.hw + }, + .num_parents = 2, + .flags = CLK_SET_RATE_PARENT + }, +}; + +static struct clk_regmap t7_anakin_clk = { + .data = &(struct clk_regmap_gate_data){ + .offset = CLKCTRL_ANAKIN_CLK_CTRL, + .bit_idx = 30, + }, + .hw.init = &(struct clk_init_data) { + .name = "t7_anakin_clk", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &t7_anakin.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT + }, +}; + +static const struct clk_parent_data t7_mipi_csi_parents[] = { + { .fw_name = "xtal", }, + { .fw_name = "gp1", }, + { .fw_name = "mpll1", }, + { .fw_name = "mpll2", }, + { .fw_name = "fdiv3", }, + { .fw_name = "fdiv4", }, + { .fw_name = "fdiv5", }, + { .fw_name = "fdiv7", }, +}; + +static struct clk_regmap t7_mipi_csi_phy0_sel = { + .data = &(struct clk_regmap_mux_data){ + .offset = CLKCTRL_MIPI_CSI_PHY_CLK_CTRL, + .mask = 0x7, + .shift = 9, + }, + .hw.init = &(struct clk_init_data){ + .name = "t7_mipi_csi_phy0_sel", + .ops = &clk_regmap_mux_ops, + .parent_data = t7_mipi_csi_parents, + .num_parents = ARRAY_SIZE(t7_mipi_csi_parents), + }, +}; + +static struct clk_regmap t7_mipi_csi_phy0_div = { + .data = &(struct clk_regmap_div_data){ + .offset = CLKCTRL_MIPI_CSI_PHY_CLK_CTRL, + .shift = 0, + .width = 7, + }, + .hw.init = &(struct clk_init_data){ + .name = "t7_mipi_csi_phy0_div", + .ops = &clk_regmap_divider_ops, + .parent_hws = (const struct clk_hw *[]) { + &t7_mipi_csi_phy0_sel.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_mipi_csi_phy0 = { + .data = &(struct clk_regmap_gate_data){ + .offset = CLKCTRL_MIPI_CSI_PHY_CLK_CTRL, + .bit_idx = 8, + }, + .hw.init = &(struct clk_init_data) { + .name = "t7_mipi_csi_phy0", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &t7_mipi_csi_phy0_div.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_mipi_csi_phy1_sel = { + .data = &(struct clk_regmap_mux_data){ + .offset = CLKCTRL_MIPI_CSI_PHY_CLK_CTRL, + .mask = 0x7, + .shift = 25, + }, + .hw.init = &(struct clk_init_data){ + .name = "t7_mipi_csi_phy1_sel", + .ops = &clk_regmap_mux_ops, + .parent_data = t7_mipi_csi_parents, + .num_parents = ARRAY_SIZE(t7_mipi_csi_parents), + }, +}; + +static struct clk_regmap t7_mipi_csi_phy1_div = { + .data = &(struct clk_regmap_div_data){ + .offset = CLKCTRL_MIPI_CSI_PHY_CLK_CTRL, + .shift = 16, + .width = 7, + }, + .hw.init = &(struct clk_init_data){ + .name = "t7_mipi_csi_phy1_div", + .ops = &clk_regmap_divider_ops, + .parent_hws = (const struct clk_hw *[]) { + &t7_mipi_csi_phy1_sel.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_mipi_csi_phy1 = { + .data = &(struct clk_regmap_gate_data){ + .offset = CLKCTRL_MIPI_CSI_PHY_CLK_CTRL, + .bit_idx = 24, + }, + .hw.init = &(struct clk_init_data) { + .name = "t7_mipi_csi_phy1", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &t7_mipi_csi_phy1_div.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_mipi_csi_phy = { + .data = &(struct clk_regmap_mux_data){ + .offset = CLKCTRL_MIPI_CSI_PHY_CLK_CTRL, + .mask = 0x1, + .shift = 31, + }, + .hw.init = &(struct clk_init_data){ + .name = "t7_mipi_csi_phy", + .ops = &clk_regmap_mux_ops, + .parent_hws = (const struct clk_hw *[]) { + &t7_mipi_csi_phy0.hw, + &t7_mipi_csi_phy1.hw + }, + .num_parents = 2, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static const struct clk_parent_data t7_mipi_isp_parents[] = { + { .fw_name = "xtal", }, + { .fw_name = "fdiv4", }, + { .fw_name = "fdiv3", }, + { .fw_name = "fdiv5", }, + { .fw_name = "fdiv7", }, + { .fw_name = "mpll2", }, + { .fw_name = "mpll3", }, + { .fw_name = "gp1", }, +}; + +static struct clk_regmap t7_mipi_isp_sel = { + .data = &(struct clk_regmap_mux_data){ + .offset = CLKCTRL_MIPI_ISP_CLK_CTRL, + .mask = 0x7, + .shift = 9, + }, + .hw.init = &(struct clk_init_data){ + .name = "t7_mipi_isp_sel", + .ops = &clk_regmap_mux_ops, + .parent_data = t7_mipi_isp_parents, + .num_parents = ARRAY_SIZE(t7_mipi_isp_parents), + }, +}; + +static struct clk_regmap t7_mipi_isp_div = { + .data = &(struct clk_regmap_div_data){ + .offset = CLKCTRL_MIPI_ISP_CLK_CTRL, + .shift = 0, + .width = 7, + }, + .hw.init = &(struct clk_init_data){ + .name = "t7_mipi_isp_div", + .ops = &clk_regmap_divider_ops, + .parent_hws = (const struct clk_hw *[]) { + &t7_mipi_isp_sel.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_mipi_isp = { + .data = &(struct clk_regmap_gate_data){ + .offset = CLKCTRL_MIPI_ISP_CLK_CTRL, + .bit_idx = 8, + }, + .hw.init = &(struct clk_init_data) { + .name = "t7_mipi_isp", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &t7_mipi_isp_div.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_ts_div = { + .data = &(struct clk_regmap_div_data){ + .offset = CLKCTRL_TS_CLK_CTRL, + .shift = 0, + .width = 8, + }, + .hw.init = &(struct clk_init_data){ + .name = "t7_ts_div", + .ops = &clk_regmap_divider_ops, + .parent_data = &(const struct clk_parent_data) { + .fw_name = "xtal", + }, + .num_parents = 1, + }, +}; + +static struct clk_regmap t7_ts = { + .data = &(struct clk_regmap_gate_data){ + .offset = CLKCTRL_TS_CLK_CTRL, + .bit_idx = 8, + }, + .hw.init = &(struct clk_init_data){ + .name = "t7_ts", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &t7_ts_div.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +/* + * The MALI IP is clocked by two identical clocks (mali_0 and mali_1) + * muxed by a glitch-free switch. + */ +static const struct clk_parent_data t7_mali_parents[] = { + { .fw_name = "xtal", }, + { .fw_name = "gp0", }, + { .fw_name = "gp1", }, + { .fw_name = "fdiv2p5", }, + { .fw_name = "fdiv3", }, + { .fw_name = "fdiv4", }, + { .fw_name = "fdiv5", }, + { .fw_name = "fdiv7", }, +}; + +static struct clk_regmap t7_mali_0_sel = { + .data = &(struct clk_regmap_mux_data){ + .offset = CLKCTRL_MALI_CLK_CTRL, + .mask = 0x7, + .shift = 9, + }, + .hw.init = &(struct clk_init_data){ + .name = "t7_mali_0_sel", + .ops = &clk_regmap_mux_ops, + .parent_data = t7_mali_parents, + .num_parents = ARRAY_SIZE(t7_mali_parents), + }, +}; + +static struct clk_regmap t7_mali_0_div = { + .data = &(struct clk_regmap_div_data){ + .offset = CLKCTRL_MALI_CLK_CTRL, + .shift = 0, + .width = 7, + }, + .hw.init = &(struct clk_init_data){ + .name = "t7_mali_0_div", + .ops = &clk_regmap_divider_ops, + .parent_hws = (const struct clk_hw *[]) { + &t7_mali_0_sel.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_mali_0 = { + .data = &(struct clk_regmap_gate_data){ + .offset = CLKCTRL_MALI_CLK_CTRL, + .bit_idx = 8, + }, + .hw.init = &(struct clk_init_data){ + .name = "t7_mali_0", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &t7_mali_0_div.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_mali_1_sel = { + .data = &(struct clk_regmap_mux_data){ + .offset = CLKCTRL_MALI_CLK_CTRL, + .mask = 0x7, + .shift = 25, + }, + .hw.init = &(struct clk_init_data){ + .name = "t7_mali_1_sel", + .ops = &clk_regmap_mux_ops, + .parent_data = t7_mali_parents, + .num_parents = ARRAY_SIZE(t7_mali_parents), + }, +}; + +static struct clk_regmap t7_mali_1_div = { + .data = &(struct clk_regmap_div_data){ + .offset = CLKCTRL_MALI_CLK_CTRL, + .shift = 16, + .width = 7, + }, + .hw.init = &(struct clk_init_data){ + .name = "t7_mali_1_div", + .ops = &clk_regmap_divider_ops, + .parent_hws = (const struct clk_hw *[]) { + &t7_mali_1_sel.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_mali_1 = { + .data = &(struct clk_regmap_gate_data){ + .offset = CLKCTRL_MALI_CLK_CTRL, + .bit_idx = 24, + }, + .hw.init = &(struct clk_init_data){ + .name = "t7_mali_1", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &t7_mali_1_div.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_mali = { + .data = &(struct clk_regmap_mux_data){ + .offset = CLKCTRL_MALI_CLK_CTRL, + .mask = 1, + .shift = 31, + }, + .hw.init = &(struct clk_init_data){ + .name = "t7_mali", + .ops = &clk_regmap_mux_ops, + .parent_hws = (const struct clk_hw *[]) { + &t7_mali_0.hw, + &t7_mali_1.hw, + }, + .num_parents = 2, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static u32 t7_eth_rmii_table[] = { 0, 7 }; + +static const struct clk_parent_data t7_eth_rmii_parents[] = { + { .fw_name = "fdiv2", }, + { .fw_name = "rmii_pad", }, +}; + +static struct clk_regmap t7_eth_rmii_sel = { + .data = &(struct clk_regmap_mux_data) { + .offset = CLKCTRL_ETH_CLK_CTRL, + .mask = 0x3, + .shift = 9, + .table = t7_eth_rmii_table + }, + .hw.init = &(struct clk_init_data){ + .name = "t7_eth_rmii_sel", + .ops = &clk_regmap_mux_ops, + .parent_data = t7_eth_rmii_parents, + .num_parents = ARRAY_SIZE(t7_eth_rmii_parents), + }, +}; + +static struct clk_regmap t7_eth_rmii_div = { + .data = &(struct clk_regmap_div_data) { + .offset = CLKCTRL_ETH_CLK_CTRL, + .shift = 0, + .width = 7, + }, + .hw.init = &(struct clk_init_data){ + .name = "t7_eth_rmii_div", + .ops = &clk_regmap_divider_ops, + .parent_hws = (const struct clk_hw *[]) { + &t7_eth_rmii_sel.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_eth_rmii = { + .data = &(struct clk_regmap_gate_data) { + .offset = CLKCTRL_ETH_CLK_CTRL, + .bit_idx = 8, + }, + .hw.init = &(struct clk_init_data){ + .name = "t7_eth_rmii", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &t7_eth_rmii_div.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_fixed_factor t7_fdiv2_div8 = { + .mult = 1, + .div = 8, + .hw.init = &(struct clk_init_data){ + .name = "t7_fdiv2_div8", + .ops = &clk_fixed_factor_ops, + .parent_data = &(const struct clk_parent_data) { + .fw_name = "fdiv2", + }, + .num_parents = 1, + }, +}; + +static struct clk_regmap t7_eth_125m = { + .data = &(struct clk_regmap_gate_data) { + .offset = CLKCTRL_ETH_CLK_CTRL, + .bit_idx = 7, + }, + .hw.init = &(struct clk_init_data){ + .name = "t7_eth_125m", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &t7_fdiv2_div8.hw + }, + .num_parents = 1, + }, +}; + +static const struct clk_parent_data t7_sd_emmc_parents[] = { + { .fw_name = "xtal", }, + { .fw_name = "fdiv2", }, + { .fw_name = "fdiv3", }, + { .fw_name = "hifi", }, + { .fw_name = "fdiv2p5", }, + { .fw_name = "mpll2", }, + { .fw_name = "mpll3", }, + { .fw_name = "gp0", }, +}; + +static struct clk_regmap t7_sd_emmc_c_sel = { + .data = &(struct clk_regmap_mux_data){ + .offset = CLKCTRL_NAND_CLK_CTRL, + .mask = 0x7, + .shift = 9, + }, + .hw.init = &(struct clk_init_data) { + .name = "t7_sd_emmc_c_sel", + .ops = &clk_regmap_mux_ops, + .parent_data = t7_sd_emmc_parents, + .num_parents = ARRAY_SIZE(t7_sd_emmc_parents), + }, +}; + +static struct clk_regmap t7_sd_emmc_c_div = { + .data = &(struct clk_regmap_div_data){ + .offset = CLKCTRL_NAND_CLK_CTRL, + .shift = 0, + .width = 7, + }, + .hw.init = &(struct clk_init_data) { + .name = "t7_sd_emmc_c_div", + .ops = &clk_regmap_divider_ops, + .parent_hws = (const struct clk_hw *[]) { + &t7_sd_emmc_c_sel.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_sd_emmc_c = { + .data = &(struct clk_regmap_gate_data){ + .offset = CLKCTRL_NAND_CLK_CTRL, + .bit_idx = 7, + }, + .hw.init = &(struct clk_init_data){ + .name = "t7_sd_emmc_c", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &t7_sd_emmc_c_div.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_sd_emmc_a_sel = { + .data = &(struct clk_regmap_mux_data){ + .offset = CLKCTRL_SD_EMMC_CLK_CTRL, + .mask = 0x7, + .shift = 9, + }, + .hw.init = &(struct clk_init_data) { + .name = "t7_sd_emmc_a_sel", + .ops = &clk_regmap_mux_ops, + .parent_data = t7_sd_emmc_parents, + .num_parents = ARRAY_SIZE(t7_sd_emmc_parents), + }, +}; + +static struct clk_regmap t7_sd_emmc_a_div = { + .data = &(struct clk_regmap_div_data){ + .offset = CLKCTRL_SD_EMMC_CLK_CTRL, + .shift = 0, + .width = 7, + }, + .hw.init = &(struct clk_init_data) { + .name = "t7_sd_emmc_a_div", + .ops = &clk_regmap_divider_ops, + .parent_hws = (const struct clk_hw *[]) { + &t7_sd_emmc_a_sel.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_sd_emmc_a = { + .data = &(struct clk_regmap_gate_data){ + .offset = CLKCTRL_SD_EMMC_CLK_CTRL, + .bit_idx = 7, + }, + .hw.init = &(struct clk_init_data){ + .name = "t7_sd_emmc_a", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &t7_sd_emmc_a_div.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_sd_emmc_b_sel = { + .data = &(struct clk_regmap_mux_data){ + .offset = CLKCTRL_SD_EMMC_CLK_CTRL, + .mask = 0x7, + .shift = 25, + }, + .hw.init = &(struct clk_init_data) { + .name = "t7_sd_emmc_b_sel", + .ops = &clk_regmap_mux_ops, + .parent_data = t7_sd_emmc_parents, + .num_parents = ARRAY_SIZE(t7_sd_emmc_parents), + }, +}; + +static struct clk_regmap t7_sd_emmc_b_div = { + .data = &(struct clk_regmap_div_data){ + .offset = CLKCTRL_SD_EMMC_CLK_CTRL, + .shift = 16, + .width = 7, + }, + .hw.init = &(struct clk_init_data) { + .name = "t7_sd_emmc_b_div", + .ops = &clk_regmap_divider_ops, + .parent_hws = (const struct clk_hw *[]) { + &t7_sd_emmc_b_sel.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_sd_emmc_b = { + .data = &(struct clk_regmap_gate_data){ + .offset = CLKCTRL_SD_EMMC_CLK_CTRL, + .bit_idx = 23, + }, + .hw.init = &(struct clk_init_data){ + .name = "t7_sd_emmc_b", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &t7_sd_emmc_b_div.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +#define SPI_PWM_CLK_MUX(_name, _reg, _mask, _shift, _parent_data) { \ + .data = &(struct clk_regmap_mux_data) { \ + .offset = _reg, \ + .mask = _mask, \ + .shift = _shift, \ + }, \ + .hw.init = &(struct clk_init_data) { \ + .name = #_name "_sel", \ + .ops = &clk_regmap_mux_ops, \ + .parent_data = _parent_data, \ + .num_parents = ARRAY_SIZE(_parent_data), \ + }, \ +} + +#define SPI_PWM_CLK_DIV(_name, _reg, _shift, _width, _parent) { \ + .data = &(struct clk_regmap_div_data) { \ + .offset = _reg, \ + .shift = _shift, \ + .width = _width, \ + }, \ + .hw.init = &(struct clk_init_data) { \ + .name = #_name "_div", \ + .ops = &clk_regmap_divider_ops, \ + .parent_hws = (const struct clk_hw *[]) { \ + &_parent.hw \ + }, \ + .num_parents = 1, \ + .flags = CLK_SET_RATE_PARENT, \ + }, \ +} + +#define SPI_PWM_CLK_GATE(_name, _reg, _bit, _parent) { \ + .data = &(struct clk_regmap_gate_data) { \ + .offset = _reg, \ + .bit_idx = _bit, \ + }, \ + .hw.init = &(struct clk_init_data) { \ + .name = #_name, \ + .ops = &clk_regmap_gate_ops, \ + .parent_hws = (const struct clk_hw *[]) { \ + &_parent.hw \ + }, \ + .num_parents = 1, \ + .flags = CLK_SET_RATE_PARENT, \ + }, \ +} + +static const struct clk_parent_data t7_spicc_parents[] = { + { .fw_name = "xtal", }, + { .fw_name = "sys", }, + { .fw_name = "fdiv4", }, + { .fw_name = "fdiv3", }, + { .fw_name = "fdiv2", }, + { .fw_name = "fdiv5", }, + { .fw_name = "fdiv7", }, + { .fw_name = "gp1", }, +}; + +static struct clk_regmap t7_spicc0_sel = + SPI_PWM_CLK_MUX(t7_spicc0, CLKCTRL_SPICC_CLK_CTRL, 0x7, 7, t7_spicc_parents); +static struct clk_regmap t7_spicc0_div = + SPI_PWM_CLK_DIV(t7_spicc0, CLKCTRL_SPICC_CLK_CTRL, 0, 6, t7_spicc0_sel); +static struct clk_regmap t7_spicc0 = + SPI_PWM_CLK_GATE(t7_spicc0, CLKCTRL_SPICC_CLK_CTRL, 6, t7_spicc0_div); + +static struct clk_regmap t7_spicc1_sel = + SPI_PWM_CLK_MUX(t7_spicc1, CLKCTRL_SPICC_CLK_CTRL, 0x7, 23, t7_spicc_parents); +static struct clk_regmap t7_spicc1_div = + SPI_PWM_CLK_DIV(t7_spicc1, CLKCTRL_SPICC_CLK_CTRL, 16, 6, t7_spicc1_sel); +static struct clk_regmap t7_spicc1 = + SPI_PWM_CLK_GATE(t7_spicc1, CLKCTRL_SPICC_CLK_CTRL, 22, t7_spicc1_div); + +static struct clk_regmap t7_spicc2_sel = + SPI_PWM_CLK_MUX(t7_spicc2, CLKCTRL_SPICC_CLK_CTRL1, 0x7, 7, t7_spicc_parents); +static struct clk_regmap t7_spicc2_div = + SPI_PWM_CLK_DIV(t7_spicc2, CLKCTRL_SPICC_CLK_CTRL1, 0, 6, t7_spicc2_sel); +static struct clk_regmap t7_spicc2 = + SPI_PWM_CLK_GATE(t7_spicc2, CLKCTRL_SPICC_CLK_CTRL1, 6, t7_spicc2_div); + +static struct clk_regmap t7_spicc3_sel = + SPI_PWM_CLK_MUX(t7_spicc3, CLKCTRL_SPICC_CLK_CTRL1, 0x7, 23, t7_spicc_parents); +static struct clk_regmap t7_spicc3_div = + SPI_PWM_CLK_DIV(t7_spicc3, CLKCTRL_SPICC_CLK_CTRL1, 16, 6, t7_spicc3_sel); +static struct clk_regmap t7_spicc3 = + SPI_PWM_CLK_GATE(t7_spicc3, CLKCTRL_SPICC_CLK_CTRL1, 22, t7_spicc3_div); + +static struct clk_regmap t7_spicc4_sel = + SPI_PWM_CLK_MUX(t7_spicc4, CLKCTRL_SPICC_CLK_CTRL2, 0x7, 7, t7_spicc_parents); +static struct clk_regmap t7_spicc4_div = + SPI_PWM_CLK_DIV(t7_spicc4, CLKCTRL_SPICC_CLK_CTRL2, 0, 6, t7_spicc4_sel); +static struct clk_regmap t7_spicc4 = + SPI_PWM_CLK_GATE(t7_spicc4, CLKCTRL_SPICC_CLK_CTRL2, 6, t7_spicc4_div); + +static struct clk_regmap t7_spicc5_sel = + SPI_PWM_CLK_MUX(t7_spicc5, CLKCTRL_SPICC_CLK_CTRL2, 0x7, 23, t7_spicc_parents); +static struct clk_regmap t7_spicc5_div = + SPI_PWM_CLK_DIV(t7_spicc5, CLKCTRL_SPICC_CLK_CTRL2, 16, 6, t7_spicc5_sel); +static struct clk_regmap t7_spicc5 = + SPI_PWM_CLK_GATE(t7_spicc5, CLKCTRL_SPICC_CLK_CTRL2, 22, t7_spicc5_div); + +static struct clk_regmap t7_saradc_sel = { + .data = &(struct clk_regmap_mux_data) { + .offset = CLKCTRL_SAR_CLK_CTRL0, + .mask = 0x1, + .shift = 9, + }, + .hw.init = &(struct clk_init_data){ + .name = "t7_saradc_sel", + .ops = &clk_regmap_mux_ops, + .parent_data = (const struct clk_parent_data []) { + { .fw_name = "xtal", }, + { .fw_name = "sys", }, + }, + .num_parents = 2, + }, +}; + +static struct clk_regmap t7_saradc_div = { + .data = &(struct clk_regmap_div_data) { + .offset = CLKCTRL_SAR_CLK_CTRL0, + .shift = 0, + .width = 8, + }, + .hw.init = &(struct clk_init_data){ + .name = "t7_saradc_div", + .ops = &clk_regmap_divider_ops, + .parent_hws = (const struct clk_hw *[]) { + &t7_saradc_sel.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_saradc = { + .data = &(struct clk_regmap_gate_data) { + .offset = CLKCTRL_SAR_CLK_CTRL0, + .bit_idx = 8, + }, + .hw.init = &(struct clk_init_data){ + .name = "t7_saradc", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &t7_saradc_div.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static const struct clk_parent_data t7_pwm_parents[] = { + { .fw_name = "xtal", }, + { .fw_name = "vid_pll0", }, + { .fw_name = "fdiv4", }, + { .fw_name = "fdiv3", }, +}; + +static struct clk_regmap t7_pwm_a_sel = + SPI_PWM_CLK_MUX(t7_pwm, CLKCTRL_PWM_CLK_AB_CTRL, 0x3, 9, t7_pwm_parents); +static struct clk_regmap t7_pwm_a_div = + SPI_PWM_CLK_DIV(t7_pwm_a, CLKCTRL_PWM_CLK_AB_CTRL, 0, 8, t7_pwm_a_sel); +static struct clk_regmap t7_pwm_a = + SPI_PWM_CLK_GATE(t7_pwm_a, CLKCTRL_PWM_CLK_AB_CTRL, 8, t7_pwm_a_div); + +static struct clk_regmap t7_pwm_b_sel = + SPI_PWM_CLK_MUX(t7_pwm_b, CLKCTRL_PWM_CLK_AB_CTRL, 0x3, 25, t7_pwm_parents); +static struct clk_regmap t7_pwm_b_div = + SPI_PWM_CLK_DIV(t7_pwm_b, CLKCTRL_PWM_CLK_AB_CTRL, 16, 8, t7_pwm_b_sel); +static struct clk_regmap t7_pwm_b = + SPI_PWM_CLK_GATE(t7_pwm_b, CLKCTRL_PWM_CLK_AB_CTRL, 24, t7_pwm_b_div); + +static struct clk_regmap t7_pwm_c_sel = + SPI_PWM_CLK_MUX(t7_pwm_c, CLKCTRL_PWM_CLK_CD_CTRL, 0x3, 9, t7_pwm_parents); +static struct clk_regmap t7_pwm_c_div = + SPI_PWM_CLK_DIV(t7_pwm_c, CLKCTRL_PWM_CLK_CD_CTRL, 0, 8, t7_pwm_c_sel); +static struct clk_regmap t7_pwm_c = + SPI_PWM_CLK_GATE(t7_pwm_c, CLKCTRL_PWM_CLK_CD_CTRL, 8, t7_pwm_c_div); + +static struct clk_regmap t7_pwm_d_sel = + SPI_PWM_CLK_MUX(t7_pwm_d, CLKCTRL_PWM_CLK_CD_CTRL, 0x3, 25, t7_pwm_parents); +static struct clk_regmap t7_pwm_d_div = + SPI_PWM_CLK_DIV(t7_pwm_d, CLKCTRL_PWM_CLK_CD_CTRL, 16, 8, t7_pwm_d_sel); +static struct clk_regmap t7_pwm_d = + SPI_PWM_CLK_GATE(t7_pwm_d, CLKCTRL_PWM_CLK_CD_CTRL, 24, t7_pwm_d_div); + +static struct clk_regmap t7_pwm_e_sel = + SPI_PWM_CLK_MUX(t7_pwm_e, CLKCTRL_PWM_CLK_EF_CTRL, 0x3, 9, t7_pwm_parents); +static struct clk_regmap t7_pwm_e_div = + SPI_PWM_CLK_DIV(t7_pwm_e, CLKCTRL_PWM_CLK_EF_CTRL, 0, 8, t7_pwm_e_sel); +static struct clk_regmap t7_pwm_e = + SPI_PWM_CLK_GATE(t7_pwm_e, CLKCTRL_PWM_CLK_EF_CTRL, 8, t7_pwm_e_div); + +static struct clk_regmap t7_pwm_f_sel = + SPI_PWM_CLK_MUX(t7_pwm_f, CLKCTRL_PWM_CLK_EF_CTRL, 0x3, 25, t7_pwm_parents); +static struct clk_regmap t7_pwm_f_div = + SPI_PWM_CLK_DIV(t7_pwm_f, CLKCTRL_PWM_CLK_EF_CTRL, 16, 8, t7_pwm_f_sel); +static struct clk_regmap t7_pwm_f = + SPI_PWM_CLK_GATE(t7_pwm_f, CLKCTRL_PWM_CLK_EF_CTRL, 24, t7_pwm_f_div); + +static struct clk_regmap t7_pwm_ao_a_sel = + SPI_PWM_CLK_MUX(t7_pwm_ao_a, CLKCTRL_PWM_CLK_AO_AB_CTRL, 0x3, 9, t7_pwm_parents); +static struct clk_regmap t7_pwm_ao_a_div = + SPI_PWM_CLK_DIV(t7_pwm_ao_a, CLKCTRL_PWM_CLK_AO_AB_CTRL, 0, 8, t7_pwm_ao_a_sel); +static struct clk_regmap t7_pwm_ao_a = + SPI_PWM_CLK_GATE(t7_pwm_ao_a, CLKCTRL_PWM_CLK_AO_AB_CTRL, 8, t7_pwm_ao_a_div); + +static struct clk_regmap t7_pwm_ao_b_sel = + SPI_PWM_CLK_MUX(t7_pwm_ao_b, CLKCTRL_PWM_CLK_AO_AB_CTRL, 0x3, 25, t7_pwm_parents); +static struct clk_regmap t7_pwm_ao_b_div = + SPI_PWM_CLK_DIV(t7_pwm_ao_b, CLKCTRL_PWM_CLK_AO_AB_CTRL, 16, 8, t7_pwm_ao_b_sel); +static struct clk_regmap t7_pwm_ao_b = + SPI_PWM_CLK_GATE(t7_pwm_ao_b, CLKCTRL_PWM_CLK_AO_AB_CTRL, 24, t7_pwm_ao_b_div); + +static struct clk_regmap t7_pwm_ao_c_sel = + SPI_PWM_CLK_MUX(t7_pwm_ao_c, CLKCTRL_PWM_CLK_AO_CD_CTRL, 0x3, 9, t7_pwm_parents); +static struct clk_regmap t7_pwm_ao_c_div = + SPI_PWM_CLK_DIV(t7_pwm_ao_c, CLKCTRL_PWM_CLK_AO_CD_CTRL, 0, 8, t7_pwm_ao_c_sel); +static struct clk_regmap t7_pwm_ao_c = + SPI_PWM_CLK_GATE(t7_pwm_ao_c, CLKCTRL_PWM_CLK_AO_CD_CTRL, 8, t7_pwm_ao_c_div); + +static struct clk_regmap t7_pwm_ao_d_sel = + SPI_PWM_CLK_MUX(t7_pwm_ao_d, CLKCTRL_PWM_CLK_AO_CD_CTRL, 0x3, 25, t7_pwm_parents); +static struct clk_regmap t7_pwm_ao_d_div = + SPI_PWM_CLK_DIV(t7_pwm_ao_d, CLKCTRL_PWM_CLK_AO_CD_CTRL, 16, 8, t7_pwm_ao_d_sel); +static struct clk_regmap t7_pwm_ao_d = + SPI_PWM_CLK_GATE(t7_pwm_ao_d, CLKCTRL_PWM_CLK_AO_CD_CTRL, 24, t7_pwm_ao_d_div); + +static struct clk_regmap t7_pwm_ao_e_sel = + SPI_PWM_CLK_MUX(t7_pwm_ao_e, CLKCTRL_PWM_CLK_AO_EF_CTRL, 0x3, 9, t7_pwm_parents); +static struct clk_regmap t7_pwm_ao_e_div = + SPI_PWM_CLK_DIV(t7_pwm_ao_e, CLKCTRL_PWM_CLK_AO_EF_CTRL, 0, 8, t7_pwm_ao_e_sel); +static struct clk_regmap t7_pwm_ao_e = + SPI_PWM_CLK_GATE(t7_pwm_ao_e, CLKCTRL_PWM_CLK_AO_EF_CTRL, 8, t7_pwm_ao_e_div); + +static struct clk_regmap t7_pwm_ao_f_sel = + SPI_PWM_CLK_MUX(t7_pwm_ao_f, CLKCTRL_PWM_CLK_AO_EF_CTRL, 0x3, 25, t7_pwm_parents); +static struct clk_regmap t7_pwm_ao_f_div = + SPI_PWM_CLK_DIV(t7_pwm_ao_f, CLKCTRL_PWM_CLK_AO_EF_CTRL, 16, 8, t7_pwm_ao_f_sel); +static struct clk_regmap t7_pwm_ao_f = + SPI_PWM_CLK_GATE(t7_pwm_ao_f, CLKCTRL_PWM_CLK_AO_EF_CTRL, 24, t7_pwm_ao_f_div); + +static struct clk_regmap t7_pwm_ao_g_sel = + SPI_PWM_CLK_MUX(t7_pwm_ao_g, CLKCTRL_PWM_CLK_AO_GH_CTRL, 0x3, 9, t7_pwm_parents); +static struct clk_regmap t7_pwm_ao_g_div = + SPI_PWM_CLK_DIV(t7_pwm_ao_g, CLKCTRL_PWM_CLK_AO_GH_CTRL, 0, 8, t7_pwm_ao_g_sel); +static struct clk_regmap t7_pwm_ao_g = + SPI_PWM_CLK_GATE(t7_pwm_ao_g, CLKCTRL_PWM_CLK_AO_GH_CTRL, 8, t7_pwm_ao_g_div); + +static struct clk_regmap t7_pwm_ao_h_sel = + SPI_PWM_CLK_MUX(t7_pwm_ao_h, CLKCTRL_PWM_CLK_AO_GH_CTRL, 0x3, 25, t7_pwm_parents); +static struct clk_regmap t7_pwm_ao_h_div = + SPI_PWM_CLK_DIV(t7_pwm_ao_h, CLKCTRL_PWM_CLK_AO_GH_CTRL, 16, 8, t7_pwm_ao_h_sel); +static struct clk_regmap t7_pwm_ao_h = + SPI_PWM_CLK_GATE(t7_pwm_ao_h, CLKCTRL_PWM_CLK_AO_GH_CTRL, 24, t7_pwm_ao_h_div); + +#define MESON_GATE(_name, _reg, _bit) MESON_PCLK_V2(_name, _reg, _bit, sys) + +static MESON_GATE(t7_sys_ddr, CLKCTRL_SYS_CLK_EN0_REG0, 0); +static MESON_GATE(t7_sys_dos, CLKCTRL_SYS_CLK_EN0_REG0, 1); +static MESON_GATE(t7_sys_mipi_dsi_a, CLKCTRL_SYS_CLK_EN0_REG0, 2); +static MESON_GATE(t7_sys_mipi_dsi_b, CLKCTRL_SYS_CLK_EN0_REG0, 3); +static MESON_GATE(t7_sys_ethphy, CLKCTRL_SYS_CLK_EN0_REG0, 4); +static MESON_GATE(t7_sys_mali, CLKCTRL_SYS_CLK_EN0_REG0, 6); +static MESON_GATE(t7_sys_aocpu, CLKCTRL_SYS_CLK_EN0_REG0, 13); +static MESON_GATE(t7_sys_aucpu, CLKCTRL_SYS_CLK_EN0_REG0, 14); +static MESON_GATE(t7_sys_cec, CLKCTRL_SYS_CLK_EN0_REG0, 16); +static MESON_GATE(t7_sys_gdc, CLKCTRL_SYS_CLK_EN0_REG0, 17); +static MESON_GATE(t7_sys_deswarp, CLKCTRL_SYS_CLK_EN0_REG0, 18); +static MESON_GATE(t7_sys_ampipe_nand, CLKCTRL_SYS_CLK_EN0_REG0, 19); +static MESON_GATE(t7_sys_ampipe_eth, CLKCTRL_SYS_CLK_EN0_REG0, 20); +static MESON_GATE(t7_sys_am2axi0, CLKCTRL_SYS_CLK_EN0_REG0, 21); +static MESON_GATE(t7_sys_am2axi1, CLKCTRL_SYS_CLK_EN0_REG0, 22); +static MESON_GATE(t7_sys_am2axi2, CLKCTRL_SYS_CLK_EN0_REG0, 23); +static MESON_GATE(t7_sys_sdemmca, CLKCTRL_SYS_CLK_EN0_REG0, 24); +static MESON_GATE(t7_sys_sdemmcb, CLKCTRL_SYS_CLK_EN0_REG0, 25); +static MESON_GATE(t7_sys_sdemmcc, CLKCTRL_SYS_CLK_EN0_REG0, 26); +static MESON_GATE(t7_sys_smartcard, CLKCTRL_SYS_CLK_EN0_REG0, 27); +static MESON_GATE(t7_sys_acodec, CLKCTRL_SYS_CLK_EN0_REG0, 28); +static MESON_GATE(t7_sys_spifc, CLKCTRL_SYS_CLK_EN0_REG0, 29); +static MESON_GATE(t7_sys_msr_clk, CLKCTRL_SYS_CLK_EN0_REG0, 30); +static MESON_GATE(t7_sys_ir_ctrl, CLKCTRL_SYS_CLK_EN0_REG0, 31); +static MESON_GATE(t7_sys_audio, CLKCTRL_SYS_CLK_EN0_REG1, 0); +static MESON_GATE(t7_sys_eth, CLKCTRL_SYS_CLK_EN0_REG1, 3); +static MESON_GATE(t7_sys_uart_a, CLKCTRL_SYS_CLK_EN0_REG1, 5); +static MESON_GATE(t7_sys_uart_b, CLKCTRL_SYS_CLK_EN0_REG1, 6); +static MESON_GATE(t7_sys_uart_c, CLKCTRL_SYS_CLK_EN0_REG1, 7); +static MESON_GATE(t7_sys_uart_d, CLKCTRL_SYS_CLK_EN0_REG1, 8); +static MESON_GATE(t7_sys_uart_e, CLKCTRL_SYS_CLK_EN0_REG1, 9); +static MESON_GATE(t7_sys_uart_f, CLKCTRL_SYS_CLK_EN0_REG1, 10); +static MESON_GATE(t7_sys_aififo, CLKCTRL_SYS_CLK_EN0_REG1, 11); +static MESON_GATE(t7_sys_spicc2, CLKCTRL_SYS_CLK_EN0_REG1, 12); +static MESON_GATE(t7_sys_spicc3, CLKCTRL_SYS_CLK_EN0_REG1, 13); +static MESON_GATE(t7_sys_spicc4, CLKCTRL_SYS_CLK_EN0_REG1, 14); +static MESON_GATE(t7_sys_ts_a73, CLKCTRL_SYS_CLK_EN0_REG1, 15); +static MESON_GATE(t7_sys_ts_a53, CLKCTRL_SYS_CLK_EN0_REG1, 16); +static MESON_GATE(t7_sys_spicc5, CLKCTRL_SYS_CLK_EN0_REG1, 17); +static MESON_GATE(t7_sys_g2d, CLKCTRL_SYS_CLK_EN0_REG1, 20); +static MESON_GATE(t7_sys_spicc0, CLKCTRL_SYS_CLK_EN0_REG1, 21); +static MESON_GATE(t7_sys_spicc1, CLKCTRL_SYS_CLK_EN0_REG1, 22); +static MESON_GATE(t7_sys_pcie, CLKCTRL_SYS_CLK_EN0_REG1, 24); +static MESON_GATE(t7_sys_usb, CLKCTRL_SYS_CLK_EN0_REG1, 26); +static MESON_GATE(t7_sys_pcie_phy, CLKCTRL_SYS_CLK_EN0_REG1, 27); +static MESON_GATE(t7_sys_i2c_ao_a, CLKCTRL_SYS_CLK_EN0_REG1, 28); +static MESON_GATE(t7_sys_i2c_ao_b, CLKCTRL_SYS_CLK_EN0_REG1, 29); +static MESON_GATE(t7_sys_i2c_m_a, CLKCTRL_SYS_CLK_EN0_REG1, 30); +static MESON_GATE(t7_sys_i2c_m_b, CLKCTRL_SYS_CLK_EN0_REG1, 31); +static MESON_GATE(t7_sys_i2c_m_c, CLKCTRL_SYS_CLK_EN0_REG2, 0); +static MESON_GATE(t7_sys_i2c_m_d, CLKCTRL_SYS_CLK_EN0_REG2, 1); +static MESON_GATE(t7_sys_i2c_m_e, CLKCTRL_SYS_CLK_EN0_REG2, 2); +static MESON_GATE(t7_sys_i2c_m_f, CLKCTRL_SYS_CLK_EN0_REG2, 3); +static MESON_GATE(t7_sys_hdmitx_apb, CLKCTRL_SYS_CLK_EN0_REG2, 4); +static MESON_GATE(t7_sys_i2c_s_a, CLKCTRL_SYS_CLK_EN0_REG2, 5); +static MESON_GATE(t7_sys_hdmirx_pclk, CLKCTRL_SYS_CLK_EN0_REG2, 8); +static MESON_GATE(t7_sys_mmc_apb, CLKCTRL_SYS_CLK_EN0_REG2, 11); +static MESON_GATE(t7_sys_mipi_isp_pclk, CLKCTRL_SYS_CLK_EN0_REG2, 17); +static MESON_GATE(t7_sys_rsa, CLKCTRL_SYS_CLK_EN0_REG2, 18); +static MESON_GATE(t7_sys_pclk_sys_apb, CLKCTRL_SYS_CLK_EN0_REG2, 19); +static MESON_GATE(t7_sys_a73pclk_apb, CLKCTRL_SYS_CLK_EN0_REG2, 20); +static MESON_GATE(t7_sys_dspa, CLKCTRL_SYS_CLK_EN0_REG2, 21); +static MESON_GATE(t7_sys_dspb, CLKCTRL_SYS_CLK_EN0_REG2, 22); +static MESON_GATE(t7_sys_vpu_intr, CLKCTRL_SYS_CLK_EN0_REG2, 25); +static MESON_GATE(t7_sys_sar_adc, CLKCTRL_SYS_CLK_EN0_REG2, 28); +static MESON_GATE(t7_sys_ts_gpu, CLKCTRL_SYS_CLK_EN0_REG2, 31); +static MESON_GATE(t7_sys_ts_nna, CLKCTRL_SYS_CLK_EN0_REG3, 0); +static MESON_GATE(t7_sys_ts_vpu, CLKCTRL_SYS_CLK_EN0_REG3, 1); +static MESON_GATE(t7_sys_ts_hevc, CLKCTRL_SYS_CLK_EN0_REG3, 2); +static MESON_GATE(t7_sys_pwm_ao_ab, CLKCTRL_SYS_CLK_EN0_REG3, 3); +static MESON_GATE(t7_sys_pwm_ao_cd, CLKCTRL_SYS_CLK_EN0_REG3, 4); +static MESON_GATE(t7_sys_pwm_ao_ef, CLKCTRL_SYS_CLK_EN0_REG3, 5); +static MESON_GATE(t7_sys_pwm_ao_gh, CLKCTRL_SYS_CLK_EN0_REG3, 6); +static MESON_GATE(t7_sys_pwm_ab, CLKCTRL_SYS_CLK_EN0_REG3, 7); +static MESON_GATE(t7_sys_pwm_cd, CLKCTRL_SYS_CLK_EN0_REG3, 8); +static MESON_GATE(t7_sys_pwm_ef, CLKCTRL_SYS_CLK_EN0_REG3, 9); + +/* + * sys_gic provides the clock for GIC(Generic Interrupt Controller). + * After clock is disabled, The GIC cannot work properly. At present, the driver + * used by our GIC is the public driver in kernel, and there is no management + * clock in the driver. + */ +static struct clk_regmap t7_sys_gic = { + .data = &(struct clk_regmap_gate_data) { + .offset = CLKCTRL_SYS_CLK_EN0_REG2, + .bit_idx = 30, + }, + .hw.init = &(struct clk_init_data){ + .name = "t7_sys_gic", + .ops = &clk_regmap_gate_ops, + .parent_data = &(const struct clk_parent_data) { + .fw_name = "sys", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, + }, +}; + +/* Array of all clocks registered by this provider */ +static struct clk_hw *t7_periphs_hw_clks[] = { + [CLKID_RTC_32K_IN] = &t7_rtc_32k_in.hw, + [CLKID_RTC_32K_DIV] = &t7_rtc_32k_div.hw, + [CLKID_RTC_32K_FORCE_SEL] = &t7_rtc_32k_force_sel.hw, + [CLKID_RTC_32K_OUT] = &t7_rtc_32k_out.hw, + [CLKID_RTC_32K_MUX0_0] = &t7_rtc_32k_mux0_0.hw, + [CLKID_RTC_32K_MUX0_1] = &t7_rtc_32k_mux0_1.hw, + [CLKID_RTC] = &t7_rtc.hw, + [CLKID_CECB_32K_IN] = &t7_cecb_32k_in.hw, + [CLKID_CECB_32K_DIV] = &t7_cecb_32k_div.hw, + [CLKID_CECB_32K_SEL_PRE] = &t7_cecb_32k_sel_pre.hw, + [CLKID_CECB_32K_SEL] = &t7_cecb_32k_sel.hw, + [CLKID_CECA_32K_IN] = &t7_ceca_32k_in.hw, + [CLKID_CECA_32K_DIV] = &t7_ceca_32k_div.hw, + [CLKID_CECA_32K_SEL_PRE] = &t7_ceca_32k_sel_pre.hw, + [CLKID_CECA_32K_SEL] = &t7_ceca_32k_sel.hw, + [CLKID_CECA_32K] = &t7_ceca_32k_out.hw, + [CLKID_CECB_32K] = &t7_cecb_32k_out.hw, + [CLKID_SC_SEL] = &t7_sc_sel.hw, + [CLKID_SC_DIV] = &t7_sc_div.hw, + [CLKID_SC] = &t7_sc.hw, + [CLKID_DSPA_A_SEL] = &t7_dspa_a_sel.hw, + [CLKID_DSPA_A_DIV] = &t7_dspa_a_div.hw, + [CLKID_DSPA_A] = &t7_dspa_a.hw, + [CLKID_DSPA_B_SEL] = &t7_dspa_b_sel.hw, + [CLKID_DSPA_B_DIV] = &t7_dspa_b_div.hw, + [CLKID_DSPA_B] = &t7_dspa_b.hw, + [CLKID_DSPA] = &t7_dspa.hw, + [CLKID_DSPB_A_SEL] = &t7_dspb_a_sel.hw, + [CLKID_DSPB_A_DIV] = &t7_dspb_a_div.hw, + [CLKID_DSPB_A] = &t7_dspb_a.hw, + [CLKID_DSPB_B_SEL] = &t7_dspb_b_sel.hw, + [CLKID_DSPB_B_DIV] = &t7_dspb_b_div.hw, + [CLKID_DSPB_B] = &t7_dspb_b.hw, + [CLKID_DSPB] = &t7_dspb.hw, + [CLKID_CLK_24M] = &t7_clk_24m.hw, + [CLKID_CLK_24M_DIV2] = &t7_clk_24m_div2.hw, + [CLKID_CLK_12M] = &t7_clk_12m.hw, + [CLKID_ANAKIN_0_SEL] = &t7_anakin_0_sel.hw, + [CLKID_ANAKIN_0_DIV] = &t7_anakin_0_div.hw, + [CLKID_ANAKIN_0] = &t7_anakin_0.hw, + [CLKID_ANAKIN_1_SEL] = &t7_anakin_1_sel.hw, + [CLKID_ANAKIN_1_DIV] = &t7_anakin_1_div.hw, + [CLKID_ANAKIN_1] = &t7_anakin_1.hw, + [CLKID_ANAKIN] = &t7_anakin.hw, + [CLKID_ANAKIN_CLK] = &t7_anakin_clk.hw, + [CLKID_FCLK_DIV2_DIVN_PRE] = &t7_fdiv2_divn_pre.hw, + [CLKID_FCLK_DIV2_DIVN] = &t7_fdiv2_divn.hw, + [CLKID_MIPI_CSI_PHY_0_SEL] = &t7_mipi_csi_phy0_sel.hw, + [CLKID_MIPI_CSI_PHY_0_DIV] = &t7_mipi_csi_phy0_div.hw, + [CLKID_MIPI_CSI_PHY_0] = &t7_mipi_csi_phy0.hw, + [CLKID_MIPI_CSI_PHY_1_SEL] = &t7_mipi_csi_phy1_sel.hw, + [CLKID_MIPI_CSI_PHY_1_DIV] = &t7_mipi_csi_phy1_div.hw, + [CLKID_MIPI_CSI_PHY_1] = &t7_mipi_csi_phy1.hw, + [CLKID_MIPI_CSI_PHY] = &t7_mipi_csi_phy.hw, + [CLKID_MIPI_ISP_SEL] = &t7_mipi_isp_sel.hw, + [CLKID_MIPI_ISP_DIV] = &t7_mipi_isp_div.hw, + [CLKID_MIPI_ISP] = &t7_mipi_isp.hw, + [CLKID_TS_DIV] = &t7_ts_div.hw, + [CLKID_TS] = &t7_ts.hw, + [CLKID_MALI_0_SEL] = &t7_mali_0_sel.hw, + [CLKID_MALI_0_DIV] = &t7_mali_0_div.hw, + [CLKID_MALI_0] = &t7_mali_0.hw, + [CLKID_MALI_1_SEL] = &t7_mali_1_sel.hw, + [CLKID_MALI_1_DIV] = &t7_mali_1_div.hw, + [CLKID_MALI_1] = &t7_mali_1.hw, + [CLKID_MALI] = &t7_mali.hw, + [CLKID_ETH_RMII_SEL] = &t7_eth_rmii_sel.hw, + [CLKID_ETH_RMII_DIV] = &t7_eth_rmii_div.hw, + [CLKID_ETH_RMII] = &t7_eth_rmii.hw, + [CLKID_FCLK_DIV2_DIV8] = &t7_fdiv2_div8.hw, + [CLKID_ETH_125M] = &t7_eth_125m.hw, + [CLKID_SD_EMMC_C_SEL] = &t7_sd_emmc_c_sel.hw, + [CLKID_SD_EMMC_C_DIV] = &t7_sd_emmc_c_div.hw, + [CLKID_SD_EMMC_C] = &t7_sd_emmc_c.hw, + [CLKID_SD_EMMC_A_SEL] = &t7_sd_emmc_a_sel.hw, + [CLKID_SD_EMMC_A_DIV] = &t7_sd_emmc_a_div.hw, + [CLKID_SD_EMMC_A] = &t7_sd_emmc_a.hw, + [CLKID_SD_EMMC_B_SEL] = &t7_sd_emmc_b_sel.hw, + [CLKID_SD_EMMC_B_DIV] = &t7_sd_emmc_b_div.hw, + [CLKID_SD_EMMC_B] = &t7_sd_emmc_b.hw, + [CLKID_SPICC0_SEL] = &t7_spicc0_sel.hw, + [CLKID_SPICC0_DIV] = &t7_spicc0_div.hw, + [CLKID_SPICC0] = &t7_spicc0.hw, + [CLKID_SPICC1_SEL] = &t7_spicc1_sel.hw, + [CLKID_SPICC1_DIV] = &t7_spicc1_div.hw, + [CLKID_SPICC1] = &t7_spicc1.hw, + [CLKID_SPICC2_SEL] = &t7_spicc2_sel.hw, + [CLKID_SPICC2_DIV] = &t7_spicc2_div.hw, + [CLKID_SPICC2] = &t7_spicc2.hw, + [CLKID_SPICC3_SEL] = &t7_spicc3_sel.hw, + [CLKID_SPICC3_DIV] = &t7_spicc3_div.hw, + [CLKID_SPICC3] = &t7_spicc3.hw, + [CLKID_SPICC4_SEL] = &t7_spicc4_sel.hw, + [CLKID_SPICC4_DIV] = &t7_spicc4_div.hw, + [CLKID_SPICC4] = &t7_spicc4.hw, + [CLKID_SPICC5_SEL] = &t7_spicc5_sel.hw, + [CLKID_SPICC5_DIV] = &t7_spicc5_div.hw, + [CLKID_SPICC5] = &t7_spicc5.hw, + [CLKID_SARADC_SEL] = &t7_saradc_sel.hw, + [CLKID_SARADC_DIV] = &t7_saradc_div.hw, + [CLKID_SARADC] = &t7_saradc.hw, + [CLKID_PWM_A_SEL] = &t7_pwm_a_sel.hw, + [CLKID_PWM_A_DIV] = &t7_pwm_a_div.hw, + [CLKID_PWM_A] = &t7_pwm_a.hw, + [CLKID_PWM_B_SEL] = &t7_pwm_b_sel.hw, + [CLKID_PWM_B_DIV] = &t7_pwm_b_div.hw, + [CLKID_PWM_B] = &t7_pwm_b.hw, + [CLKID_PWM_C_SEL] = &t7_pwm_c_sel.hw, + [CLKID_PWM_C_DIV] = &t7_pwm_c_div.hw, + [CLKID_PWM_C] = &t7_pwm_c.hw, + [CLKID_PWM_D_SEL] = &t7_pwm_d_sel.hw, + [CLKID_PWM_D_DIV] = &t7_pwm_d_div.hw, + [CLKID_PWM_D] = &t7_pwm_d.hw, + [CLKID_PWM_E_SEL] = &t7_pwm_e_sel.hw, + [CLKID_PWM_E_DIV] = &t7_pwm_e_div.hw, + [CLKID_PWM_E] = &t7_pwm_e.hw, + [CLKID_PWM_F_SEL] = &t7_pwm_f_sel.hw, + [CLKID_PWM_F_DIV] = &t7_pwm_f_div.hw, + [CLKID_PWM_F] = &t7_pwm_f.hw, + [CLKID_PWM_AO_A_SEL] = &t7_pwm_ao_a_sel.hw, + [CLKID_PWM_AO_A_DIV] = &t7_pwm_ao_a_div.hw, + [CLKID_PWM_AO_A] = &t7_pwm_ao_a.hw, + [CLKID_PWM_AO_B_SEL] = &t7_pwm_ao_b_sel.hw, + [CLKID_PWM_AO_B_DIV] = &t7_pwm_ao_b_div.hw, + [CLKID_PWM_AO_B] = &t7_pwm_ao_b.hw, + [CLKID_PWM_AO_C_SEL] = &t7_pwm_ao_c_sel.hw, + [CLKID_PWM_AO_C_DIV] = &t7_pwm_ao_c_div.hw, + [CLKID_PWM_AO_C] = &t7_pwm_ao_c.hw, + [CLKID_PWM_AO_D_SEL] = &t7_pwm_ao_d_sel.hw, + [CLKID_PWM_AO_D_DIV] = &t7_pwm_ao_d_div.hw, + [CLKID_PWM_AO_D] = &t7_pwm_ao_d.hw, + [CLKID_PWM_AO_E_SEL] = &t7_pwm_ao_e_sel.hw, + [CLKID_PWM_AO_E_DIV] = &t7_pwm_ao_e_div.hw, + [CLKID_PWM_AO_E] = &t7_pwm_ao_e.hw, + [CLKID_PWM_AO_F_SEL] = &t7_pwm_ao_f_sel.hw, + [CLKID_PWM_AO_F_DIV] = &t7_pwm_ao_f_div.hw, + [CLKID_PWM_AO_F] = &t7_pwm_ao_f.hw, + [CLKID_PWM_AO_G_SEL] = &t7_pwm_ao_g_sel.hw, + [CLKID_PWM_AO_G_DIV] = &t7_pwm_ao_g_div.hw, + [CLKID_PWM_AO_G] = &t7_pwm_ao_g.hw, + [CLKID_PWM_AO_H_SEL] = &t7_pwm_ao_h_sel.hw, + [CLKID_PWM_AO_H_DIV] = &t7_pwm_ao_h_div.hw, + [CLKID_PWM_AO_H] = &t7_pwm_ao_h.hw, + [CLKID_SYS_DDR] = &t7_sys_ddr.hw, + [CLKID_SYS_DOS] = &t7_sys_dos.hw, + [CLKID_SYS_MIPI_DSI_A] = &t7_sys_mipi_dsi_a.hw, + [CLKID_SYS_MIPI_DSI_B] = &t7_sys_mipi_dsi_b.hw, + [CLKID_SYS_ETHPHY] = &t7_sys_ethphy.hw, + [CLKID_SYS_MALI] = &t7_sys_mali.hw, + [CLKID_SYS_AOCPU] = &t7_sys_aocpu.hw, + [CLKID_SYS_AUCPU] = &t7_sys_aucpu.hw, + [CLKID_SYS_CEC] = &t7_sys_cec.hw, + [CLKID_SYS_GDC] = &t7_sys_gdc.hw, + [CLKID_SYS_DESWARP] = &t7_sys_deswarp.hw, + [CLKID_SYS_AMPIPE_NAND] = &t7_sys_ampipe_nand.hw, + [CLKID_SYS_AMPIPE_ETH] = &t7_sys_ampipe_eth.hw, + [CLKID_SYS_AM2AXI0] = &t7_sys_am2axi0.hw, + [CLKID_SYS_AM2AXI1] = &t7_sys_am2axi1.hw, + [CLKID_SYS_AM2AXI2] = &t7_sys_am2axi2.hw, + [CLKID_SYS_SD_EMMC_A] = &t7_sys_sdemmca.hw, + [CLKID_SYS_SD_EMMC_B] = &t7_sys_sdemmcb.hw, + [CLKID_SYS_SD_EMMC_C] = &t7_sys_sdemmcc.hw, + [CLKID_SYS_SMARTCARD] = &t7_sys_smartcard.hw, + [CLKID_SYS_ACODEC] = &t7_sys_acodec.hw, + [CLKID_SYS_SPIFC] = &t7_sys_spifc.hw, + [CLKID_SYS_MSR_CLK] = &t7_sys_msr_clk.hw, + [CLKID_SYS_IR_CTRL] = &t7_sys_ir_ctrl.hw, + [CLKID_SYS_AUDIO] = &t7_sys_audio.hw, + [CLKID_SYS_ETH] = &t7_sys_eth.hw, + [CLKID_SYS_UART_A] = &t7_sys_uart_a.hw, + [CLKID_SYS_UART_B] = &t7_sys_uart_b.hw, + [CLKID_SYS_UART_C] = &t7_sys_uart_c.hw, + [CLKID_SYS_UART_D] = &t7_sys_uart_d.hw, + [CLKID_SYS_UART_E] = &t7_sys_uart_e.hw, + [CLKID_SYS_UART_F] = &t7_sys_uart_f.hw, + [CLKID_SYS_AIFIFO] = &t7_sys_aififo.hw, + [CLKID_SYS_SPICC2] = &t7_sys_spicc2.hw, + [CLKID_SYS_SPICC3] = &t7_sys_spicc3.hw, + [CLKID_SYS_SPICC4] = &t7_sys_spicc4.hw, + [CLKID_SYS_TS_A73] = &t7_sys_ts_a73.hw, + [CLKID_SYS_TS_A53] = &t7_sys_ts_a53.hw, + [CLKID_SYS_SPICC5] = &t7_sys_spicc5.hw, + [CLKID_SYS_G2D] = &t7_sys_g2d.hw, + [CLKID_SYS_SPICC0] = &t7_sys_spicc0.hw, + [CLKID_SYS_SPICC1] = &t7_sys_spicc1.hw, + [CLKID_SYS_PCIE] = &t7_sys_pcie.hw, + [CLKID_SYS_USB] = &t7_sys_usb.hw, + [CLKID_SYS_PCIE_PHY] = &t7_sys_pcie_phy.hw, + [CLKID_SYS_I2C_AO_A] = &t7_sys_i2c_ao_a.hw, + [CLKID_SYS_I2C_AO_B] = &t7_sys_i2c_ao_b.hw, + [CLKID_SYS_I2C_M_A] = &t7_sys_i2c_m_a.hw, + [CLKID_SYS_I2C_M_B] = &t7_sys_i2c_m_b.hw, + [CLKID_SYS_I2C_M_C] = &t7_sys_i2c_m_c.hw, + [CLKID_SYS_I2C_M_D] = &t7_sys_i2c_m_d.hw, + [CLKID_SYS_I2C_M_E] = &t7_sys_i2c_m_e.hw, + [CLKID_SYS_I2C_M_F] = &t7_sys_i2c_m_f.hw, + [CLKID_SYS_HDMITX_APB] = &t7_sys_hdmitx_apb.hw, + [CLKID_SYS_I2C_S_A] = &t7_sys_i2c_s_a.hw, + [CLKID_SYS_HDMIRX_PCLK] = &t7_sys_hdmirx_pclk.hw, + [CLKID_SYS_MMC_APB] = &t7_sys_mmc_apb.hw, + [CLKID_SYS_MIPI_ISP_PCLK] = &t7_sys_mipi_isp_pclk.hw, + [CLKID_SYS_RSA] = &t7_sys_rsa.hw, + [CLKID_SYS_PCLK_SYS_APB] = &t7_sys_pclk_sys_apb.hw, + [CLKID_SYS_A73PCLK_APB] = &t7_sys_a73pclk_apb.hw, + [CLKID_SYS_DSPA] = &t7_sys_dspa.hw, + [CLKID_SYS_DSPB] = &t7_sys_dspb.hw, + [CLKID_SYS_VPU_INTR] = &t7_sys_vpu_intr.hw, + [CLKID_SYS_SAR_ADC] = &t7_sys_sar_adc.hw, + [CLKID_SYS_GIC] = &t7_sys_gic.hw, + [CLKID_SYS_TS_GPU] = &t7_sys_ts_gpu.hw, + [CLKID_SYS_TS_NNA] = &t7_sys_ts_nna.hw, + [CLKID_SYS_TS_VPU] = &t7_sys_ts_vpu.hw, + [CLKID_SYS_TS_HEVC] = &t7_sys_ts_hevc.hw, + [CLKID_SYS_PWM_AB] = &t7_sys_pwm_ab.hw, + [CLKID_SYS_PWM_CD] = &t7_sys_pwm_cd.hw, + [CLKID_SYS_PWM_EF] = &t7_sys_pwm_ef.hw, + [CLKID_SYS_PWM_AO_AB] = &t7_sys_pwm_ao_ab.hw, + [CLKID_SYS_PWM_AO_CD] = &t7_sys_pwm_ao_cd.hw, + [CLKID_SYS_PWM_AO_EF] = &t7_sys_pwm_ao_ef.hw, + [CLKID_SYS_PWM_AO_GH] = &t7_sys_pwm_ao_gh.hw, +}; + +/* Convenience table to populate regmap in .probe */ +static struct clk_regmap *const t7_periphs_regmaps[] = { + &t7_rtc_32k_in, + &t7_rtc_32k_div, + &t7_rtc_32k_force_sel, + &t7_rtc_32k_out, + &t7_rtc_32k_mux0_0, + &t7_rtc_32k_mux0_1, + &t7_rtc, + &t7_cecb_32k_in, + &t7_cecb_32k_div, + &t7_cecb_32k_sel_pre, + &t7_cecb_32k_sel, + &t7_ceca_32k_in, + &t7_ceca_32k_div, + &t7_ceca_32k_sel_pre, + &t7_ceca_32k_sel, + &t7_ceca_32k_out, + &t7_cecb_32k_out, + &t7_sc_sel, + &t7_sc_div, + &t7_sc, + &t7_dspa_a_sel, + &t7_dspa_a_div, + &t7_dspa_a, + &t7_dspa_b_sel, + &t7_dspa_b_div, + &t7_dspa_b, + &t7_dspa, + &t7_dspb_a_sel, + &t7_dspb_a_div, + &t7_dspb_a, + &t7_dspb_b_sel, + &t7_dspb_b_div, + &t7_dspb_b, + &t7_dspb, + &t7_clk_24m, + &t7_clk_12m, + &t7_anakin_0_sel, + &t7_anakin_0_div, + &t7_anakin_0, + &t7_anakin_1_sel, + &t7_anakin_1_div, + &t7_anakin_1, + &t7_anakin, + &t7_anakin_clk, + &t7_fdiv2_divn_pre, + &t7_fdiv2_divn, + &t7_mipi_csi_phy0_sel, + &t7_mipi_csi_phy0_div, + &t7_mipi_csi_phy0, + &t7_mipi_csi_phy1_sel, + &t7_mipi_csi_phy1_div, + &t7_mipi_csi_phy1, + &t7_mipi_csi_phy, + &t7_mipi_isp_sel, + &t7_mipi_isp_div, + &t7_mipi_isp, + &t7_ts_div, + &t7_ts, + &t7_mali_0_sel, + &t7_mali_0_div, + &t7_mali_0, + &t7_mali_1_sel, + &t7_mali_1_div, + &t7_mali_1, + &t7_mali, + &t7_eth_rmii_sel, + &t7_eth_rmii_div, + &t7_eth_rmii, + &t7_eth_125m, + &t7_sd_emmc_c_sel, + &t7_sd_emmc_c_div, + &t7_sd_emmc_c, + &t7_sd_emmc_a_sel, + &t7_sd_emmc_a_div, + &t7_sd_emmc_a, + &t7_sd_emmc_b_sel, + &t7_sd_emmc_b_div, + &t7_sd_emmc_b, + &t7_spicc0_sel, + &t7_spicc0_div, + &t7_spicc0, + &t7_spicc1_sel, + &t7_spicc1_div, + &t7_spicc1, + &t7_spicc2_sel, + &t7_spicc2_div, + &t7_spicc2, + &t7_spicc3_sel, + &t7_spicc3_div, + &t7_spicc3, + &t7_spicc4_sel, + &t7_spicc4_div, + &t7_spicc4, + &t7_spicc5_sel, + &t7_spicc5_div, + &t7_spicc5, + &t7_saradc_sel, + &t7_saradc_div, + &t7_saradc, + &t7_pwm_a_sel, + &t7_pwm_a_div, + &t7_pwm_a, + &t7_pwm_b_sel, + &t7_pwm_b_div, + &t7_pwm_b, + &t7_pwm_c_sel, + &t7_pwm_c_div, + &t7_pwm_c, + &t7_pwm_d_sel, + &t7_pwm_d_div, + &t7_pwm_d, + &t7_pwm_e_sel, + &t7_pwm_e_div, + &t7_pwm_e, + &t7_pwm_f_sel, + &t7_pwm_f_div, + &t7_pwm_f, + &t7_pwm_ao_a_sel, + &t7_pwm_ao_a_div, + &t7_pwm_ao_a, + &t7_pwm_ao_b_sel, + &t7_pwm_ao_b_div, + &t7_pwm_ao_b, + &t7_pwm_ao_c_sel, + &t7_pwm_ao_c_div, + &t7_pwm_ao_c, + &t7_pwm_ao_d_sel, + &t7_pwm_ao_d_div, + &t7_pwm_ao_d, + &t7_pwm_ao_e_sel, + &t7_pwm_ao_e_div, + &t7_pwm_ao_e, + &t7_pwm_ao_f_sel, + &t7_pwm_ao_f_div, + &t7_pwm_ao_f, + &t7_pwm_ao_g_sel, + &t7_pwm_ao_g_div, + &t7_pwm_ao_g, + &t7_pwm_ao_h_sel, + &t7_pwm_ao_h_div, + &t7_pwm_ao_h, + &t7_pwm_ao_h, + &t7_sys_ddr, + &t7_sys_dos, + &t7_sys_mipi_dsi_a, + &t7_sys_mipi_dsi_b, + &t7_sys_ethphy, + &t7_sys_mali, + &t7_sys_aocpu, + &t7_sys_aucpu, + &t7_sys_cec, + &t7_sys_gdc, + &t7_sys_deswarp, + &t7_sys_ampipe_nand, + &t7_sys_ampipe_eth, + &t7_sys_am2axi0, + &t7_sys_am2axi1, + &t7_sys_am2axi2, + &t7_sys_sdemmca, + &t7_sys_sdemmcb, + &t7_sys_sdemmcc, + &t7_sys_smartcard, + &t7_sys_acodec, + &t7_sys_spifc, + &t7_sys_msr_clk, + &t7_sys_ir_ctrl, + &t7_sys_audio, + &t7_sys_eth, + &t7_sys_uart_a, + &t7_sys_uart_b, + &t7_sys_uart_c, + &t7_sys_uart_d, + &t7_sys_uart_e, + &t7_sys_uart_f, + &t7_sys_aififo, + &t7_sys_spicc2, + &t7_sys_spicc3, + &t7_sys_spicc4, + &t7_sys_ts_a73, + &t7_sys_ts_a53, + &t7_sys_spicc5, + &t7_sys_g2d, + &t7_sys_spicc0, + &t7_sys_spicc1, + &t7_sys_pcie, + &t7_sys_usb, + &t7_sys_pcie_phy, + &t7_sys_i2c_ao_a, + &t7_sys_i2c_ao_b, + &t7_sys_i2c_m_a, + &t7_sys_i2c_m_b, + &t7_sys_i2c_m_c, + &t7_sys_i2c_m_d, + &t7_sys_i2c_m_e, + &t7_sys_i2c_m_f, + &t7_sys_hdmitx_apb, + &t7_sys_i2c_s_a, + &t7_sys_hdmirx_pclk, + &t7_sys_mmc_apb, + &t7_sys_mipi_isp_pclk, + &t7_sys_rsa, + &t7_sys_pclk_sys_apb, + &t7_sys_a73pclk_apb, + &t7_sys_dspa, + &t7_sys_dspb, + &t7_sys_vpu_intr, + &t7_sys_sar_adc, + &t7_sys_gic, + &t7_sys_ts_gpu, + &t7_sys_ts_nna, + &t7_sys_ts_vpu, + &t7_sys_ts_hevc, + &t7_sys_pwm_ab, + &t7_sys_pwm_cd, + &t7_sys_pwm_ef, + &t7_sys_pwm_ao_ab, + &t7_sys_pwm_ao_cd, + &t7_sys_pwm_ao_ef, + &t7_sys_pwm_ao_gh, +}; + +static const struct regmap_config t7_periphs_regmap_cfg = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, + .max_register = CLKCTRL_SPICC_CLK_CTRL2 +}; + +static struct meson_clk_hw_data t7_periphs_clks = { + .hws = t7_periphs_hw_clks, + .num = ARRAY_SIZE(t7_periphs_hw_clks), +}; + +static int amlogic_t7_periphs_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + void __iomem *base; + struct regmap *map; + int i, ret; + + base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + map = devm_regmap_init_mmio(dev, base, &t7_periphs_regmap_cfg); + if (IS_ERR(map)) + return PTR_ERR(map); + + /* Populate regmap for the regmap backed clocks */ + for (i = 0; i < ARRAY_SIZE(t7_periphs_regmaps); i++) + t7_periphs_regmaps[i]->map = map; + + for (i = 0; i < t7_periphs_clks.num; i++) { + ret = devm_clk_hw_register(dev, t7_periphs_clks.hws[i]); + if (ret) + return ret; + } + + return devm_of_clk_add_hw_provider(dev, meson_clk_hw_get, &t7_periphs_clks); +} + +static const struct of_device_id t7_periphs_clkc_match_table[] = { + { .compatible = "amlogic,t7-peripherals-clkc", }, + {} +}; +MODULE_DEVICE_TABLE(of, t7_periphs_clkc_match_table); + +static struct platform_driver t7_periphs_clkc_driver = { + .probe = amlogic_t7_periphs_probe, + .driver = { + .name = "t7-peripherals-clkc", + .of_match_table = t7_periphs_clkc_match_table, + }, +}; + +MODULE_DESCRIPTION("Amlogic T7 Peripherals Clock Controller driver"); +module_platform_driver(t7_periphs_clkc_driver); +MODULE_AUTHOR("Jian Hu <jian.hu@amlogic.com>"); +MODULE_LICENSE("GPL"); +MODULE_IMPORT_NS("CLK_MESON"); -- 2.47.1 ^ permalink raw reply related [flat|nested] 19+ messages in thread
* Re: [PATCH v3 6/6] clk: meson: t7: add t7 clock peripherals controller driver 2025-05-09 7:48 ` [PATCH v3 6/6] clk: meson: t7: add t7 clock peripherals controller driver Jian Hu @ 2025-05-14 8:00 ` Jerome Brunet 2025-06-13 9:39 ` Jian Hu 0 siblings, 1 reply; 19+ messages in thread From: Jerome Brunet @ 2025-05-14 8:00 UTC (permalink / raw) To: Jian Hu Cc: Xianwei Zhao, Chuan Liu, Neil Armstrong, Kevin Hilman, Stephen Boyd, Michael Turquette, Dmitry Rokosov, robh+dt, Rob Herring, devicetree, linux-clk, linux-amlogic, linux-kernel, linux-arm-kernel On Fri 09 May 2025 at 07:48, Jian Hu <jian.hu@amlogic.com> wrote: > Add Peripheral clock controller driver for the Amlogic T7 SoC family. > > Signed-off-by: Jian Hu <jian.hu@amlogic.com> > --- > drivers/clk/meson/Kconfig | 13 + > drivers/clk/meson/Makefile | 1 + > drivers/clk/meson/t7-peripherals.c | 2359 ++++++++++++++++++++++++++++ > 3 files changed, 2373 insertions(+) > create mode 100644 drivers/clk/meson/t7-peripherals.c > > diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig > index 8bb4f26a86ed..e32faa24c760 100644 > --- a/drivers/clk/meson/Kconfig > +++ b/drivers/clk/meson/Kconfig > @@ -216,4 +216,17 @@ config COMMON_CLK_T7_PLL > device, AKA T7. PLLs are required by most peripheral to operate > Say Y if you are a T7 based device. > > +config COMMON_CLK_T7_PERIPHERALS > + tristate "Amlogic T7 SoC peripherals clock controller support" > + depends on ARM64 > + default y > + select COMMON_CLK_MESON_REGMAP > + select COMMON_CLK_MESON_CLKC_UTILS > + select COMMON_CLK_MESON_DUALDIV > + imply COMMON_CLK_SCMI > + imply COMMON_CLK_T7_PLL > + help > + Support for the Peripherals clock controller on Amlogic A311D2 based > + device, AKA T7. Peripherals are required by most peripheral to operate > + Say Y if you are a T7 based device. > endmenu > diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile > index 646257694c34..6fef3188af30 100644 > --- a/drivers/clk/meson/Makefile > +++ b/drivers/clk/meson/Makefile > @@ -28,3 +28,4 @@ obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o meson8-ddr.o > obj-$(CONFIG_COMMON_CLK_S4_PLL) += s4-pll.o > obj-$(CONFIG_COMMON_CLK_S4_PERIPHERALS) += s4-peripherals.o > obj-$(CONFIG_COMMON_CLK_T7_PLL) += t7-pll.o > +obj-$(CONFIG_COMMON_CLK_T7_PERIPHERALS) += t7-peripherals.o > diff --git a/drivers/clk/meson/t7-peripherals.c b/drivers/clk/meson/t7-peripherals.c > new file mode 100644 > index 000000000000..9a0681183eee > --- /dev/null > +++ b/drivers/clk/meson/t7-peripherals.c > @@ -0,0 +1,2359 @@ > +// SPDX-License-Identifier: (GPL-2.0-only OR MIT) > +/* > + * Copyright (C) 2024 Amlogic, Inc. All rights reserved. > + * Author: Jian Hu <jian.hu@amlogic.com> > + */ > + > +#include <linux/clk-provider.h> > +#include <linux/platform_device.h> > +#include "clk-dualdiv.h" > +#include "clk-regmap.h" > +#include "meson-clkc-utils.h" > +#include <dt-bindings/clock/amlogic,t7-peripherals-clkc.h> > + > +#define CLKCTRL_RTC_BY_OSCIN_CTRL0 0x8 > +#define CLKCTRL_RTC_BY_OSCIN_CTRL1 0xc > +#define CLKCTRL_RTC_CTRL 0x10 > +#define CLKCTRL_SYS_CLK_CTRL0 0x40 > +#define CLKCTRL_SYS_CLK_EN0_REG0 0x44 > +#define CLKCTRL_SYS_CLK_EN0_REG1 0x48 > +#define CLKCTRL_SYS_CLK_EN0_REG2 0x4c > +#define CLKCTRL_SYS_CLK_EN0_REG3 0x50 > +#define CLKCTRL_CECA_CTRL0 0x88 > +#define CLKCTRL_CECA_CTRL1 0x8c > +#define CLKCTRL_CECB_CTRL0 0x90 > +#define CLKCTRL_CECB_CTRL1 0x94 > +#define CLKCTRL_SC_CLK_CTRL 0x98 > +#define CLKCTRL_DSPA_CLK_CTRL0 0x9c > +#define CLKCTRL_DSPB_CLK_CTRL0 0xa0 > +#define CLKCTRL_CLK12_24_CTRL 0xa8 > +#define CLKCTRL_ANAKIN_CLK_CTRL 0xac > +#define CLKCTRL_MIPI_CSI_PHY_CLK_CTRL 0x10c > +#define CLKCTRL_MIPI_ISP_CLK_CTRL 0x110 > +#define CLKCTRL_TS_CLK_CTRL 0x158 > +#define CLKCTRL_MALI_CLK_CTRL 0x15c > +#define CLKCTRL_ETH_CLK_CTRL 0x164 > +#define CLKCTRL_NAND_CLK_CTRL 0x168 > +#define CLKCTRL_SD_EMMC_CLK_CTRL 0x16c > +#define CLKCTRL_SPICC_CLK_CTRL 0x174 > +#define CLKCTRL_SAR_CLK_CTRL0 0x17c > +#define CLKCTRL_PWM_CLK_AB_CTRL 0x180 > +#define CLKCTRL_PWM_CLK_CD_CTRL 0x184 > +#define CLKCTRL_PWM_CLK_EF_CTRL 0x188 > +#define CLKCTRL_PWM_CLK_AO_AB_CTRL 0x1a0 > +#define CLKCTRL_PWM_CLK_AO_CD_CTRL 0x1a4 > +#define CLKCTRL_PWM_CLK_AO_EF_CTRL 0x1a8 > +#define CLKCTRL_PWM_CLK_AO_GH_CTRL 0x1ac > +#define CLKCTRL_SPICC_CLK_CTRL1 0x1c0 > +#define CLKCTRL_SPICC_CLK_CTRL2 0x1c4 > + > +static struct clk_regmap t7_rtc_32k_in = { > + .data = &(struct clk_regmap_gate_data){ > + .offset = CLKCTRL_RTC_BY_OSCIN_CTRL0, > + .bit_idx = 31, > + }, > + .hw.init = &(struct clk_init_data) { > + .name = "t7_rtc_32k_in", > + .ops = &clk_regmap_gate_ops, > + .parent_data = &(const struct clk_parent_data) { > + .fw_name = "xtal", > + }, > + .num_parents = 1, > + }, > +}; > + > +static const struct meson_clk_dualdiv_param t7_clk_32k_div_table[] = { > + { > + .n1 = 733, .m1 = 8, > + .n2 = 732, .m2 = 11, > + .dual = 1, > + }, > + {} > +}; > + > +static struct clk_regmap t7_rtc_32k_div = { > + .data = &(struct meson_clk_dualdiv_data){ > + .n1 = { > + .reg_off = CLKCTRL_RTC_BY_OSCIN_CTRL0, > + .shift = 0, > + .width = 12, > + }, > + .n2 = { > + .reg_off = CLKCTRL_RTC_BY_OSCIN_CTRL0, > + .shift = 12, > + .width = 12, > + }, > + .m1 = { > + .reg_off = CLKCTRL_RTC_BY_OSCIN_CTRL1, > + .shift = 0, > + .width = 12, > + }, > + .m2 = { > + .reg_off = CLKCTRL_RTC_BY_OSCIN_CTRL1, > + .shift = 12, > + .width = 12, > + }, > + .dual = { > + .reg_off = CLKCTRL_RTC_BY_OSCIN_CTRL0, > + .shift = 28, > + .width = 1, > + }, > + .table = t7_clk_32k_div_table, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "t7_rtc_32k_div", > + .ops = &meson_clk_dualdiv_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &t7_rtc_32k_in.hw > + }, > + .num_parents = 1, > + }, > +}; > + > +static struct clk_regmap t7_rtc_32k_force_sel = { > + .data = &(struct clk_regmap_mux_data) { > + .offset = CLKCTRL_RTC_BY_OSCIN_CTRL1, > + .mask = 0x1, > + .shift = 24, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "t7_rtc_32k_force_sel", > + .ops = &clk_regmap_mux_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &t7_rtc_32k_div.hw, > + &t7_rtc_32k_in.hw, > + }, > + .num_parents = 2, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap t7_rtc_32k_out = { > + .data = &(struct clk_regmap_gate_data){ > + .offset = CLKCTRL_RTC_BY_OSCIN_CTRL0, > + .bit_idx = 30, > + }, > + .hw.init = &(struct clk_init_data) { > + .name = "t7_rtc_32k_out", > + .ops = &clk_regmap_gate_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &t7_rtc_32k_force_sel.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap t7_rtc_32k_mux0_0 = { > + .data = &(struct clk_regmap_mux_data) { > + .offset = CLKCTRL_RTC_CTRL, > + .mask = 0x1, > + .shift = 0, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "t7_rtc_32k_mux0_0", > + .ops = &clk_regmap_mux_ops, > + .parent_data = (const struct clk_parent_data []) { > + { .fw_name = "xtal", }, > + { .hw = &t7_rtc_32k_out.hw }, > + }, > + .num_parents = 2, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap t7_rtc_32k_mux0_1 = { > + .data = &(struct clk_regmap_mux_data) { > + .offset = CLKCTRL_RTC_CTRL, > + .mask = 0x1, > + .shift = 0, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "t7_rtc_32k_mux0_1", > + .ops = &clk_regmap_mux_ops, > + .parent_data = (const struct clk_parent_data []) { > + { .fw_name = "pad", }, > + { .fw_name = "xtal", }, > + }, > + .num_parents = 2, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap t7_rtc = { > + .data = &(struct clk_regmap_mux_data) { > + .offset = CLKCTRL_RTC_CTRL, > + .mask = 0x1, > + .shift = 1, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "t7_rtc", > + .ops = &clk_regmap_mux_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &t7_rtc_32k_mux0_0.hw, > + &t7_rtc_32k_mux0_1.hw, > + }, > + .num_parents = 2, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap t7_ceca_32k_in = { > + .data = &(struct clk_regmap_gate_data){ > + .offset = CLKCTRL_CECA_CTRL0, > + .bit_idx = 31, > + }, > + .hw.init = &(struct clk_init_data) { > + .name = "t7_ceca_32k_in", > + .ops = &clk_regmap_gate_ops, > + .parent_data = &(const struct clk_parent_data) { > + .fw_name = "xtal", > + }, > + .num_parents = 1, > + }, > +}; > + > +static struct clk_regmap t7_ceca_32k_div = { > + .data = &(struct meson_clk_dualdiv_data){ > + .n1 = { > + .reg_off = CLKCTRL_CECA_CTRL0, > + .shift = 0, > + .width = 12, > + }, > + .n2 = { > + .reg_off = CLKCTRL_CECA_CTRL0, > + .shift = 12, > + .width = 12, > + }, > + .m1 = { > + .reg_off = CLKCTRL_CECA_CTRL1, > + .shift = 0, > + .width = 12, > + }, > + .m2 = { > + .reg_off = CLKCTRL_CECA_CTRL1, > + .shift = 12, > + .width = 12, > + }, > + .dual = { > + .reg_off = CLKCTRL_CECA_CTRL0, > + .shift = 28, > + .width = 1, > + }, > + .table = t7_clk_32k_div_table, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "t7_ceca_32k_div", > + .ops = &meson_clk_dualdiv_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &t7_ceca_32k_in.hw > + }, > + .num_parents = 1, > + }, > +}; > + > +static struct clk_regmap t7_ceca_32k_sel_pre = { > + .data = &(struct clk_regmap_mux_data) { > + .offset = CLKCTRL_CECA_CTRL1, > + .mask = 0x1, > + .shift = 24, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "t7_ceca_32k_sel_pre", > + .ops = &clk_regmap_mux_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &t7_ceca_32k_div.hw, > + &t7_ceca_32k_in.hw, > + }, > + .num_parents = 2, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap t7_ceca_32k_sel = { > + .data = &(struct clk_regmap_mux_data) { > + .offset = CLKCTRL_CECA_CTRL1, > + .mask = 0x1, > + .shift = 31, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "t7_ceca_32k_sel", > + .ops = &clk_regmap_mux_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &t7_ceca_32k_sel_pre.hw, > + &t7_rtc.hw, > + }, > + .num_parents = 2, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap t7_ceca_32k_out = { > + .data = &(struct clk_regmap_gate_data){ > + .offset = CLKCTRL_CECA_CTRL0, > + .bit_idx = 30, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "t7_ceca_32k_out", > + .ops = &clk_regmap_gate_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &t7_ceca_32k_sel.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap t7_cecb_32k_in = { > + .data = &(struct clk_regmap_gate_data){ > + .offset = CLKCTRL_CECB_CTRL0, > + .bit_idx = 31, > + }, > + .hw.init = &(struct clk_init_data) { > + .name = "t7_cecb_32k_in", > + .ops = &clk_regmap_gate_ops, > + .parent_data = &(const struct clk_parent_data) { > + .fw_name = "xtal", > + }, > + .num_parents = 1, > + }, > +}; > + > +static struct clk_regmap t7_cecb_32k_div = { > + .data = &(struct meson_clk_dualdiv_data){ > + .n1 = { > + .reg_off = CLKCTRL_CECB_CTRL0, > + .shift = 0, > + .width = 12, > + }, > + .n2 = { > + .reg_off = CLKCTRL_CECB_CTRL0, > + .shift = 12, > + .width = 12, > + }, > + .m1 = { > + .reg_off = CLKCTRL_CECB_CTRL1, > + .shift = 0, > + .width = 12, > + }, > + .m2 = { > + .reg_off = CLKCTRL_CECB_CTRL1, > + .shift = 12, > + .width = 12, > + }, > + .dual = { > + .reg_off = CLKCTRL_CECB_CTRL0, > + .shift = 28, > + .width = 1, > + }, > + .table = t7_clk_32k_div_table, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "t7_cecb_32k_div", > + .ops = &meson_clk_dualdiv_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &t7_cecb_32k_in.hw > + }, > + .num_parents = 1, > + }, > +}; > + > +static struct clk_regmap t7_cecb_32k_sel_pre = { > + .data = &(struct clk_regmap_mux_data) { > + .offset = CLKCTRL_CECB_CTRL1, > + .mask = 0x1, > + .shift = 24, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "t7_cecb_32k_sel_pre", > + .ops = &clk_regmap_mux_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &t7_cecb_32k_div.hw, > + &t7_cecb_32k_in.hw, > + }, > + .num_parents = 2, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap t7_cecb_32k_sel = { > + .data = &(struct clk_regmap_mux_data) { > + .offset = CLKCTRL_CECB_CTRL1, > + .mask = 0x1, > + .shift = 31, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "t7_cecb_32k_sel", > + .ops = &clk_regmap_mux_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &t7_cecb_32k_sel_pre.hw, > + &t7_rtc.hw, > + }, > + .num_parents = 2, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap t7_cecb_32k_out = { > + .data = &(struct clk_regmap_gate_data){ > + .offset = CLKCTRL_CECB_CTRL0, > + .bit_idx = 30, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "t7_cecb_32k_out", > + .ops = &clk_regmap_gate_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &t7_cecb_32k_sel.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +/* Smartcard Clock */ > +static const struct clk_parent_data t7_sc_parents[] = { > + { .fw_name = "fdiv4", }, > + { .fw_name = "fdiv3", }, > + { .fw_name = "fdiv5", }, > + { .fw_name = "xtal", }, > +}; > + > +static struct clk_regmap t7_sc_sel = { > + .data = &(struct clk_regmap_mux_data){ > + .offset = CLKCTRL_SC_CLK_CTRL, > + .mask = 0x3, > + .shift = 9, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "t7_sc_sel", > + .ops = &clk_regmap_mux_ops, > + .parent_data = t7_sc_parents, > + .num_parents = ARRAY_SIZE(t7_sc_parents), > + }, > +}; > + > +static struct clk_regmap t7_sc_div = { > + .data = &(struct clk_regmap_div_data){ > + .offset = CLKCTRL_SC_CLK_CTRL, > + .shift = 0, > + .width = 8, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "t7_sc_div", > + .ops = &clk_regmap_divider_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &t7_sc_sel.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap t7_sc = { > + .data = &(struct clk_regmap_gate_data){ > + .offset = CLKCTRL_SC_CLK_CTRL, > + .bit_idx = 8, > + }, > + .hw.init = &(struct clk_init_data) { > + .name = "t7_sc", > + .ops = &clk_regmap_gate_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &t7_sc_div.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +/* > + * The DSPA/B IP is clocked by two identical clocks (dspa/b_a and dspa/b_b) > + * muxed by a glitch-free switch. > + */ > +static const struct clk_parent_data t7_dsp_ab_parent_data[] = { > + { .fw_name = "xtal", }, > + { .fw_name = "fdiv2p5", }, > + { .fw_name = "fdiv3", }, > + { .fw_name = "fdiv5", }, > + { .fw_name = "hifi", }, > + { .fw_name = "fdiv4", }, > + { .fw_name = "fdiv7", }, > + { .hw = &t7_rtc.hw }, > +}; > + > +static struct clk_regmap t7_dspa_a_sel = { > + .data = &(struct clk_regmap_mux_data){ > + .offset = CLKCTRL_DSPA_CLK_CTRL0, > + .mask = 0x7, > + .shift = 10, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "t7_dspa_a_sel", > + .ops = &clk_regmap_mux_ops, > + .parent_data = t7_dsp_ab_parent_data, > + .num_parents = ARRAY_SIZE(t7_dsp_ab_parent_data), > + }, > +}; > + > +static struct clk_regmap t7_dspa_a_div = { > + .data = &(struct clk_regmap_div_data){ > + .offset = CLKCTRL_DSPA_CLK_CTRL0, > + .shift = 0, > + .width = 10, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "t7_dspa_a_div", > + .ops = &clk_regmap_divider_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &t7_dspa_a_sel.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap t7_dspa_a = { > + .data = &(struct clk_regmap_gate_data){ > + .offset = CLKCTRL_DSPA_CLK_CTRL0, > + .bit_idx = 13, > + }, > + .hw.init = &(struct clk_init_data) { > + .name = "t7_dspa_a", > + .ops = &clk_regmap_gate_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &t7_dspa_a_div.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap t7_dspa_b_sel = { > + .data = &(struct clk_regmap_mux_data){ > + .offset = CLKCTRL_DSPA_CLK_CTRL0, > + .mask = 0x7, > + .shift = 26, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "t7_dspa_b_sel", > + .ops = &clk_regmap_mux_ops, > + .parent_data = t7_dsp_ab_parent_data, > + .num_parents = ARRAY_SIZE(t7_dsp_ab_parent_data), > + }, > +}; > + > +static struct clk_regmap t7_dspa_b_div = { > + .data = &(struct clk_regmap_div_data){ > + .offset = CLKCTRL_DSPA_CLK_CTRL0, > + .shift = 16, > + .width = 10, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "t7_dspa_b_div", > + .ops = &clk_regmap_divider_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &t7_dspa_b_sel.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap t7_dspa_b = { > + .data = &(struct clk_regmap_gate_data){ > + .offset = CLKCTRL_DSPA_CLK_CTRL0, > + .bit_idx = 29, > + }, > + .hw.init = &(struct clk_init_data) { > + .name = "t7_dspa_b", > + .ops = &clk_regmap_gate_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &t7_dspa_b_div.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap t7_dspa = { > + .data = &(struct clk_regmap_mux_data){ > + .offset = CLKCTRL_DSPA_CLK_CTRL0, > + .mask = 0x1, > + .shift = 15, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "t7_dspa", > + .ops = &clk_regmap_mux_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &t7_dspa_a.hw, > + &t7_dspa_b.hw, > + }, > + .num_parents = 2, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap t7_dspb_a_sel = { > + .data = &(struct clk_regmap_mux_data){ > + .offset = CLKCTRL_DSPB_CLK_CTRL0, > + .mask = 0x7, > + .shift = 10, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "t7_dspb_a_sel", > + .ops = &clk_regmap_mux_ops, > + .parent_data = t7_dsp_ab_parent_data, > + .num_parents = ARRAY_SIZE(t7_dsp_ab_parent_data), > + }, > +}; > + > +static struct clk_regmap t7_dspb_a_div = { > + .data = &(struct clk_regmap_div_data){ > + .offset = CLKCTRL_DSPB_CLK_CTRL0, > + .shift = 0, > + .width = 10, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "t7_dspb_a_div", > + .ops = &clk_regmap_divider_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &t7_dspb_a_sel.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap t7_dspb_a = { > + .data = &(struct clk_regmap_gate_data){ > + .offset = CLKCTRL_DSPB_CLK_CTRL0, > + .bit_idx = 13, > + }, > + .hw.init = &(struct clk_init_data) { > + .name = "t7_dspb_a", > + .ops = &clk_regmap_gate_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &t7_dspb_a_div.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap t7_dspb_b_sel = { > + .data = &(struct clk_regmap_mux_data){ > + .offset = CLKCTRL_DSPB_CLK_CTRL0, > + .mask = 0x7, > + .shift = 26, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "t7_dspb_b_sel", > + .ops = &clk_regmap_mux_ops, > + .parent_data = t7_dsp_ab_parent_data, > + .num_parents = ARRAY_SIZE(t7_dsp_ab_parent_data), > + }, > +}; > + > +static struct clk_regmap t7_dspb_b_div = { > + .data = &(struct clk_regmap_div_data){ > + .offset = CLKCTRL_DSPB_CLK_CTRL0, > + .shift = 16, > + .width = 10, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "t7_dspb_b_div", > + .ops = &clk_regmap_divider_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &t7_dspb_b_sel.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap t7_dspb_b = { > + .data = &(struct clk_regmap_gate_data){ > + .offset = CLKCTRL_DSPB_CLK_CTRL0, > + .bit_idx = 29, > + }, > + .hw.init = &(struct clk_init_data) { > + .name = "t7_dspb_b", > + .ops = &clk_regmap_gate_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &t7_dspb_b_div.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap t7_dspb = { > + .data = &(struct clk_regmap_mux_data){ > + .offset = CLKCTRL_DSPB_CLK_CTRL0, > + .mask = 0x1, > + .shift = 15, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "t7_dspb", > + .ops = &clk_regmap_mux_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &t7_dspb_a.hw, > + &t7_dspb_b.hw, > + }, > + .num_parents = 2, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap t7_clk_24m = { > + .data = &(struct clk_regmap_gate_data){ > + .offset = CLKCTRL_CLK12_24_CTRL, > + .bit_idx = 11, > + }, > + .hw.init = &(struct clk_init_data) { > + .name = "t7_24m", > + .ops = &clk_regmap_gate_ops, > + .parent_data = &(const struct clk_parent_data) { > + .fw_name = "xtal", > + }, > + .num_parents = 1, > + }, > +}; > + > +static struct clk_fixed_factor t7_clk_24m_div2 = { > + .mult = 1, > + .div = 2, > + .hw.init = &(struct clk_init_data){ > + .name = "t7_24m_div2", > + .ops = &clk_fixed_factor_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &t7_clk_24m.hw > + }, > + .num_parents = 1, > + }, > +}; > + > +static struct clk_regmap t7_clk_12m = { > + .data = &(struct clk_regmap_gate_data){ > + .offset = CLKCTRL_CLK12_24_CTRL, > + .bit_idx = 10, > + }, > + .hw.init = &(struct clk_init_data) { > + .name = "t7_12m", > + .ops = &clk_regmap_gate_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &t7_clk_24m_div2.hw > + }, > + .num_parents = 1, > + }, > +}; > + > +static struct clk_regmap t7_fdiv2_divn_pre = { > + .data = &(struct clk_regmap_div_data){ > + .offset = CLKCTRL_CLK12_24_CTRL, > + .shift = 0, > + .width = 8, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "t7_fdiv2_divn_pre", > + .ops = &clk_regmap_divider_ops, > + .parent_data = &(const struct clk_parent_data) { > + .fw_name = "fdiv2", > + }, > + .num_parents = 1, > + }, > +}; > + > +static struct clk_regmap t7_fdiv2_divn = { > + .data = &(struct clk_regmap_gate_data){ > + .offset = CLKCTRL_CLK12_24_CTRL, > + .bit_idx = 12, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "t7_fdiv2_divn", > + .ops = &clk_regmap_gate_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &t7_fdiv2_divn_pre.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +/* > + * The NNA IP is clocked by two identical clocks (anakin_0 and anakin_1) > + * muxed by a glitch-free switch. > + */ > +static const struct clk_parent_data t7_anakin_parent_data[] = { > + { .fw_name = "fdiv4", }, > + { .fw_name = "fdiv3", }, > + { .fw_name = "fdiv5", }, > + { .fw_name = "fdiv2", }, > + { .fw_name = "vid_pll0", }, > + { .fw_name = "mpll1", }, > + { .fw_name = "mpll2", }, > + { .fw_name = "fdiv2p5", }, > +}; > + > +static struct clk_regmap t7_anakin_0_sel = { > + .data = &(struct clk_regmap_mux_data){ > + .offset = CLKCTRL_ANAKIN_CLK_CTRL, > + .mask = 0x7, > + .shift = 9, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "t7_anakin_0_sel", > + .ops = &clk_regmap_mux_ops, > + .parent_data = t7_anakin_parent_data, > + .num_parents = ARRAY_SIZE(t7_anakin_parent_data), > + }, > +}; > + > +static struct clk_regmap t7_anakin_0_div = { > + .data = &(struct clk_regmap_div_data){ > + .offset = CLKCTRL_ANAKIN_CLK_CTRL, > + .shift = 0, > + .width = 7, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "t7_anakin_0_div", > + .ops = &clk_regmap_divider_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &t7_anakin_0_sel.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap t7_anakin_0 = { > + .data = &(struct clk_regmap_gate_data){ > + .offset = CLKCTRL_ANAKIN_CLK_CTRL, > + .bit_idx = 8, > + }, > + .hw.init = &(struct clk_init_data) { > + .name = "t7_anakin_0", > + .ops = &clk_regmap_gate_ops, > + .parent_hws = (const struct clk_hw *[]) { &t7_anakin_0_div.hw }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap t7_anakin_1_sel = { > + .data = &(struct clk_regmap_mux_data){ > + .offset = CLKCTRL_ANAKIN_CLK_CTRL, > + .mask = 0x7, > + .shift = 25, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "t7_anakin_1_sel", > + .ops = &clk_regmap_mux_ops, > + .parent_data = t7_anakin_parent_data, > + .num_parents = ARRAY_SIZE(t7_anakin_parent_data), > + }, > +}; > + > +static struct clk_regmap t7_anakin_1_div = { > + .data = &(struct clk_regmap_div_data){ > + .offset = CLKCTRL_ANAKIN_CLK_CTRL, > + .shift = 16, > + .width = 7, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "t7_anakin_1_div", > + .ops = &clk_regmap_divider_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &t7_anakin_1_sel.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap t7_anakin_1 = { > + .data = &(struct clk_regmap_gate_data){ > + .offset = CLKCTRL_ANAKIN_CLK_CTRL, > + .bit_idx = 24, > + }, > + .hw.init = &(struct clk_init_data) { > + .name = "t7_anakin_1", > + .ops = &clk_regmap_gate_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &t7_anakin_1_div.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap t7_anakin = { > + .data = &(struct clk_regmap_mux_data){ > + .offset = CLKCTRL_ANAKIN_CLK_CTRL, > + .mask = 1, > + .shift = 31, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "t7_anakin_sel", > + .ops = &clk_regmap_mux_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &t7_anakin_0.hw, > + &t7_anakin_1.hw > + }, > + .num_parents = 2, > + .flags = CLK_SET_RATE_PARENT > + }, > +}; > + > +static struct clk_regmap t7_anakin_clk = { > + .data = &(struct clk_regmap_gate_data){ > + .offset = CLKCTRL_ANAKIN_CLK_CTRL, > + .bit_idx = 30, > + }, > + .hw.init = &(struct clk_init_data) { > + .name = "t7_anakin_clk", > + .ops = &clk_regmap_gate_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &t7_anakin.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT > + }, > +}; > + > +static const struct clk_parent_data t7_mipi_csi_parents[] = { > + { .fw_name = "xtal", }, > + { .fw_name = "gp1", }, > + { .fw_name = "mpll1", }, > + { .fw_name = "mpll2", }, > + { .fw_name = "fdiv3", }, > + { .fw_name = "fdiv4", }, > + { .fw_name = "fdiv5", }, > + { .fw_name = "fdiv7", }, > +}; > + > +static struct clk_regmap t7_mipi_csi_phy0_sel = { > + .data = &(struct clk_regmap_mux_data){ > + .offset = CLKCTRL_MIPI_CSI_PHY_CLK_CTRL, > + .mask = 0x7, > + .shift = 9, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "t7_mipi_csi_phy0_sel", > + .ops = &clk_regmap_mux_ops, > + .parent_data = t7_mipi_csi_parents, > + .num_parents = ARRAY_SIZE(t7_mipi_csi_parents), > + }, > +}; > + > +static struct clk_regmap t7_mipi_csi_phy0_div = { > + .data = &(struct clk_regmap_div_data){ > + .offset = CLKCTRL_MIPI_CSI_PHY_CLK_CTRL, > + .shift = 0, > + .width = 7, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "t7_mipi_csi_phy0_div", > + .ops = &clk_regmap_divider_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &t7_mipi_csi_phy0_sel.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap t7_mipi_csi_phy0 = { > + .data = &(struct clk_regmap_gate_data){ > + .offset = CLKCTRL_MIPI_CSI_PHY_CLK_CTRL, > + .bit_idx = 8, > + }, > + .hw.init = &(struct clk_init_data) { > + .name = "t7_mipi_csi_phy0", > + .ops = &clk_regmap_gate_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &t7_mipi_csi_phy0_div.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap t7_mipi_csi_phy1_sel = { > + .data = &(struct clk_regmap_mux_data){ > + .offset = CLKCTRL_MIPI_CSI_PHY_CLK_CTRL, > + .mask = 0x7, > + .shift = 25, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "t7_mipi_csi_phy1_sel", > + .ops = &clk_regmap_mux_ops, > + .parent_data = t7_mipi_csi_parents, > + .num_parents = ARRAY_SIZE(t7_mipi_csi_parents), > + }, > +}; > + > +static struct clk_regmap t7_mipi_csi_phy1_div = { > + .data = &(struct clk_regmap_div_data){ > + .offset = CLKCTRL_MIPI_CSI_PHY_CLK_CTRL, > + .shift = 16, > + .width = 7, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "t7_mipi_csi_phy1_div", > + .ops = &clk_regmap_divider_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &t7_mipi_csi_phy1_sel.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap t7_mipi_csi_phy1 = { > + .data = &(struct clk_regmap_gate_data){ > + .offset = CLKCTRL_MIPI_CSI_PHY_CLK_CTRL, > + .bit_idx = 24, > + }, > + .hw.init = &(struct clk_init_data) { > + .name = "t7_mipi_csi_phy1", > + .ops = &clk_regmap_gate_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &t7_mipi_csi_phy1_div.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap t7_mipi_csi_phy = { > + .data = &(struct clk_regmap_mux_data){ > + .offset = CLKCTRL_MIPI_CSI_PHY_CLK_CTRL, > + .mask = 0x1, > + .shift = 31, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "t7_mipi_csi_phy", > + .ops = &clk_regmap_mux_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &t7_mipi_csi_phy0.hw, > + &t7_mipi_csi_phy1.hw > + }, > + .num_parents = 2, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static const struct clk_parent_data t7_mipi_isp_parents[] = { > + { .fw_name = "xtal", }, > + { .fw_name = "fdiv4", }, > + { .fw_name = "fdiv3", }, > + { .fw_name = "fdiv5", }, > + { .fw_name = "fdiv7", }, > + { .fw_name = "mpll2", }, > + { .fw_name = "mpll3", }, > + { .fw_name = "gp1", }, > +}; > + > +static struct clk_regmap t7_mipi_isp_sel = { > + .data = &(struct clk_regmap_mux_data){ > + .offset = CLKCTRL_MIPI_ISP_CLK_CTRL, > + .mask = 0x7, > + .shift = 9, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "t7_mipi_isp_sel", > + .ops = &clk_regmap_mux_ops, > + .parent_data = t7_mipi_isp_parents, > + .num_parents = ARRAY_SIZE(t7_mipi_isp_parents), > + }, > +}; > + > +static struct clk_regmap t7_mipi_isp_div = { > + .data = &(struct clk_regmap_div_data){ > + .offset = CLKCTRL_MIPI_ISP_CLK_CTRL, > + .shift = 0, > + .width = 7, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "t7_mipi_isp_div", > + .ops = &clk_regmap_divider_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &t7_mipi_isp_sel.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap t7_mipi_isp = { > + .data = &(struct clk_regmap_gate_data){ > + .offset = CLKCTRL_MIPI_ISP_CLK_CTRL, > + .bit_idx = 8, > + }, > + .hw.init = &(struct clk_init_data) { > + .name = "t7_mipi_isp", > + .ops = &clk_regmap_gate_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &t7_mipi_isp_div.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap t7_ts_div = { > + .data = &(struct clk_regmap_div_data){ > + .offset = CLKCTRL_TS_CLK_CTRL, > + .shift = 0, > + .width = 8, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "t7_ts_div", > + .ops = &clk_regmap_divider_ops, > + .parent_data = &(const struct clk_parent_data) { > + .fw_name = "xtal", > + }, > + .num_parents = 1, > + }, > +}; > + > +static struct clk_regmap t7_ts = { > + .data = &(struct clk_regmap_gate_data){ > + .offset = CLKCTRL_TS_CLK_CTRL, > + .bit_idx = 8, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "t7_ts", > + .ops = &clk_regmap_gate_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &t7_ts_div.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +/* > + * The MALI IP is clocked by two identical clocks (mali_0 and mali_1) > + * muxed by a glitch-free switch. > + */ > +static const struct clk_parent_data t7_mali_parents[] = { > + { .fw_name = "xtal", }, > + { .fw_name = "gp0", }, > + { .fw_name = "gp1", }, > + { .fw_name = "fdiv2p5", }, > + { .fw_name = "fdiv3", }, > + { .fw_name = "fdiv4", }, > + { .fw_name = "fdiv5", }, > + { .fw_name = "fdiv7", }, > +}; > + > +static struct clk_regmap t7_mali_0_sel = { > + .data = &(struct clk_regmap_mux_data){ > + .offset = CLKCTRL_MALI_CLK_CTRL, > + .mask = 0x7, > + .shift = 9, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "t7_mali_0_sel", > + .ops = &clk_regmap_mux_ops, > + .parent_data = t7_mali_parents, > + .num_parents = ARRAY_SIZE(t7_mali_parents), > + }, > +}; > + > +static struct clk_regmap t7_mali_0_div = { > + .data = &(struct clk_regmap_div_data){ > + .offset = CLKCTRL_MALI_CLK_CTRL, > + .shift = 0, > + .width = 7, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "t7_mali_0_div", > + .ops = &clk_regmap_divider_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &t7_mali_0_sel.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap t7_mali_0 = { > + .data = &(struct clk_regmap_gate_data){ > + .offset = CLKCTRL_MALI_CLK_CTRL, > + .bit_idx = 8, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "t7_mali_0", > + .ops = &clk_regmap_gate_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &t7_mali_0_div.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap t7_mali_1_sel = { > + .data = &(struct clk_regmap_mux_data){ > + .offset = CLKCTRL_MALI_CLK_CTRL, > + .mask = 0x7, > + .shift = 25, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "t7_mali_1_sel", > + .ops = &clk_regmap_mux_ops, > + .parent_data = t7_mali_parents, > + .num_parents = ARRAY_SIZE(t7_mali_parents), > + }, > +}; > + > +static struct clk_regmap t7_mali_1_div = { > + .data = &(struct clk_regmap_div_data){ > + .offset = CLKCTRL_MALI_CLK_CTRL, > + .shift = 16, > + .width = 7, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "t7_mali_1_div", > + .ops = &clk_regmap_divider_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &t7_mali_1_sel.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap t7_mali_1 = { > + .data = &(struct clk_regmap_gate_data){ > + .offset = CLKCTRL_MALI_CLK_CTRL, > + .bit_idx = 24, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "t7_mali_1", > + .ops = &clk_regmap_gate_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &t7_mali_1_div.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap t7_mali = { > + .data = &(struct clk_regmap_mux_data){ > + .offset = CLKCTRL_MALI_CLK_CTRL, > + .mask = 1, > + .shift = 31, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "t7_mali", > + .ops = &clk_regmap_mux_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &t7_mali_0.hw, > + &t7_mali_1.hw, > + }, > + .num_parents = 2, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static u32 t7_eth_rmii_table[] = { 0, 7 }; > + > +static const struct clk_parent_data t7_eth_rmii_parents[] = { > + { .fw_name = "fdiv2", }, > + { .fw_name = "rmii_pad", }, Are you sure about that ? check the bindings > +}; > + > +static struct clk_regmap t7_eth_rmii_sel = { > + .data = &(struct clk_regmap_mux_data) { > + .offset = CLKCTRL_ETH_CLK_CTRL, > + .mask = 0x3, > + .shift = 9, > + .table = t7_eth_rmii_table > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "t7_eth_rmii_sel", > + .ops = &clk_regmap_mux_ops, > + .parent_data = t7_eth_rmii_parents, > + .num_parents = ARRAY_SIZE(t7_eth_rmii_parents), > + }, > +}; > + > +static struct clk_regmap t7_eth_rmii_div = { > + .data = &(struct clk_regmap_div_data) { > + .offset = CLKCTRL_ETH_CLK_CTRL, > + .shift = 0, > + .width = 7, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "t7_eth_rmii_div", > + .ops = &clk_regmap_divider_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &t7_eth_rmii_sel.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap t7_eth_rmii = { > + .data = &(struct clk_regmap_gate_data) { > + .offset = CLKCTRL_ETH_CLK_CTRL, > + .bit_idx = 8, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "t7_eth_rmii", > + .ops = &clk_regmap_gate_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &t7_eth_rmii_div.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_fixed_factor t7_fdiv2_div8 = { > + .mult = 1, > + .div = 8, > + .hw.init = &(struct clk_init_data){ > + .name = "t7_fdiv2_div8", > + .ops = &clk_fixed_factor_ops, > + .parent_data = &(const struct clk_parent_data) { > + .fw_name = "fdiv2", > + }, > + .num_parents = 1, > + }, > +}; > + > +static struct clk_regmap t7_eth_125m = { > + .data = &(struct clk_regmap_gate_data) { > + .offset = CLKCTRL_ETH_CLK_CTRL, > + .bit_idx = 7, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "t7_eth_125m", > + .ops = &clk_regmap_gate_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &t7_fdiv2_div8.hw > + }, > + .num_parents = 1, > + }, > +}; > + > +static const struct clk_parent_data t7_sd_emmc_parents[] = { > + { .fw_name = "xtal", }, > + { .fw_name = "fdiv2", }, > + { .fw_name = "fdiv3", }, > + { .fw_name = "hifi", }, > + { .fw_name = "fdiv2p5", }, > + { .fw_name = "mpll2", }, > + { .fw_name = "mpll3", }, > + { .fw_name = "gp0", }, > +}; > + > +static struct clk_regmap t7_sd_emmc_c_sel = { > + .data = &(struct clk_regmap_mux_data){ > + .offset = CLKCTRL_NAND_CLK_CTRL, > + .mask = 0x7, > + .shift = 9, > + }, > + .hw.init = &(struct clk_init_data) { > + .name = "t7_sd_emmc_c_sel", > + .ops = &clk_regmap_mux_ops, > + .parent_data = t7_sd_emmc_parents, > + .num_parents = ARRAY_SIZE(t7_sd_emmc_parents), > + }, > +}; > + > +static struct clk_regmap t7_sd_emmc_c_div = { > + .data = &(struct clk_regmap_div_data){ > + .offset = CLKCTRL_NAND_CLK_CTRL, > + .shift = 0, > + .width = 7, > + }, > + .hw.init = &(struct clk_init_data) { > + .name = "t7_sd_emmc_c_div", > + .ops = &clk_regmap_divider_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &t7_sd_emmc_c_sel.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap t7_sd_emmc_c = { > + .data = &(struct clk_regmap_gate_data){ > + .offset = CLKCTRL_NAND_CLK_CTRL, > + .bit_idx = 7, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "t7_sd_emmc_c", > + .ops = &clk_regmap_gate_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &t7_sd_emmc_c_div.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap t7_sd_emmc_a_sel = { > + .data = &(struct clk_regmap_mux_data){ > + .offset = CLKCTRL_SD_EMMC_CLK_CTRL, > + .mask = 0x7, > + .shift = 9, > + }, > + .hw.init = &(struct clk_init_data) { > + .name = "t7_sd_emmc_a_sel", > + .ops = &clk_regmap_mux_ops, > + .parent_data = t7_sd_emmc_parents, > + .num_parents = ARRAY_SIZE(t7_sd_emmc_parents), > + }, > +}; > + > +static struct clk_regmap t7_sd_emmc_a_div = { > + .data = &(struct clk_regmap_div_data){ > + .offset = CLKCTRL_SD_EMMC_CLK_CTRL, > + .shift = 0, > + .width = 7, > + }, > + .hw.init = &(struct clk_init_data) { > + .name = "t7_sd_emmc_a_div", > + .ops = &clk_regmap_divider_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &t7_sd_emmc_a_sel.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap t7_sd_emmc_a = { > + .data = &(struct clk_regmap_gate_data){ > + .offset = CLKCTRL_SD_EMMC_CLK_CTRL, > + .bit_idx = 7, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "t7_sd_emmc_a", > + .ops = &clk_regmap_gate_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &t7_sd_emmc_a_div.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap t7_sd_emmc_b_sel = { > + .data = &(struct clk_regmap_mux_data){ > + .offset = CLKCTRL_SD_EMMC_CLK_CTRL, > + .mask = 0x7, > + .shift = 25, > + }, > + .hw.init = &(struct clk_init_data) { > + .name = "t7_sd_emmc_b_sel", > + .ops = &clk_regmap_mux_ops, > + .parent_data = t7_sd_emmc_parents, > + .num_parents = ARRAY_SIZE(t7_sd_emmc_parents), > + }, > +}; > + > +static struct clk_regmap t7_sd_emmc_b_div = { > + .data = &(struct clk_regmap_div_data){ > + .offset = CLKCTRL_SD_EMMC_CLK_CTRL, > + .shift = 16, > + .width = 7, > + }, > + .hw.init = &(struct clk_init_data) { > + .name = "t7_sd_emmc_b_div", > + .ops = &clk_regmap_divider_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &t7_sd_emmc_b_sel.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap t7_sd_emmc_b = { > + .data = &(struct clk_regmap_gate_data){ > + .offset = CLKCTRL_SD_EMMC_CLK_CTRL, > + .bit_idx = 23, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "t7_sd_emmc_b", > + .ops = &clk_regmap_gate_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &t7_sd_emmc_b_div.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +#define SPI_PWM_CLK_MUX(_name, _reg, _mask, _shift, _parent_data) { \ > + .data = &(struct clk_regmap_mux_data) { \ > + .offset = _reg, \ > + .mask = _mask, \ > + .shift = _shift, \ > + }, \ > + .hw.init = &(struct clk_init_data) { \ > + .name = #_name "_sel", \ > + .ops = &clk_regmap_mux_ops, \ > + .parent_data = _parent_data, \ > + .num_parents = ARRAY_SIZE(_parent_data), \ > + }, \ > +} > + > +#define SPI_PWM_CLK_DIV(_name, _reg, _shift, _width, _parent) { \ > + .data = &(struct clk_regmap_div_data) { \ > + .offset = _reg, \ > + .shift = _shift, \ > + .width = _width, \ > + }, \ > + .hw.init = &(struct clk_init_data) { \ > + .name = #_name "_div", \ > + .ops = &clk_regmap_divider_ops, \ > + .parent_hws = (const struct clk_hw *[]) { \ > + &_parent.hw \ > + }, \ > + .num_parents = 1, \ > + .flags = CLK_SET_RATE_PARENT, \ > + }, \ > +} > + > +#define SPI_PWM_CLK_GATE(_name, _reg, _bit, _parent) { \ > + .data = &(struct clk_regmap_gate_data) { \ > + .offset = _reg, \ > + .bit_idx = _bit, \ > + }, \ > + .hw.init = &(struct clk_init_data) { \ > + .name = #_name, \ > + .ops = &clk_regmap_gate_ops, \ > + .parent_hws = (const struct clk_hw *[]) { \ > + &_parent.hw \ > + }, \ > + .num_parents = 1, \ > + .flags = CLK_SET_RATE_PARENT, \ > + }, \ > +} Again that something that has been repeated for way too long. You'll wait for the clean-up to be done. If you want to help, you can review and test the patch being sent. It may speed things up. > + > +static const struct clk_parent_data t7_spicc_parents[] = { > + { .fw_name = "xtal", }, > + { .fw_name = "sys", }, > + { .fw_name = "fdiv4", }, > + { .fw_name = "fdiv3", }, > + { .fw_name = "fdiv2", }, > + { .fw_name = "fdiv5", }, > + { .fw_name = "fdiv7", }, > + { .fw_name = "gp1", }, > +}; > + > +static struct clk_regmap t7_spicc0_sel = > + SPI_PWM_CLK_MUX(t7_spicc0, CLKCTRL_SPICC_CLK_CTRL, 0x7, 7, t7_spicc_parents); > +static struct clk_regmap t7_spicc0_div = > + SPI_PWM_CLK_DIV(t7_spicc0, CLKCTRL_SPICC_CLK_CTRL, 0, 6, t7_spicc0_sel); > +static struct clk_regmap t7_spicc0 = > + SPI_PWM_CLK_GATE(t7_spicc0, CLKCTRL_SPICC_CLK_CTRL, 6, t7_spicc0_div); > + > +static struct clk_regmap t7_spicc1_sel = > + SPI_PWM_CLK_MUX(t7_spicc1, CLKCTRL_SPICC_CLK_CTRL, 0x7, 23, t7_spicc_parents); > +static struct clk_regmap t7_spicc1_div = > + SPI_PWM_CLK_DIV(t7_spicc1, CLKCTRL_SPICC_CLK_CTRL, 16, 6, t7_spicc1_sel); > +static struct clk_regmap t7_spicc1 = > + SPI_PWM_CLK_GATE(t7_spicc1, CLKCTRL_SPICC_CLK_CTRL, 22, t7_spicc1_div); > + > +static struct clk_regmap t7_spicc2_sel = > + SPI_PWM_CLK_MUX(t7_spicc2, CLKCTRL_SPICC_CLK_CTRL1, 0x7, 7, t7_spicc_parents); > +static struct clk_regmap t7_spicc2_div = > + SPI_PWM_CLK_DIV(t7_spicc2, CLKCTRL_SPICC_CLK_CTRL1, 0, 6, t7_spicc2_sel); > +static struct clk_regmap t7_spicc2 = > + SPI_PWM_CLK_GATE(t7_spicc2, CLKCTRL_SPICC_CLK_CTRL1, 6, t7_spicc2_div); > + > +static struct clk_regmap t7_spicc3_sel = > + SPI_PWM_CLK_MUX(t7_spicc3, CLKCTRL_SPICC_CLK_CTRL1, 0x7, 23, t7_spicc_parents); > +static struct clk_regmap t7_spicc3_div = > + SPI_PWM_CLK_DIV(t7_spicc3, CLKCTRL_SPICC_CLK_CTRL1, 16, 6, t7_spicc3_sel); > +static struct clk_regmap t7_spicc3 = > + SPI_PWM_CLK_GATE(t7_spicc3, CLKCTRL_SPICC_CLK_CTRL1, 22, t7_spicc3_div); > + > +static struct clk_regmap t7_spicc4_sel = > + SPI_PWM_CLK_MUX(t7_spicc4, CLKCTRL_SPICC_CLK_CTRL2, 0x7, 7, t7_spicc_parents); > +static struct clk_regmap t7_spicc4_div = > + SPI_PWM_CLK_DIV(t7_spicc4, CLKCTRL_SPICC_CLK_CTRL2, 0, 6, t7_spicc4_sel); > +static struct clk_regmap t7_spicc4 = > + SPI_PWM_CLK_GATE(t7_spicc4, CLKCTRL_SPICC_CLK_CTRL2, 6, t7_spicc4_div); > + > +static struct clk_regmap t7_spicc5_sel = > + SPI_PWM_CLK_MUX(t7_spicc5, CLKCTRL_SPICC_CLK_CTRL2, 0x7, 23, t7_spicc_parents); > +static struct clk_regmap t7_spicc5_div = > + SPI_PWM_CLK_DIV(t7_spicc5, CLKCTRL_SPICC_CLK_CTRL2, 16, 6, t7_spicc5_sel); > +static struct clk_regmap t7_spicc5 = > + SPI_PWM_CLK_GATE(t7_spicc5, CLKCTRL_SPICC_CLK_CTRL2, 22, t7_spicc5_div); > + > +static struct clk_regmap t7_saradc_sel = { > + .data = &(struct clk_regmap_mux_data) { > + .offset = CLKCTRL_SAR_CLK_CTRL0, > + .mask = 0x1, > + .shift = 9, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "t7_saradc_sel", > + .ops = &clk_regmap_mux_ops, > + .parent_data = (const struct clk_parent_data []) { > + { .fw_name = "xtal", }, > + { .fw_name = "sys", }, > + }, > + .num_parents = 2, > + }, > +}; > + > +static struct clk_regmap t7_saradc_div = { > + .data = &(struct clk_regmap_div_data) { > + .offset = CLKCTRL_SAR_CLK_CTRL0, > + .shift = 0, > + .width = 8, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "t7_saradc_div", > + .ops = &clk_regmap_divider_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &t7_saradc_sel.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap t7_saradc = { > + .data = &(struct clk_regmap_gate_data) { > + .offset = CLKCTRL_SAR_CLK_CTRL0, > + .bit_idx = 8, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "t7_saradc", > + .ops = &clk_regmap_gate_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &t7_saradc_div.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static const struct clk_parent_data t7_pwm_parents[] = { > + { .fw_name = "xtal", }, > + { .fw_name = "vid_pll0", }, > + { .fw_name = "fdiv4", }, > + { .fw_name = "fdiv3", }, > +}; > + > +static struct clk_regmap t7_pwm_a_sel = > + SPI_PWM_CLK_MUX(t7_pwm, CLKCTRL_PWM_CLK_AB_CTRL, 0x3, 9, t7_pwm_parents); > +static struct clk_regmap t7_pwm_a_div = > + SPI_PWM_CLK_DIV(t7_pwm_a, CLKCTRL_PWM_CLK_AB_CTRL, 0, 8, t7_pwm_a_sel); > +static struct clk_regmap t7_pwm_a = > + SPI_PWM_CLK_GATE(t7_pwm_a, CLKCTRL_PWM_CLK_AB_CTRL, 8, t7_pwm_a_div); > + > +static struct clk_regmap t7_pwm_b_sel = > + SPI_PWM_CLK_MUX(t7_pwm_b, CLKCTRL_PWM_CLK_AB_CTRL, 0x3, 25, t7_pwm_parents); > +static struct clk_regmap t7_pwm_b_div = > + SPI_PWM_CLK_DIV(t7_pwm_b, CLKCTRL_PWM_CLK_AB_CTRL, 16, 8, t7_pwm_b_sel); > +static struct clk_regmap t7_pwm_b = > + SPI_PWM_CLK_GATE(t7_pwm_b, CLKCTRL_PWM_CLK_AB_CTRL, 24, t7_pwm_b_div); > + > +static struct clk_regmap t7_pwm_c_sel = > + SPI_PWM_CLK_MUX(t7_pwm_c, CLKCTRL_PWM_CLK_CD_CTRL, 0x3, 9, t7_pwm_parents); > +static struct clk_regmap t7_pwm_c_div = > + SPI_PWM_CLK_DIV(t7_pwm_c, CLKCTRL_PWM_CLK_CD_CTRL, 0, 8, t7_pwm_c_sel); > +static struct clk_regmap t7_pwm_c = > + SPI_PWM_CLK_GATE(t7_pwm_c, CLKCTRL_PWM_CLK_CD_CTRL, 8, t7_pwm_c_div); > + > +static struct clk_regmap t7_pwm_d_sel = > + SPI_PWM_CLK_MUX(t7_pwm_d, CLKCTRL_PWM_CLK_CD_CTRL, 0x3, 25, t7_pwm_parents); > +static struct clk_regmap t7_pwm_d_div = > + SPI_PWM_CLK_DIV(t7_pwm_d, CLKCTRL_PWM_CLK_CD_CTRL, 16, 8, t7_pwm_d_sel); > +static struct clk_regmap t7_pwm_d = > + SPI_PWM_CLK_GATE(t7_pwm_d, CLKCTRL_PWM_CLK_CD_CTRL, 24, t7_pwm_d_div); > + > +static struct clk_regmap t7_pwm_e_sel = > + SPI_PWM_CLK_MUX(t7_pwm_e, CLKCTRL_PWM_CLK_EF_CTRL, 0x3, 9, t7_pwm_parents); > +static struct clk_regmap t7_pwm_e_div = > + SPI_PWM_CLK_DIV(t7_pwm_e, CLKCTRL_PWM_CLK_EF_CTRL, 0, 8, t7_pwm_e_sel); > +static struct clk_regmap t7_pwm_e = > + SPI_PWM_CLK_GATE(t7_pwm_e, CLKCTRL_PWM_CLK_EF_CTRL, 8, t7_pwm_e_div); > + > +static struct clk_regmap t7_pwm_f_sel = > + SPI_PWM_CLK_MUX(t7_pwm_f, CLKCTRL_PWM_CLK_EF_CTRL, 0x3, 25, t7_pwm_parents); > +static struct clk_regmap t7_pwm_f_div = > + SPI_PWM_CLK_DIV(t7_pwm_f, CLKCTRL_PWM_CLK_EF_CTRL, 16, 8, t7_pwm_f_sel); > +static struct clk_regmap t7_pwm_f = > + SPI_PWM_CLK_GATE(t7_pwm_f, CLKCTRL_PWM_CLK_EF_CTRL, 24, t7_pwm_f_div); > + > +static struct clk_regmap t7_pwm_ao_a_sel = > + SPI_PWM_CLK_MUX(t7_pwm_ao_a, CLKCTRL_PWM_CLK_AO_AB_CTRL, 0x3, 9, t7_pwm_parents); > +static struct clk_regmap t7_pwm_ao_a_div = > + SPI_PWM_CLK_DIV(t7_pwm_ao_a, CLKCTRL_PWM_CLK_AO_AB_CTRL, 0, 8, t7_pwm_ao_a_sel); > +static struct clk_regmap t7_pwm_ao_a = > + SPI_PWM_CLK_GATE(t7_pwm_ao_a, CLKCTRL_PWM_CLK_AO_AB_CTRL, 8, t7_pwm_ao_a_div); > + > +static struct clk_regmap t7_pwm_ao_b_sel = > + SPI_PWM_CLK_MUX(t7_pwm_ao_b, CLKCTRL_PWM_CLK_AO_AB_CTRL, 0x3, 25, t7_pwm_parents); > +static struct clk_regmap t7_pwm_ao_b_div = > + SPI_PWM_CLK_DIV(t7_pwm_ao_b, CLKCTRL_PWM_CLK_AO_AB_CTRL, 16, 8, t7_pwm_ao_b_sel); > +static struct clk_regmap t7_pwm_ao_b = > + SPI_PWM_CLK_GATE(t7_pwm_ao_b, CLKCTRL_PWM_CLK_AO_AB_CTRL, 24, t7_pwm_ao_b_div); > + > +static struct clk_regmap t7_pwm_ao_c_sel = > + SPI_PWM_CLK_MUX(t7_pwm_ao_c, CLKCTRL_PWM_CLK_AO_CD_CTRL, 0x3, 9, t7_pwm_parents); > +static struct clk_regmap t7_pwm_ao_c_div = > + SPI_PWM_CLK_DIV(t7_pwm_ao_c, CLKCTRL_PWM_CLK_AO_CD_CTRL, 0, 8, t7_pwm_ao_c_sel); > +static struct clk_regmap t7_pwm_ao_c = > + SPI_PWM_CLK_GATE(t7_pwm_ao_c, CLKCTRL_PWM_CLK_AO_CD_CTRL, 8, t7_pwm_ao_c_div); > + > +static struct clk_regmap t7_pwm_ao_d_sel = > + SPI_PWM_CLK_MUX(t7_pwm_ao_d, CLKCTRL_PWM_CLK_AO_CD_CTRL, 0x3, 25, t7_pwm_parents); > +static struct clk_regmap t7_pwm_ao_d_div = > + SPI_PWM_CLK_DIV(t7_pwm_ao_d, CLKCTRL_PWM_CLK_AO_CD_CTRL, 16, 8, t7_pwm_ao_d_sel); > +static struct clk_regmap t7_pwm_ao_d = > + SPI_PWM_CLK_GATE(t7_pwm_ao_d, CLKCTRL_PWM_CLK_AO_CD_CTRL, 24, t7_pwm_ao_d_div); > + > +static struct clk_regmap t7_pwm_ao_e_sel = > + SPI_PWM_CLK_MUX(t7_pwm_ao_e, CLKCTRL_PWM_CLK_AO_EF_CTRL, 0x3, 9, t7_pwm_parents); > +static struct clk_regmap t7_pwm_ao_e_div = > + SPI_PWM_CLK_DIV(t7_pwm_ao_e, CLKCTRL_PWM_CLK_AO_EF_CTRL, 0, 8, t7_pwm_ao_e_sel); > +static struct clk_regmap t7_pwm_ao_e = > + SPI_PWM_CLK_GATE(t7_pwm_ao_e, CLKCTRL_PWM_CLK_AO_EF_CTRL, 8, t7_pwm_ao_e_div); > + > +static struct clk_regmap t7_pwm_ao_f_sel = > + SPI_PWM_CLK_MUX(t7_pwm_ao_f, CLKCTRL_PWM_CLK_AO_EF_CTRL, 0x3, 25, t7_pwm_parents); > +static struct clk_regmap t7_pwm_ao_f_div = > + SPI_PWM_CLK_DIV(t7_pwm_ao_f, CLKCTRL_PWM_CLK_AO_EF_CTRL, 16, 8, t7_pwm_ao_f_sel); > +static struct clk_regmap t7_pwm_ao_f = > + SPI_PWM_CLK_GATE(t7_pwm_ao_f, CLKCTRL_PWM_CLK_AO_EF_CTRL, 24, t7_pwm_ao_f_div); > + > +static struct clk_regmap t7_pwm_ao_g_sel = > + SPI_PWM_CLK_MUX(t7_pwm_ao_g, CLKCTRL_PWM_CLK_AO_GH_CTRL, 0x3, 9, t7_pwm_parents); > +static struct clk_regmap t7_pwm_ao_g_div = > + SPI_PWM_CLK_DIV(t7_pwm_ao_g, CLKCTRL_PWM_CLK_AO_GH_CTRL, 0, 8, t7_pwm_ao_g_sel); > +static struct clk_regmap t7_pwm_ao_g = > + SPI_PWM_CLK_GATE(t7_pwm_ao_g, CLKCTRL_PWM_CLK_AO_GH_CTRL, 8, t7_pwm_ao_g_div); > + > +static struct clk_regmap t7_pwm_ao_h_sel = > + SPI_PWM_CLK_MUX(t7_pwm_ao_h, CLKCTRL_PWM_CLK_AO_GH_CTRL, 0x3, 25, t7_pwm_parents); > +static struct clk_regmap t7_pwm_ao_h_div = > + SPI_PWM_CLK_DIV(t7_pwm_ao_h, CLKCTRL_PWM_CLK_AO_GH_CTRL, 16, 8, t7_pwm_ao_h_sel); > +static struct clk_regmap t7_pwm_ao_h = > + SPI_PWM_CLK_GATE(t7_pwm_ao_h, CLKCTRL_PWM_CLK_AO_GH_CTRL, 24, t7_pwm_ao_h_div); > + > +#define MESON_GATE(_name, _reg, _bit) MESON_PCLK_V2(_name, _reg, _bit, sys) > + > +static MESON_GATE(t7_sys_ddr, CLKCTRL_SYS_CLK_EN0_REG0, 0); > +static MESON_GATE(t7_sys_dos, CLKCTRL_SYS_CLK_EN0_REG0, 1); > +static MESON_GATE(t7_sys_mipi_dsi_a, CLKCTRL_SYS_CLK_EN0_REG0, 2); > +static MESON_GATE(t7_sys_mipi_dsi_b, CLKCTRL_SYS_CLK_EN0_REG0, 3); > +static MESON_GATE(t7_sys_ethphy, CLKCTRL_SYS_CLK_EN0_REG0, 4); > +static MESON_GATE(t7_sys_mali, CLKCTRL_SYS_CLK_EN0_REG0, 6); > +static MESON_GATE(t7_sys_aocpu, CLKCTRL_SYS_CLK_EN0_REG0, 13); > +static MESON_GATE(t7_sys_aucpu, CLKCTRL_SYS_CLK_EN0_REG0, 14); > +static MESON_GATE(t7_sys_cec, CLKCTRL_SYS_CLK_EN0_REG0, 16); > +static MESON_GATE(t7_sys_gdc, CLKCTRL_SYS_CLK_EN0_REG0, 17); > +static MESON_GATE(t7_sys_deswarp, CLKCTRL_SYS_CLK_EN0_REG0, 18); > +static MESON_GATE(t7_sys_ampipe_nand, CLKCTRL_SYS_CLK_EN0_REG0, 19); > +static MESON_GATE(t7_sys_ampipe_eth, CLKCTRL_SYS_CLK_EN0_REG0, 20); > +static MESON_GATE(t7_sys_am2axi0, CLKCTRL_SYS_CLK_EN0_REG0, 21); > +static MESON_GATE(t7_sys_am2axi1, CLKCTRL_SYS_CLK_EN0_REG0, 22); > +static MESON_GATE(t7_sys_am2axi2, CLKCTRL_SYS_CLK_EN0_REG0, 23); > +static MESON_GATE(t7_sys_sdemmca, CLKCTRL_SYS_CLK_EN0_REG0, 24); > +static MESON_GATE(t7_sys_sdemmcb, CLKCTRL_SYS_CLK_EN0_REG0, 25); > +static MESON_GATE(t7_sys_sdemmcc, CLKCTRL_SYS_CLK_EN0_REG0, 26); > +static MESON_GATE(t7_sys_smartcard, CLKCTRL_SYS_CLK_EN0_REG0, 27); > +static MESON_GATE(t7_sys_acodec, CLKCTRL_SYS_CLK_EN0_REG0, 28); > +static MESON_GATE(t7_sys_spifc, CLKCTRL_SYS_CLK_EN0_REG0, 29); > +static MESON_GATE(t7_sys_msr_clk, CLKCTRL_SYS_CLK_EN0_REG0, 30); > +static MESON_GATE(t7_sys_ir_ctrl, CLKCTRL_SYS_CLK_EN0_REG0, 31); > +static MESON_GATE(t7_sys_audio, CLKCTRL_SYS_CLK_EN0_REG1, 0); > +static MESON_GATE(t7_sys_eth, CLKCTRL_SYS_CLK_EN0_REG1, 3); > +static MESON_GATE(t7_sys_uart_a, CLKCTRL_SYS_CLK_EN0_REG1, 5); > +static MESON_GATE(t7_sys_uart_b, CLKCTRL_SYS_CLK_EN0_REG1, 6); > +static MESON_GATE(t7_sys_uart_c, CLKCTRL_SYS_CLK_EN0_REG1, 7); > +static MESON_GATE(t7_sys_uart_d, CLKCTRL_SYS_CLK_EN0_REG1, 8); > +static MESON_GATE(t7_sys_uart_e, CLKCTRL_SYS_CLK_EN0_REG1, 9); > +static MESON_GATE(t7_sys_uart_f, CLKCTRL_SYS_CLK_EN0_REG1, 10); > +static MESON_GATE(t7_sys_aififo, CLKCTRL_SYS_CLK_EN0_REG1, 11); > +static MESON_GATE(t7_sys_spicc2, CLKCTRL_SYS_CLK_EN0_REG1, 12); > +static MESON_GATE(t7_sys_spicc3, CLKCTRL_SYS_CLK_EN0_REG1, 13); > +static MESON_GATE(t7_sys_spicc4, CLKCTRL_SYS_CLK_EN0_REG1, 14); > +static MESON_GATE(t7_sys_ts_a73, CLKCTRL_SYS_CLK_EN0_REG1, 15); > +static MESON_GATE(t7_sys_ts_a53, CLKCTRL_SYS_CLK_EN0_REG1, 16); > +static MESON_GATE(t7_sys_spicc5, CLKCTRL_SYS_CLK_EN0_REG1, 17); > +static MESON_GATE(t7_sys_g2d, CLKCTRL_SYS_CLK_EN0_REG1, 20); > +static MESON_GATE(t7_sys_spicc0, CLKCTRL_SYS_CLK_EN0_REG1, 21); > +static MESON_GATE(t7_sys_spicc1, CLKCTRL_SYS_CLK_EN0_REG1, 22); > +static MESON_GATE(t7_sys_pcie, CLKCTRL_SYS_CLK_EN0_REG1, 24); > +static MESON_GATE(t7_sys_usb, CLKCTRL_SYS_CLK_EN0_REG1, 26); > +static MESON_GATE(t7_sys_pcie_phy, CLKCTRL_SYS_CLK_EN0_REG1, 27); > +static MESON_GATE(t7_sys_i2c_ao_a, CLKCTRL_SYS_CLK_EN0_REG1, 28); > +static MESON_GATE(t7_sys_i2c_ao_b, CLKCTRL_SYS_CLK_EN0_REG1, 29); > +static MESON_GATE(t7_sys_i2c_m_a, CLKCTRL_SYS_CLK_EN0_REG1, 30); > +static MESON_GATE(t7_sys_i2c_m_b, CLKCTRL_SYS_CLK_EN0_REG1, 31); > +static MESON_GATE(t7_sys_i2c_m_c, CLKCTRL_SYS_CLK_EN0_REG2, 0); > +static MESON_GATE(t7_sys_i2c_m_d, CLKCTRL_SYS_CLK_EN0_REG2, 1); > +static MESON_GATE(t7_sys_i2c_m_e, CLKCTRL_SYS_CLK_EN0_REG2, 2); > +static MESON_GATE(t7_sys_i2c_m_f, CLKCTRL_SYS_CLK_EN0_REG2, 3); > +static MESON_GATE(t7_sys_hdmitx_apb, CLKCTRL_SYS_CLK_EN0_REG2, 4); > +static MESON_GATE(t7_sys_i2c_s_a, CLKCTRL_SYS_CLK_EN0_REG2, 5); > +static MESON_GATE(t7_sys_hdmirx_pclk, CLKCTRL_SYS_CLK_EN0_REG2, 8); > +static MESON_GATE(t7_sys_mmc_apb, CLKCTRL_SYS_CLK_EN0_REG2, 11); > +static MESON_GATE(t7_sys_mipi_isp_pclk, CLKCTRL_SYS_CLK_EN0_REG2, 17); > +static MESON_GATE(t7_sys_rsa, CLKCTRL_SYS_CLK_EN0_REG2, 18); > +static MESON_GATE(t7_sys_pclk_sys_apb, CLKCTRL_SYS_CLK_EN0_REG2, 19); > +static MESON_GATE(t7_sys_a73pclk_apb, CLKCTRL_SYS_CLK_EN0_REG2, 20); > +static MESON_GATE(t7_sys_dspa, CLKCTRL_SYS_CLK_EN0_REG2, 21); > +static MESON_GATE(t7_sys_dspb, CLKCTRL_SYS_CLK_EN0_REG2, 22); > +static MESON_GATE(t7_sys_vpu_intr, CLKCTRL_SYS_CLK_EN0_REG2, 25); > +static MESON_GATE(t7_sys_sar_adc, CLKCTRL_SYS_CLK_EN0_REG2, 28); > +static MESON_GATE(t7_sys_ts_gpu, CLKCTRL_SYS_CLK_EN0_REG2, 31); > +static MESON_GATE(t7_sys_ts_nna, CLKCTRL_SYS_CLK_EN0_REG3, 0); > +static MESON_GATE(t7_sys_ts_vpu, CLKCTRL_SYS_CLK_EN0_REG3, 1); > +static MESON_GATE(t7_sys_ts_hevc, CLKCTRL_SYS_CLK_EN0_REG3, 2); > +static MESON_GATE(t7_sys_pwm_ao_ab, CLKCTRL_SYS_CLK_EN0_REG3, 3); > +static MESON_GATE(t7_sys_pwm_ao_cd, CLKCTRL_SYS_CLK_EN0_REG3, 4); > +static MESON_GATE(t7_sys_pwm_ao_ef, CLKCTRL_SYS_CLK_EN0_REG3, 5); > +static MESON_GATE(t7_sys_pwm_ao_gh, CLKCTRL_SYS_CLK_EN0_REG3, 6); > +static MESON_GATE(t7_sys_pwm_ab, CLKCTRL_SYS_CLK_EN0_REG3, 7); > +static MESON_GATE(t7_sys_pwm_cd, CLKCTRL_SYS_CLK_EN0_REG3, 8); > +static MESON_GATE(t7_sys_pwm_ef, CLKCTRL_SYS_CLK_EN0_REG3, 9); > + > +/* > + * sys_gic provides the clock for GIC(Generic Interrupt Controller). > + * After clock is disabled, The GIC cannot work properly. At present, the driver > + * used by our GIC is the public driver in kernel, and there is no management > + * clock in the driver. > + */ > +static struct clk_regmap t7_sys_gic = { > + .data = &(struct clk_regmap_gate_data) { > + .offset = CLKCTRL_SYS_CLK_EN0_REG2, > + .bit_idx = 30, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "t7_sys_gic", > + .ops = &clk_regmap_gate_ops, > + .parent_data = &(const struct clk_parent_data) { > + .fw_name = "sys", > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, Do you really intend to for the rate of the sys pll to be set through this clock ? > + }, > +}; > + > +/* Array of all clocks registered by this provider */ > +static struct clk_hw *t7_periphs_hw_clks[] = { > + [CLKID_RTC_32K_IN] = &t7_rtc_32k_in.hw, > + [CLKID_RTC_32K_DIV] = &t7_rtc_32k_div.hw, > + [CLKID_RTC_32K_FORCE_SEL] = &t7_rtc_32k_force_sel.hw, > + [CLKID_RTC_32K_OUT] = &t7_rtc_32k_out.hw, > + [CLKID_RTC_32K_MUX0_0] = &t7_rtc_32k_mux0_0.hw, > + [CLKID_RTC_32K_MUX0_1] = &t7_rtc_32k_mux0_1.hw, > + [CLKID_RTC] = &t7_rtc.hw, > + [CLKID_CECB_32K_IN] = &t7_cecb_32k_in.hw, > + [CLKID_CECB_32K_DIV] = &t7_cecb_32k_div.hw, > + [CLKID_CECB_32K_SEL_PRE] = &t7_cecb_32k_sel_pre.hw, > + [CLKID_CECB_32K_SEL] = &t7_cecb_32k_sel.hw, > + [CLKID_CECA_32K_IN] = &t7_ceca_32k_in.hw, > + [CLKID_CECA_32K_DIV] = &t7_ceca_32k_div.hw, > + [CLKID_CECA_32K_SEL_PRE] = &t7_ceca_32k_sel_pre.hw, > + [CLKID_CECA_32K_SEL] = &t7_ceca_32k_sel.hw, > + [CLKID_CECA_32K] = &t7_ceca_32k_out.hw, > + [CLKID_CECB_32K] = &t7_cecb_32k_out.hw, > + [CLKID_SC_SEL] = &t7_sc_sel.hw, > + [CLKID_SC_DIV] = &t7_sc_div.hw, > + [CLKID_SC] = &t7_sc.hw, > + [CLKID_DSPA_A_SEL] = &t7_dspa_a_sel.hw, > + [CLKID_DSPA_A_DIV] = &t7_dspa_a_div.hw, > + [CLKID_DSPA_A] = &t7_dspa_a.hw, > + [CLKID_DSPA_B_SEL] = &t7_dspa_b_sel.hw, > + [CLKID_DSPA_B_DIV] = &t7_dspa_b_div.hw, > + [CLKID_DSPA_B] = &t7_dspa_b.hw, > + [CLKID_DSPA] = &t7_dspa.hw, > + [CLKID_DSPB_A_SEL] = &t7_dspb_a_sel.hw, > + [CLKID_DSPB_A_DIV] = &t7_dspb_a_div.hw, > + [CLKID_DSPB_A] = &t7_dspb_a.hw, > + [CLKID_DSPB_B_SEL] = &t7_dspb_b_sel.hw, > + [CLKID_DSPB_B_DIV] = &t7_dspb_b_div.hw, > + [CLKID_DSPB_B] = &t7_dspb_b.hw, > + [CLKID_DSPB] = &t7_dspb.hw, > + [CLKID_CLK_24M] = &t7_clk_24m.hw, > + [CLKID_CLK_24M_DIV2] = &t7_clk_24m_div2.hw, > + [CLKID_CLK_12M] = &t7_clk_12m.hw, > + [CLKID_ANAKIN_0_SEL] = &t7_anakin_0_sel.hw, > + [CLKID_ANAKIN_0_DIV] = &t7_anakin_0_div.hw, > + [CLKID_ANAKIN_0] = &t7_anakin_0.hw, > + [CLKID_ANAKIN_1_SEL] = &t7_anakin_1_sel.hw, > + [CLKID_ANAKIN_1_DIV] = &t7_anakin_1_div.hw, > + [CLKID_ANAKIN_1] = &t7_anakin_1.hw, > + [CLKID_ANAKIN] = &t7_anakin.hw, > + [CLKID_ANAKIN_CLK] = &t7_anakin_clk.hw, > + [CLKID_FCLK_DIV2_DIVN_PRE] = &t7_fdiv2_divn_pre.hw, > + [CLKID_FCLK_DIV2_DIVN] = &t7_fdiv2_divn.hw, > + [CLKID_MIPI_CSI_PHY_0_SEL] = &t7_mipi_csi_phy0_sel.hw, > + [CLKID_MIPI_CSI_PHY_0_DIV] = &t7_mipi_csi_phy0_div.hw, > + [CLKID_MIPI_CSI_PHY_0] = &t7_mipi_csi_phy0.hw, > + [CLKID_MIPI_CSI_PHY_1_SEL] = &t7_mipi_csi_phy1_sel.hw, > + [CLKID_MIPI_CSI_PHY_1_DIV] = &t7_mipi_csi_phy1_div.hw, > + [CLKID_MIPI_CSI_PHY_1] = &t7_mipi_csi_phy1.hw, > + [CLKID_MIPI_CSI_PHY] = &t7_mipi_csi_phy.hw, > + [CLKID_MIPI_ISP_SEL] = &t7_mipi_isp_sel.hw, > + [CLKID_MIPI_ISP_DIV] = &t7_mipi_isp_div.hw, > + [CLKID_MIPI_ISP] = &t7_mipi_isp.hw, > + [CLKID_TS_DIV] = &t7_ts_div.hw, > + [CLKID_TS] = &t7_ts.hw, > + [CLKID_MALI_0_SEL] = &t7_mali_0_sel.hw, > + [CLKID_MALI_0_DIV] = &t7_mali_0_div.hw, > + [CLKID_MALI_0] = &t7_mali_0.hw, > + [CLKID_MALI_1_SEL] = &t7_mali_1_sel.hw, > + [CLKID_MALI_1_DIV] = &t7_mali_1_div.hw, > + [CLKID_MALI_1] = &t7_mali_1.hw, > + [CLKID_MALI] = &t7_mali.hw, > + [CLKID_ETH_RMII_SEL] = &t7_eth_rmii_sel.hw, > + [CLKID_ETH_RMII_DIV] = &t7_eth_rmii_div.hw, > + [CLKID_ETH_RMII] = &t7_eth_rmii.hw, > + [CLKID_FCLK_DIV2_DIV8] = &t7_fdiv2_div8.hw, > + [CLKID_ETH_125M] = &t7_eth_125m.hw, > + [CLKID_SD_EMMC_C_SEL] = &t7_sd_emmc_c_sel.hw, > + [CLKID_SD_EMMC_C_DIV] = &t7_sd_emmc_c_div.hw, > + [CLKID_SD_EMMC_C] = &t7_sd_emmc_c.hw, > + [CLKID_SD_EMMC_A_SEL] = &t7_sd_emmc_a_sel.hw, > + [CLKID_SD_EMMC_A_DIV] = &t7_sd_emmc_a_div.hw, > + [CLKID_SD_EMMC_A] = &t7_sd_emmc_a.hw, > + [CLKID_SD_EMMC_B_SEL] = &t7_sd_emmc_b_sel.hw, > + [CLKID_SD_EMMC_B_DIV] = &t7_sd_emmc_b_div.hw, > + [CLKID_SD_EMMC_B] = &t7_sd_emmc_b.hw, > + [CLKID_SPICC0_SEL] = &t7_spicc0_sel.hw, > + [CLKID_SPICC0_DIV] = &t7_spicc0_div.hw, > + [CLKID_SPICC0] = &t7_spicc0.hw, > + [CLKID_SPICC1_SEL] = &t7_spicc1_sel.hw, > + [CLKID_SPICC1_DIV] = &t7_spicc1_div.hw, > + [CLKID_SPICC1] = &t7_spicc1.hw, > + [CLKID_SPICC2_SEL] = &t7_spicc2_sel.hw, > + [CLKID_SPICC2_DIV] = &t7_spicc2_div.hw, > + [CLKID_SPICC2] = &t7_spicc2.hw, > + [CLKID_SPICC3_SEL] = &t7_spicc3_sel.hw, > + [CLKID_SPICC3_DIV] = &t7_spicc3_div.hw, > + [CLKID_SPICC3] = &t7_spicc3.hw, > + [CLKID_SPICC4_SEL] = &t7_spicc4_sel.hw, > + [CLKID_SPICC4_DIV] = &t7_spicc4_div.hw, > + [CLKID_SPICC4] = &t7_spicc4.hw, > + [CLKID_SPICC5_SEL] = &t7_spicc5_sel.hw, > + [CLKID_SPICC5_DIV] = &t7_spicc5_div.hw, > + [CLKID_SPICC5] = &t7_spicc5.hw, > + [CLKID_SARADC_SEL] = &t7_saradc_sel.hw, > + [CLKID_SARADC_DIV] = &t7_saradc_div.hw, > + [CLKID_SARADC] = &t7_saradc.hw, > + [CLKID_PWM_A_SEL] = &t7_pwm_a_sel.hw, > + [CLKID_PWM_A_DIV] = &t7_pwm_a_div.hw, > + [CLKID_PWM_A] = &t7_pwm_a.hw, > + [CLKID_PWM_B_SEL] = &t7_pwm_b_sel.hw, > + [CLKID_PWM_B_DIV] = &t7_pwm_b_div.hw, > + [CLKID_PWM_B] = &t7_pwm_b.hw, > + [CLKID_PWM_C_SEL] = &t7_pwm_c_sel.hw, > + [CLKID_PWM_C_DIV] = &t7_pwm_c_div.hw, > + [CLKID_PWM_C] = &t7_pwm_c.hw, > + [CLKID_PWM_D_SEL] = &t7_pwm_d_sel.hw, > + [CLKID_PWM_D_DIV] = &t7_pwm_d_div.hw, > + [CLKID_PWM_D] = &t7_pwm_d.hw, > + [CLKID_PWM_E_SEL] = &t7_pwm_e_sel.hw, > + [CLKID_PWM_E_DIV] = &t7_pwm_e_div.hw, > + [CLKID_PWM_E] = &t7_pwm_e.hw, > + [CLKID_PWM_F_SEL] = &t7_pwm_f_sel.hw, > + [CLKID_PWM_F_DIV] = &t7_pwm_f_div.hw, > + [CLKID_PWM_F] = &t7_pwm_f.hw, > + [CLKID_PWM_AO_A_SEL] = &t7_pwm_ao_a_sel.hw, > + [CLKID_PWM_AO_A_DIV] = &t7_pwm_ao_a_div.hw, > + [CLKID_PWM_AO_A] = &t7_pwm_ao_a.hw, > + [CLKID_PWM_AO_B_SEL] = &t7_pwm_ao_b_sel.hw, > + [CLKID_PWM_AO_B_DIV] = &t7_pwm_ao_b_div.hw, > + [CLKID_PWM_AO_B] = &t7_pwm_ao_b.hw, > + [CLKID_PWM_AO_C_SEL] = &t7_pwm_ao_c_sel.hw, > + [CLKID_PWM_AO_C_DIV] = &t7_pwm_ao_c_div.hw, > + [CLKID_PWM_AO_C] = &t7_pwm_ao_c.hw, > + [CLKID_PWM_AO_D_SEL] = &t7_pwm_ao_d_sel.hw, > + [CLKID_PWM_AO_D_DIV] = &t7_pwm_ao_d_div.hw, > + [CLKID_PWM_AO_D] = &t7_pwm_ao_d.hw, > + [CLKID_PWM_AO_E_SEL] = &t7_pwm_ao_e_sel.hw, > + [CLKID_PWM_AO_E_DIV] = &t7_pwm_ao_e_div.hw, > + [CLKID_PWM_AO_E] = &t7_pwm_ao_e.hw, > + [CLKID_PWM_AO_F_SEL] = &t7_pwm_ao_f_sel.hw, > + [CLKID_PWM_AO_F_DIV] = &t7_pwm_ao_f_div.hw, > + [CLKID_PWM_AO_F] = &t7_pwm_ao_f.hw, > + [CLKID_PWM_AO_G_SEL] = &t7_pwm_ao_g_sel.hw, > + [CLKID_PWM_AO_G_DIV] = &t7_pwm_ao_g_div.hw, > + [CLKID_PWM_AO_G] = &t7_pwm_ao_g.hw, > + [CLKID_PWM_AO_H_SEL] = &t7_pwm_ao_h_sel.hw, > + [CLKID_PWM_AO_H_DIV] = &t7_pwm_ao_h_div.hw, > + [CLKID_PWM_AO_H] = &t7_pwm_ao_h.hw, > + [CLKID_SYS_DDR] = &t7_sys_ddr.hw, > + [CLKID_SYS_DOS] = &t7_sys_dos.hw, > + [CLKID_SYS_MIPI_DSI_A] = &t7_sys_mipi_dsi_a.hw, > + [CLKID_SYS_MIPI_DSI_B] = &t7_sys_mipi_dsi_b.hw, > + [CLKID_SYS_ETHPHY] = &t7_sys_ethphy.hw, > + [CLKID_SYS_MALI] = &t7_sys_mali.hw, > + [CLKID_SYS_AOCPU] = &t7_sys_aocpu.hw, > + [CLKID_SYS_AUCPU] = &t7_sys_aucpu.hw, > + [CLKID_SYS_CEC] = &t7_sys_cec.hw, > + [CLKID_SYS_GDC] = &t7_sys_gdc.hw, > + [CLKID_SYS_DESWARP] = &t7_sys_deswarp.hw, > + [CLKID_SYS_AMPIPE_NAND] = &t7_sys_ampipe_nand.hw, > + [CLKID_SYS_AMPIPE_ETH] = &t7_sys_ampipe_eth.hw, > + [CLKID_SYS_AM2AXI0] = &t7_sys_am2axi0.hw, > + [CLKID_SYS_AM2AXI1] = &t7_sys_am2axi1.hw, > + [CLKID_SYS_AM2AXI2] = &t7_sys_am2axi2.hw, > + [CLKID_SYS_SD_EMMC_A] = &t7_sys_sdemmca.hw, > + [CLKID_SYS_SD_EMMC_B] = &t7_sys_sdemmcb.hw, > + [CLKID_SYS_SD_EMMC_C] = &t7_sys_sdemmcc.hw, > + [CLKID_SYS_SMARTCARD] = &t7_sys_smartcard.hw, > + [CLKID_SYS_ACODEC] = &t7_sys_acodec.hw, > + [CLKID_SYS_SPIFC] = &t7_sys_spifc.hw, > + [CLKID_SYS_MSR_CLK] = &t7_sys_msr_clk.hw, > + [CLKID_SYS_IR_CTRL] = &t7_sys_ir_ctrl.hw, > + [CLKID_SYS_AUDIO] = &t7_sys_audio.hw, > + [CLKID_SYS_ETH] = &t7_sys_eth.hw, > + [CLKID_SYS_UART_A] = &t7_sys_uart_a.hw, > + [CLKID_SYS_UART_B] = &t7_sys_uart_b.hw, > + [CLKID_SYS_UART_C] = &t7_sys_uart_c.hw, > + [CLKID_SYS_UART_D] = &t7_sys_uart_d.hw, > + [CLKID_SYS_UART_E] = &t7_sys_uart_e.hw, > + [CLKID_SYS_UART_F] = &t7_sys_uart_f.hw, > + [CLKID_SYS_AIFIFO] = &t7_sys_aififo.hw, > + [CLKID_SYS_SPICC2] = &t7_sys_spicc2.hw, > + [CLKID_SYS_SPICC3] = &t7_sys_spicc3.hw, > + [CLKID_SYS_SPICC4] = &t7_sys_spicc4.hw, > + [CLKID_SYS_TS_A73] = &t7_sys_ts_a73.hw, > + [CLKID_SYS_TS_A53] = &t7_sys_ts_a53.hw, > + [CLKID_SYS_SPICC5] = &t7_sys_spicc5.hw, > + [CLKID_SYS_G2D] = &t7_sys_g2d.hw, > + [CLKID_SYS_SPICC0] = &t7_sys_spicc0.hw, > + [CLKID_SYS_SPICC1] = &t7_sys_spicc1.hw, > + [CLKID_SYS_PCIE] = &t7_sys_pcie.hw, > + [CLKID_SYS_USB] = &t7_sys_usb.hw, > + [CLKID_SYS_PCIE_PHY] = &t7_sys_pcie_phy.hw, > + [CLKID_SYS_I2C_AO_A] = &t7_sys_i2c_ao_a.hw, > + [CLKID_SYS_I2C_AO_B] = &t7_sys_i2c_ao_b.hw, > + [CLKID_SYS_I2C_M_A] = &t7_sys_i2c_m_a.hw, > + [CLKID_SYS_I2C_M_B] = &t7_sys_i2c_m_b.hw, > + [CLKID_SYS_I2C_M_C] = &t7_sys_i2c_m_c.hw, > + [CLKID_SYS_I2C_M_D] = &t7_sys_i2c_m_d.hw, > + [CLKID_SYS_I2C_M_E] = &t7_sys_i2c_m_e.hw, > + [CLKID_SYS_I2C_M_F] = &t7_sys_i2c_m_f.hw, > + [CLKID_SYS_HDMITX_APB] = &t7_sys_hdmitx_apb.hw, > + [CLKID_SYS_I2C_S_A] = &t7_sys_i2c_s_a.hw, > + [CLKID_SYS_HDMIRX_PCLK] = &t7_sys_hdmirx_pclk.hw, > + [CLKID_SYS_MMC_APB] = &t7_sys_mmc_apb.hw, > + [CLKID_SYS_MIPI_ISP_PCLK] = &t7_sys_mipi_isp_pclk.hw, > + [CLKID_SYS_RSA] = &t7_sys_rsa.hw, > + [CLKID_SYS_PCLK_SYS_APB] = &t7_sys_pclk_sys_apb.hw, > + [CLKID_SYS_A73PCLK_APB] = &t7_sys_a73pclk_apb.hw, > + [CLKID_SYS_DSPA] = &t7_sys_dspa.hw, > + [CLKID_SYS_DSPB] = &t7_sys_dspb.hw, > + [CLKID_SYS_VPU_INTR] = &t7_sys_vpu_intr.hw, > + [CLKID_SYS_SAR_ADC] = &t7_sys_sar_adc.hw, > + [CLKID_SYS_GIC] = &t7_sys_gic.hw, > + [CLKID_SYS_TS_GPU] = &t7_sys_ts_gpu.hw, > + [CLKID_SYS_TS_NNA] = &t7_sys_ts_nna.hw, > + [CLKID_SYS_TS_VPU] = &t7_sys_ts_vpu.hw, > + [CLKID_SYS_TS_HEVC] = &t7_sys_ts_hevc.hw, > + [CLKID_SYS_PWM_AB] = &t7_sys_pwm_ab.hw, > + [CLKID_SYS_PWM_CD] = &t7_sys_pwm_cd.hw, > + [CLKID_SYS_PWM_EF] = &t7_sys_pwm_ef.hw, > + [CLKID_SYS_PWM_AO_AB] = &t7_sys_pwm_ao_ab.hw, > + [CLKID_SYS_PWM_AO_CD] = &t7_sys_pwm_ao_cd.hw, > + [CLKID_SYS_PWM_AO_EF] = &t7_sys_pwm_ao_ef.hw, > + [CLKID_SYS_PWM_AO_GH] = &t7_sys_pwm_ao_gh.hw, > +}; > + > +/* Convenience table to populate regmap in .probe */ > +static struct clk_regmap *const t7_periphs_regmaps[] = { > + &t7_rtc_32k_in, > + &t7_rtc_32k_div, > + &t7_rtc_32k_force_sel, > + &t7_rtc_32k_out, > + &t7_rtc_32k_mux0_0, > + &t7_rtc_32k_mux0_1, > + &t7_rtc, > + &t7_cecb_32k_in, > + &t7_cecb_32k_div, > + &t7_cecb_32k_sel_pre, > + &t7_cecb_32k_sel, > + &t7_ceca_32k_in, > + &t7_ceca_32k_div, > + &t7_ceca_32k_sel_pre, > + &t7_ceca_32k_sel, > + &t7_ceca_32k_out, > + &t7_cecb_32k_out, > + &t7_sc_sel, > + &t7_sc_div, > + &t7_sc, > + &t7_dspa_a_sel, > + &t7_dspa_a_div, > + &t7_dspa_a, > + &t7_dspa_b_sel, > + &t7_dspa_b_div, > + &t7_dspa_b, > + &t7_dspa, > + &t7_dspb_a_sel, > + &t7_dspb_a_div, > + &t7_dspb_a, > + &t7_dspb_b_sel, > + &t7_dspb_b_div, > + &t7_dspb_b, > + &t7_dspb, > + &t7_clk_24m, > + &t7_clk_12m, > + &t7_anakin_0_sel, > + &t7_anakin_0_div, > + &t7_anakin_0, > + &t7_anakin_1_sel, > + &t7_anakin_1_div, > + &t7_anakin_1, > + &t7_anakin, > + &t7_anakin_clk, > + &t7_fdiv2_divn_pre, > + &t7_fdiv2_divn, > + &t7_mipi_csi_phy0_sel, > + &t7_mipi_csi_phy0_div, > + &t7_mipi_csi_phy0, > + &t7_mipi_csi_phy1_sel, > + &t7_mipi_csi_phy1_div, > + &t7_mipi_csi_phy1, > + &t7_mipi_csi_phy, > + &t7_mipi_isp_sel, > + &t7_mipi_isp_div, > + &t7_mipi_isp, > + &t7_ts_div, > + &t7_ts, > + &t7_mali_0_sel, > + &t7_mali_0_div, > + &t7_mali_0, > + &t7_mali_1_sel, > + &t7_mali_1_div, > + &t7_mali_1, > + &t7_mali, > + &t7_eth_rmii_sel, > + &t7_eth_rmii_div, > + &t7_eth_rmii, > + &t7_eth_125m, > + &t7_sd_emmc_c_sel, > + &t7_sd_emmc_c_div, > + &t7_sd_emmc_c, > + &t7_sd_emmc_a_sel, > + &t7_sd_emmc_a_div, > + &t7_sd_emmc_a, > + &t7_sd_emmc_b_sel, > + &t7_sd_emmc_b_div, > + &t7_sd_emmc_b, > + &t7_spicc0_sel, > + &t7_spicc0_div, > + &t7_spicc0, > + &t7_spicc1_sel, > + &t7_spicc1_div, > + &t7_spicc1, > + &t7_spicc2_sel, > + &t7_spicc2_div, > + &t7_spicc2, > + &t7_spicc3_sel, > + &t7_spicc3_div, > + &t7_spicc3, > + &t7_spicc4_sel, > + &t7_spicc4_div, > + &t7_spicc4, > + &t7_spicc5_sel, > + &t7_spicc5_div, > + &t7_spicc5, > + &t7_saradc_sel, > + &t7_saradc_div, > + &t7_saradc, > + &t7_pwm_a_sel, > + &t7_pwm_a_div, > + &t7_pwm_a, > + &t7_pwm_b_sel, > + &t7_pwm_b_div, > + &t7_pwm_b, > + &t7_pwm_c_sel, > + &t7_pwm_c_div, > + &t7_pwm_c, > + &t7_pwm_d_sel, > + &t7_pwm_d_div, > + &t7_pwm_d, > + &t7_pwm_e_sel, > + &t7_pwm_e_div, > + &t7_pwm_e, > + &t7_pwm_f_sel, > + &t7_pwm_f_div, > + &t7_pwm_f, > + &t7_pwm_ao_a_sel, > + &t7_pwm_ao_a_div, > + &t7_pwm_ao_a, > + &t7_pwm_ao_b_sel, > + &t7_pwm_ao_b_div, > + &t7_pwm_ao_b, > + &t7_pwm_ao_c_sel, > + &t7_pwm_ao_c_div, > + &t7_pwm_ao_c, > + &t7_pwm_ao_d_sel, > + &t7_pwm_ao_d_div, > + &t7_pwm_ao_d, > + &t7_pwm_ao_e_sel, > + &t7_pwm_ao_e_div, > + &t7_pwm_ao_e, > + &t7_pwm_ao_f_sel, > + &t7_pwm_ao_f_div, > + &t7_pwm_ao_f, > + &t7_pwm_ao_g_sel, > + &t7_pwm_ao_g_div, > + &t7_pwm_ao_g, > + &t7_pwm_ao_h_sel, > + &t7_pwm_ao_h_div, > + &t7_pwm_ao_h, > + &t7_pwm_ao_h, > + &t7_sys_ddr, > + &t7_sys_dos, > + &t7_sys_mipi_dsi_a, > + &t7_sys_mipi_dsi_b, > + &t7_sys_ethphy, > + &t7_sys_mali, > + &t7_sys_aocpu, > + &t7_sys_aucpu, > + &t7_sys_cec, > + &t7_sys_gdc, > + &t7_sys_deswarp, > + &t7_sys_ampipe_nand, > + &t7_sys_ampipe_eth, > + &t7_sys_am2axi0, > + &t7_sys_am2axi1, > + &t7_sys_am2axi2, > + &t7_sys_sdemmca, > + &t7_sys_sdemmcb, > + &t7_sys_sdemmcc, > + &t7_sys_smartcard, > + &t7_sys_acodec, > + &t7_sys_spifc, > + &t7_sys_msr_clk, > + &t7_sys_ir_ctrl, > + &t7_sys_audio, > + &t7_sys_eth, > + &t7_sys_uart_a, > + &t7_sys_uart_b, > + &t7_sys_uart_c, > + &t7_sys_uart_d, > + &t7_sys_uart_e, > + &t7_sys_uart_f, > + &t7_sys_aififo, > + &t7_sys_spicc2, > + &t7_sys_spicc3, > + &t7_sys_spicc4, > + &t7_sys_ts_a73, > + &t7_sys_ts_a53, > + &t7_sys_spicc5, > + &t7_sys_g2d, > + &t7_sys_spicc0, > + &t7_sys_spicc1, > + &t7_sys_pcie, > + &t7_sys_usb, > + &t7_sys_pcie_phy, > + &t7_sys_i2c_ao_a, > + &t7_sys_i2c_ao_b, > + &t7_sys_i2c_m_a, > + &t7_sys_i2c_m_b, > + &t7_sys_i2c_m_c, > + &t7_sys_i2c_m_d, > + &t7_sys_i2c_m_e, > + &t7_sys_i2c_m_f, > + &t7_sys_hdmitx_apb, > + &t7_sys_i2c_s_a, > + &t7_sys_hdmirx_pclk, > + &t7_sys_mmc_apb, > + &t7_sys_mipi_isp_pclk, > + &t7_sys_rsa, > + &t7_sys_pclk_sys_apb, > + &t7_sys_a73pclk_apb, > + &t7_sys_dspa, > + &t7_sys_dspb, > + &t7_sys_vpu_intr, > + &t7_sys_sar_adc, > + &t7_sys_gic, > + &t7_sys_ts_gpu, > + &t7_sys_ts_nna, > + &t7_sys_ts_vpu, > + &t7_sys_ts_hevc, > + &t7_sys_pwm_ab, > + &t7_sys_pwm_cd, > + &t7_sys_pwm_ef, > + &t7_sys_pwm_ao_ab, > + &t7_sys_pwm_ao_cd, > + &t7_sys_pwm_ao_ef, > + &t7_sys_pwm_ao_gh, > +}; > + > +static const struct regmap_config t7_periphs_regmap_cfg = { > + .reg_bits = 32, > + .val_bits = 32, > + .reg_stride = 4, > + .max_register = CLKCTRL_SPICC_CLK_CTRL2 > +}; > + > +static struct meson_clk_hw_data t7_periphs_clks = { > + .hws = t7_periphs_hw_clks, > + .num = ARRAY_SIZE(t7_periphs_hw_clks), > +}; > + > +static int amlogic_t7_periphs_probe(struct platform_device *pdev) > +{ > + struct device *dev = &pdev->dev; > + void __iomem *base; > + struct regmap *map; > + int i, ret; > + > + base = devm_platform_ioremap_resource(pdev, 0); > + if (IS_ERR(base)) > + return PTR_ERR(base); > + > + map = devm_regmap_init_mmio(dev, base, &t7_periphs_regmap_cfg); > + if (IS_ERR(map)) > + return PTR_ERR(map); > + > + /* Populate regmap for the regmap backed clocks */ > + for (i = 0; i < ARRAY_SIZE(t7_periphs_regmaps); i++) > + t7_periphs_regmaps[i]->map = map; > + > + for (i = 0; i < t7_periphs_clks.num; i++) { > + ret = devm_clk_hw_register(dev, t7_periphs_clks.hws[i]); > + if (ret) > + return ret; > + } > + > + return devm_of_clk_add_hw_provider(dev, meson_clk_hw_get, &t7_periphs_clks); > +} > + > +static const struct of_device_id t7_periphs_clkc_match_table[] = { > + { .compatible = "amlogic,t7-peripherals-clkc", }, > + {} > +}; > +MODULE_DEVICE_TABLE(of, t7_periphs_clkc_match_table); > + > +static struct platform_driver t7_periphs_clkc_driver = { > + .probe = amlogic_t7_periphs_probe, > + .driver = { > + .name = "t7-peripherals-clkc", > + .of_match_table = t7_periphs_clkc_match_table, > + }, > +}; > + > +MODULE_DESCRIPTION("Amlogic T7 Peripherals Clock Controller driver"); > +module_platform_driver(t7_periphs_clkc_driver); > +MODULE_AUTHOR("Jian Hu <jian.hu@amlogic.com>"); > +MODULE_LICENSE("GPL"); > +MODULE_IMPORT_NS("CLK_MESON"); -- Jerome ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v3 6/6] clk: meson: t7: add t7 clock peripherals controller driver 2025-05-14 8:00 ` Jerome Brunet @ 2025-06-13 9:39 ` Jian Hu 0 siblings, 0 replies; 19+ messages in thread From: Jian Hu @ 2025-06-13 9:39 UTC (permalink / raw) To: Jerome Brunet Cc: Xianwei Zhao, Chuan Liu, Neil Armstrong, Kevin Hilman, Stephen Boyd, Michael Turquette, Dmitry Rokosov, robh+dt, Rob Herring, devicetree, linux-clk, linux-amlogic, linux-kernel, linux-arm-kernel On 2025/5/14 16:00, Jerome Brunet wrote: > [ EXTERNAL EMAIL ] > > On Fri 09 May 2025 at 07:48, Jian Hu <jian.hu@amlogic.com> wrote: > >> Add Peripheral clock controller driver for the Amlogic T7 SoC family. >> >> Signed-off-by: Jian Hu <jian.hu@amlogic.com> >> --- >> drivers/clk/meson/Kconfig | 13 + >> drivers/clk/meson/Makefile | 1 + >> drivers/clk/meson/t7-peripherals.c | 2359 ++++++++++++++++++++++++++++ >> 3 files changed, 2373 insertions(+) >> create mode 100644 drivers/clk/meson/t7-peripherals.c >> >> ...... >> >> + >> +static u32 t7_eth_rmii_table[] = { 0, 7 }; >> + >> +static const struct clk_parent_data t7_eth_rmii_parents[] = { >> + { .fw_name = "fdiv2", }, >> + { .fw_name = "rmii_pad", }, > Are you sure about that ? check the bindings Ok, rmii_pad is optional parent, I will update it in DT bindings. >> + >> +#define SPI_PWM_CLK_MUX(_name, _reg, _mask, _shift, _parent_data) { \ >> + .data = &(struct clk_regmap_mux_data) { \ >> + .offset = _reg, \ >> + .mask = _mask, \ >> + .shift = _shift, \ >> + }, \ >> + .hw.init = &(struct clk_init_data) { \ >> + .name = #_name "_sel", \ >> + .ops = &clk_regmap_mux_ops, \ >> + .parent_data = _parent_data, \ >> + .num_parents = ARRAY_SIZE(_parent_data), \ >> + }, \ >> +} >> + >> +#define SPI_PWM_CLK_DIV(_name, _reg, _shift, _width, _parent) { \ >> + .data = &(struct clk_regmap_div_data) { \ >> + .offset = _reg, \ >> + .shift = _shift, \ >> + .width = _width, \ >> + }, \ >> + .hw.init = &(struct clk_init_data) { \ >> + .name = #_name "_div", \ >> + .ops = &clk_regmap_divider_ops, \ >> + .parent_hws = (const struct clk_hw *[]) { \ >> + &_parent.hw \ >> + }, \ >> + .num_parents = 1, \ >> + .flags = CLK_SET_RATE_PARENT, \ >> + }, \ >> +} >> + >> +#define SPI_PWM_CLK_GATE(_name, _reg, _bit, _parent) { \ >> + .data = &(struct clk_regmap_gate_data) { \ >> + .offset = _reg, \ >> + .bit_idx = _bit, \ >> + }, \ >> + .hw.init = &(struct clk_init_data) { \ >> + .name = #_name, \ >> + .ops = &clk_regmap_gate_ops, \ >> + .parent_hws = (const struct clk_hw *[]) { \ >> + &_parent.hw \ >> + }, \ >> + .num_parents = 1, \ >> + .flags = CLK_SET_RATE_PARENT, \ >> + }, \ >> +} > > Again that something that has been repeated for way too long. > You'll wait for the clean-up to be done. If you want to help, you can > review and test the patch being sent. It may speed things up. I want to confirm here . you said the clean-up patch is not related to spi and pwm clocks, Right ? I can see the regmap drop table patch [0], is it the sending patch? [0]: https://patchwork.kernel.org/project/linux-amlogic/patch/20250120-amlogic-clk-drop-clk-regmap-tables-v3-0-126244146947@baylibre.com/ I will apply the regmap clean-up patch serial and verified it on T7. If not， Please correct me. >> + >> +static const struct clk_parent_data t7_spicc_parents[] = { >> + { .fw_name = "xtal", }, >> + { .fw_name = "sys", }, >> + { .fw_name = "fdiv4", }, >> + { .fw_name = "fdiv3", }, >> + { .fw_name = "fdiv2", }, >> + { .fw_name = "fdiv5", }, >> + { .fw_name = "fdiv7", }, >> + { .fw_name = "gp1", }, >> +}; >> + >> ...... >> +static struct clk_regmap t7_sys_gic = { >> + .data = &(struct clk_regmap_gate_data) { >> + .offset = CLKCTRL_SYS_CLK_EN0_REG2, >> + .bit_idx = 30, >> + }, >> + .hw.init = &(struct clk_init_data){ >> + .name = "t7_sys_gic", >> + .ops = &clk_regmap_gate_ops, >> + .parent_data = &(const struct clk_parent_data) { >> + .fw_name = "sys", >> + }, >> + .num_parents = 1, >> + .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, > Do you really intend to for the rate of the sys pll to be set through > this clock ? Ok, CLK_SET_RATE_PARENT is not necessary here, I will remove it. >> ...... > -- > Jerome ^ permalink raw reply [flat|nested] 19+ messages in thread
end of thread, other threads:[~2025-07-03 3:42 UTC | newest]
Thread overview: 19+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-05-09 7:48 [PATCH v3 0/6] add support for T7 family clock controller Jian Hu
2025-05-09 7:48 ` [PATCH v3 1/6] dt-bindings: clock: add Amlogic T7 PLL " Jian Hu
2025-05-09 16:09 ` Conor Dooley
2025-05-09 7:48 ` [PATCH v3 2/6] dt-bindings: clock: add Amlogic T7 SCMI " Jian Hu
2025-05-09 7:48 ` [PATCH v3 3/6] dt-bindings: clock: add Amlogic T7 peripherals " Jian Hu
2025-05-09 7:48 ` [PATCH v3 4/6] clk: meson: t7: add support for the T7 SoC PLL clock Jian Hu
2025-05-14 7:52 ` Jerome Brunet
2025-06-12 13:02 ` Jian Hu
2025-06-16 16:27 ` Jerome Brunet
2025-06-25 2:52 ` Jian Hu
2025-06-25 7:46 ` Jerome Brunet
2025-07-03 3:42 ` Jian Hu
2025-05-09 7:48 ` [PATCH v3 5/6] clk: meson: add MESON_PCLK_V2 for sys gate clock Jian Hu
2025-05-14 7:39 ` Jerome Brunet
[not found] ` <ea83e375-7088-4047-92f1-31d0e7c2c331@amlogic.com>
2025-06-16 16:28 ` Jerome Brunet
2025-06-20 9:21 ` Jian Hu
2025-05-09 7:48 ` [PATCH v3 6/6] clk: meson: t7: add t7 clock peripherals controller driver Jian Hu
2025-05-14 8:00 ` Jerome Brunet
2025-06-13 9:39 ` Jian Hu
This is a public inbox, see mirroring instructions for how to clone and mirror all data and code used for this inbox; as well as URLs for NNTP newsgroup(s).