Re: [PATCH v4 5/5] clk: meson: t7: add t7 clock peripherals controller driver

[Jian Hu <jian.hu@amlogic.com>]

On 11/4/2025 6:14 PM, Jerome Brunet wrote:
> [ EXTERNAL EMAIL ]
>
> On Tue 04 Nov 2025 at 17:17, Jian Hu <jian.hu@amlogic.com> wrote:
>
>>>> +
>>>> +static struct clk_regmap t7_dspa = {
>>>> +     .data = &(struct clk_regmap_mux_data){
>>>> +             .offset = DSPA_CLK_CTRL0,
>>>> +             .mask = 0x1,
>>>> +             .shift = 15,
>>>> +     },
>>>> +     .hw.init = &(struct clk_init_data){
>>>> +             .name = "dspa",
>>>> +             .ops = &clk_regmap_mux_ops,
>>>> +             .parent_hws = (const struct clk_hw *[]) {
>>>> +                     &t7_dspa_a.hw,
>>>> +                     &t7_dspa_b.hw,
>>>> +             },
>>>> +             .num_parents = 2,
>>>> +             .flags = CLK_SET_RATE_PARENT,
>>>> +     },
>>>> +};
>>>> +
>>>> ......
>>>> +
>>>> +static struct clk_regmap t7_anakin_0 = {
>>> Nitpick: for the DSP it was a/b, here it is 0/1
>>> Could you pick one way or the other and stick to it ?
>>
>> ok , I will use 0/1 for DSP.
> I think I prefer a/b if you don't mind. see below for why ...


Mali is named as mali_0, mali_1 in this driver.   And G12A/S4/GXBB 
series do the same.

If they are named as anakin_a and anakin_b here, there will be two 
naming methods.

Shall we keep consistent ?


If use 0/1 to name them.

dsp clocks are:

     dspa_0_sel

     dspa_0_div

     dspa_0

     dspa_1_sel

     dspa_1_div

     dspa_1

     dspb_0_sel

     dspb_0_div

     dspb_0

     dspb_1_sel

     dspb_1_div

     dspb_1


anakin clocks are:

     anakin_0_sel

     anakin_0_div

     anakin_0

     anakin_1_sel

     anakin_1_div

     anakin_1

     anakin_01_sel

     anakin


If use a/b to name them.

dsp clocks are:

     dspa_a_sel

     dspa_a_div

     dspa_a

     dspa_b_sel

     dspa_b_div

     dspa_b

     dspb_a_sel

     dspb_a_div

     dspb_a

     dspb_b_sel

     dspb_b_div

     dspb_b


anakin clocks are:

     anakin_a_sel

     anakin_a_div

     anakin_a

     anakin_b_sel

     anakin_b_div

     anakin_b

     anakin_ab_sel

     anakin


Which one is better?

>>>> +     .data = &(struct clk_regmap_gate_data){
>>>> +             .offset = ANAKIN_CLK_CTRL,
>>>> +             .bit_idx = 8,
>>>> +     },
>>>> +     .hw.init = &(struct clk_init_data) {
>>>> +             .name = "anakin_0",
>>>> +             .ops = &clk_regmap_gate_ops,
>>>> +             .parent_hws = (const struct clk_hw *[]) { &t7_anakin_0_div.hw },
>>>> +             .num_parents = 1,
>>>> +             .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
>>>> +     },
>>>> +};
> [...]
>
>>>> +
>>>> +static struct clk_regmap t7_anakin_clk = {
>>>> +     .data = &(struct clk_regmap_gate_data){
>>>> +             .offset = ANAKIN_CLK_CTRL,
>>>> +             .bit_idx = 30,
>>>> +     },
>>>> +     .hw.init = &(struct clk_init_data) {
>>>> +             .name = "anakin_clk",
>>> Again, not a great name, especially considering the one above.
>>> Is this really really how the doc refers to these 2 clocks ?
>>
>> bit30 gate clock is after bit31 mux clock,  and the gate clock is the final
>> output clock, it is used to gate anakin clock.
>>
>> I will rename bit31 as anakin_pre, rename bit30 as anakin.
> Ok for the last element
>
> ... but I don't  like "_pre" for a mux selecting one the 2 glitch free
> path. It does not help understanding the tree.
>
> For such mux, when it is not the last element, I would suggest
> "_ab_sel" ... at least it is clear what it does so, "anakin_ab_sel" ?
>

ok, anakin_ab_sel and anakin for these two clocks.


Maybe anakin_01_sel and anakin for these two clocks, if you agree to 0/1 
naming convention.

>>>> +             .ops = &clk_regmap_gate_ops,
>>>> +             .parent_hws = (const struct clk_hw *[]) {
>>>> +                     &t7_anakin.hw
>>>> +             },
>>>> +             .num_parents = 1,
>>>> +             .flags = CLK_SET_RATE_PARENT
>>>> +     },
>>>> +};
>>>> +