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Mon, 03 Feb 2025 12:24:54 -0800 (PST) Received: from [100.64.0.1] ([165.188.116.9]) by smtp.gmail.com with ESMTPSA id 8926c6da1cb9f-4ec7458ef58sm2399719173.5.2025.02.03.12.24.52 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 03 Feb 2025 12:24:54 -0800 (PST) Message-ID: <237ce4e3-d66f-43ee-bd4e-38007dc750e5@sifive.com> Date: Mon, 3 Feb 2025 14:24:52 -0600 Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH RESEND v3 1/3] dt-bindings: clock: Add bindings for Canaan K230 clock controller To: Xukai Wang Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Troy Mitchell , Krzysztof Kozlowski , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley References: <20250203-b4-k230-clk-v3-0-362c79124572@zohomail.com> <20250203-b4-k230-clk-v3-1-362c79124572@zohomail.com> From: Samuel Holland Content-Language: en-US In-Reply-To: <20250203-b4-k230-clk-v3-1-362c79124572@zohomail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 2025-02-03 8:49 AM, Xukai Wang wrote: > This patch adds the Device Tree binding for the clock controller > on Canaan k230. The binding defines the new clocks available and > the required properties to configure them correctly. > > Reviewed-by: Krzysztof Kozlowski > Signed-off-by: Xukai Wang > --- > .../devicetree/bindings/clock/canaan,k230-clk.yaml | 43 +++++++++++++++++++ > include/dt-bindings/clock/canaan,k230-clk.h | 49 ++++++++++++++++++++++ > 2 files changed, 92 insertions(+) > > diff --git a/Documentation/devicetree/bindings/clock/canaan,k230-clk.yaml b/Documentation/devicetree/bindings/clock/canaan,k230-clk.yaml > new file mode 100644 > index 0000000000000000000000000000000000000000..d7220fa30e4699a68fa5279c04abc63c1905fa4a > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/canaan,k230-clk.yaml > @@ -0,0 +1,43 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/clock/canaan,k230-clk.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Canaan Kendryte K230 Clock > + > +maintainers: > + - Xukai Wang > + > +properties: > + compatible: > + const: canaan,k230-clk > + > + reg: > + items: > + - description: PLL control registers. > + - description: Sysclk control registers. >From the way the driver is structured, this looks rather like two separate hardware blocks, not two groups of registers for a single hardware block. For example, the driver registers two clock providers for the same DT node, with overlapping indexes. This doesn't work. Either you need two separate DT nodes -- one for the PLLs and another for the sysclks -- or you need to include the PLLs in the binding header below at non-overlapping indexes. Regards, Samuel > + > + clocks: > + maxItems: 1 > + > + '#clock-cells': > + const: 1 > + > +required: > + - compatible > + - reg > + - clocks > + - '#clock-cells' > + > +additionalProperties: false > + > +examples: > + - | > + clock-controller@91102000 { > + compatible = "canaan,k230-clk"; > + reg = <0x91102000 0x1000>, > + <0x91100000 0x1000>; > + clocks = <&osc24m>; > + #clock-cells = <1>; > + }; > diff --git a/include/dt-bindings/clock/canaan,k230-clk.h b/include/dt-bindings/clock/canaan,k230-clk.h > new file mode 100644 > index 0000000000000000000000000000000000000000..47d966fda5771615dad8ade64eeec42a9b27696e > --- /dev/null > +++ b/include/dt-bindings/clock/canaan,k230-clk.h > @@ -0,0 +1,49 @@ > +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ > +/* > + * Kendryte Canaan K230 Clock Drivers > + * > + * Author: Xukai Wang > + */ > + > +#ifndef CLOCK_K230_CLK_H > +#define CLOCK_K230_CLK_H > + > +/* Kendryte K230 SoC clock identifiers (arbitrary values). */ > +#define K230_CPU0_SRC 0 > +#define K230_CPU0_ACLK 1 > +#define K230_CPU0_PLIC 2 > +#define K230_CPU0_NOC_DDRCP4 3 > +#define K230_CPU0_PCLK 4 > +#define K230_PMU_PCLK 5 > +#define K230_HS_HCLK_HIGH_SRC 6 > +#define K230_HS_HCLK_HIGH_GATE 7 > +#define K230_HS_HCLK_SRC 8 > +#define K230_HS_SD0_HS_AHB_GAT 9 > +#define K230_HS_SD1_HS_AHB_GAT 10 > +#define K230_HS_SSI1_HS_AHB_GA 11 > +#define K230_HS_SSI2_HS_AHB_GA 12 > +#define K230_HS_USB0_HS_AHB_GA 13 > +#define K230_HS_USB1_HS_AHB_GA 14 > +#define K230_HS_SSI0_AXI15 15 > +#define K230_HS_SSI1 16 > +#define K230_HS_SSI2 17 > +#define K230_HS_QSPI_AXI_SRC 18 > +#define K230_HS_SSI1_ACLK_GATE 19 > +#define K230_HS_SSI2_ACLK_GATE 20 > +#define K230_HS_SD_CARD_SRC 21 > +#define K230_HS_SD0_CARD_TX 22 > +#define K230_HS_SD1_CARD_TX 23 > +#define K230_HS_SD_AXI_SRC 24 > +#define K230_HS_SD0_AXI_GATE 25 > +#define K230_HS_SD1_AXI_GATE 26 > +#define K230_HS_SD0_BASE_GATE 27 > +#define K230_HS_SD1_BASE_GATE 28 > +#define K230_HS_OSPI_SRC 29 > +#define K230_HS_USB_REF_50M 30 > +#define K230_HS_SD_TIMER_SRC 31 > +#define K230_HS_SD0_TIMER_GATE 32 > +#define K230_HS_SD1_TIMER_GATE 33 > +#define K230_HS_USB0_REFERENCE 34 > +#define K230_HS_USB1_REFERENCE 35 > + > +#endif /* CLOCK_K230_CLK_H */ >