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Wed, 28 Jan 2026 15:56:04 +0100 (CET) From: Alexander Stein To: AngeloGioacchino Del Regno , Chen-Yu Tsai , Chia-I Wu , Dong Aisheng , Laura Nao , Matthias Brugger , Michael Turquette , =?ISO-8859-1?Q?N=EDcolas_F=2E__R=2E__A=2E?= Prado , Yassine Oudjana , Stephen Boyd , Nicolas Frattaroli Cc: kernel@collabora.com, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: Re: [PATCH RESEND v3 1/5] clk: Respect CLK_OPS_PARENT_ENABLE during recalc Date: Wed, 28 Jan 2026 15:55:27 +0100 Message-ID: <2403222.ElGaqSPkdT@steina-w> Organization: TQ-Systems GmbH In-Reply-To: <5791016.31r3eYUQgx@workhorse> References: <20251215-mtk-pll-rpm-v3-0-5afb3191e869@collabora.com> <6239343.lOV4Wx5bFT@steina-w> <5791016.31r3eYUQgx@workhorse> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; 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Januar 2026, 15:11:33 CET schrieb Nicolas Frattaroli: > On Tuesday, 27 January 2026 15:55:29 Central European Standard Time Alexa= nder Stein wrote: > > Hello, > >=20 > > Am Freitag, 23. Januar 2026, 02:45:33 CET schrieb Stephen Boyd: > > > Quoting Nicolas Frattaroli (2025-12-15 03:23:58) > > > > When CLK_OPS_PARENT_ENABLE was introduced, it guarded various clock > > > > operations, such as setting the rate or switching parents. However, > > > > another operation that can and often does touch actual hardware sta= te is > > > > recalc_rate, which may also be affected by such a dependency. > > > >=20 > > > > Add parent enables/disables where the recalc_rate op is called dire= ctly. > > > >=20 > > > > Fixes: fc8726a2c021 ("clk: core: support clocks which requires pare= nts enable (part 2)") > > > > Fixes: a4b3518d146f ("clk: core: support clocks which requires pare= nts enable (part 1)") > > > > Reviewed-by: AngeloGioacchino Del Regno > > > > Reviewed-by: Chen-Yu Tsai > > > > Signed-off-by: Nicolas Frattaroli > > > > --- > > >=20 > > > Applied to clk-next > >=20 > > Unfortunately this breaks my board TQMa8MPxL+MBa8MPxL on next-20260126. > > Last lines on bootlog (earlycon is necessary) > > > [ 1.175639] Initialise system trusted keyrings > > > [ 1.178907] workingset: timestamp_bits=3D42 max_order=3D19 bucket_= order=3D0 > > > [ 1.185822] NFS: Registering the id_resolver key type > > > [ 1.190295] Key type id_resolver registered > > > [ 1.194473] Key type id_legacy registered > > > [ 1.198515] nfs4filelayout_init: NFSv4 File Layout Driver Register= ing... > > > [ 1.205235] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver > > > Registering... [ 1.213235] cryptd: max_cpu_qlen set to 1000 > > > [ 1.274689] Key type asymmetric registered > > > [ 1.275939] Asymmetric key parser 'x509' registered > > > [ 1.280896] Block layer SCSI generic (bsg) driver version 0.4 load= ed > > > (major 242) [ 1.288278] io scheduler mq-deadline registered > > > [ 1.292840] io scheduler kyber registered > > > [ 1.299245] ledtrig-cpu: registered to indicate activity on CPUs > >=20 > > Reverting commit 669917676e93fca5ea3c66fc9539830312bec58e fixes the pro= blem. >=20 > Hi Alexander, >=20 > sorry for breaking -next. >=20 > Can you try the following patch to print which clock+parent is causing > the hang on your platform? >=20 > --- > diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c > index 1b0f9d567f48..fa1443517768 100644 > --- a/drivers/clk/clk.c > +++ b/drivers/clk/clk.c > @@ -1921,13 +1921,21 @@ static unsigned long clk_recalc(struct clk_core *= core, > unsigned long rate =3D parent_rate; > =20 > if (core->ops->recalc_rate && !clk_pm_runtime_get(core)) { > - if (core->flags & CLK_OPS_PARENT_ENABLE) > + if (core->flags & CLK_OPS_PARENT_ENABLE) { > + pr_info("%s: enabling parent %s for %s\n", __func__, > + core->parent ? core->parent->name : "(null)", > + core->name); > clk_core_prepare_enable(core->parent); > + } > =20 > rate =3D core->ops->recalc_rate(core->hw, parent_rate); > =20 > - if (core->flags & CLK_OPS_PARENT_ENABLE) > + if (core->flags & CLK_OPS_PARENT_ENABLE) { > + pr_info("%s: disabling parent %s for %s\n", __func__, > + core->parent ? core->parent->name : "(null)", > + core->name); > clk_core_disable_unprepare(core->parent); > + } > =20 > clk_pm_runtime_put(core); > } > @@ -4038,8 +4046,12 @@ static int __clk_core_init(struct clk_core *core) > */ > clk_core_update_duty_cycle_nolock(core); > =20 > - if (core->flags & CLK_OPS_PARENT_ENABLE) > + if (core->flags & CLK_OPS_PARENT_ENABLE) { > + pr_info("%s: enabling parent %s for %s\n", __func__, > + core->parent ? core->parent->name : "(null)", > + core->name); > clk_core_prepare_enable(core->parent); > + } > =20 > /* > * Set clk's rate. The preferred method is to use .recalc_rate. For > @@ -4056,8 +4068,12 @@ static int __clk_core_init(struct clk_core *core) > rate =3D 0; > core->rate =3D core->req_rate =3D rate; > =20 > - if (core->flags & CLK_OPS_PARENT_ENABLE) > + if (core->flags & CLK_OPS_PARENT_ENABLE) { > + pr_info("%s: disabling parent %s for %s\n", __func__, > + core->parent ? core->parent->name : "(null)", > + core->name); > clk_core_disable_unprepare(core->parent); > + } > =20 > /* > * Enable CLK_IS_CRITICAL clocks so newly added critical clocks > --- >=20 > Thanks for reporting this. thanks for the debugging patch. I'll respond to the other thread where Mark is active as well. Best regards, Alexander > Kind regards, > Nicolas Frattaroli >=20 > >=20 > > Best regards, > > Alexander > >=20 >=20 >=20 >=20 >=20 >=20 >=20 =2D-=20 TQ-Systems GmbH | M=FChlstra=DFe 2, Gut Delling | 82229 Seefeld, Germany Amtsgericht M=FCnchen, HRB 105018 Gesch=E4ftsf=FChrer: Detlef Schneider, R=FCdiger Stahl, Stefan Schneider http://www.tq-group.com/