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[83.9.29.190]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ae353ca20f3sm903250666b.175.2025.07.01.08.19.18 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 01 Jul 2025 08:19:20 -0700 (PDT) Message-ID: <24e4241e-d8a1-41c7-b0f3-3ec01b4375ae@oss.qualcomm.com> Date: Tue, 1 Jul 2025 17:19:17 +0200 Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 00/10] Add clock drivers for SM7635 To: Luca Weiss , Dmitry Baryshkov Cc: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20250625-sm7635-clocks-v1-0-ca3120e3a80e@fairphone.com> <68056b4a-b1c3-401f-8720-8e0c3cda6249@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzAxMDEwMiBTYWx0ZWRfX3tlxQDf4JOXB EA29E/x78FWRufhnd8WiXGdJl/iSnGqZNVtHQGwgg3EnoqVwS84fO+MkU0mSPyoi/1gsb+rc7sG PUu1eLXqMBLCW9NzWwzNZsIrlCOgR2LNlTa53lJTbx5jGkWIsRhdQ/Zuk6SJjSHXP8Q84t8u3d0 kJGjcZrV1curdiTviLcx02zHFstL9lhE1sdtvlk+iLPZwJkjBI33TQOf0VrrJNHqWjaaj6pR/f2 nJj5jVibA+qY2J7Ghj8+VYorPenyhQpgfEH+eX/gXa7RobSSknpwOWcy63GqA3JL9/gEQHsycIO n/KW/Vn6X2x1YbwQwBerHGIVmZKNHWCYF4u5DhfbOvwfN9otgq+WljESU9ciazhgnQxH/B5re47 6BRpIhlFc0xKdi51qiMUtwauiCwnKz/ObP3joANZrXvkeh7XNT6bQlup4xbaht000K8tcBsx X-Authority-Analysis: v=2.4 cv=Y8L4sgeN c=1 sm=1 tr=0 ts=6863fc7b cx=c_pps a=hnmNkyzTK/kJ09Xio7VxxA==:117 a=fKQzr7EGRj+VoE0XNsDNvQ==:17 a=IkcTkHD0fZMA:10 a=Wb1JkmetP80A:10 a=VwQbUJbxAAAA:8 a=6H0WHjuAAAAA:8 a=IgS4KiuvraTEoa23li4A:9 a=QEXdDO2ut3YA:10 a=PEH46H7Ffwr30OY-TuGO:22 a=Soq9LBFxuPC4vsCAQt-j:22 X-Proofpoint-GUID: kQPLq3dH-UytvF03jNp1s5nw0cUdPOfY X-Proofpoint-ORIG-GUID: kQPLq3dH-UytvF03jNp1s5nw0cUdPOfY X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.7,FMLib:17.12.80.40 definitions=2025-07-01_02,2025-06-27_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 clxscore=1015 priorityscore=1501 mlxlogscore=815 lowpriorityscore=0 impostorscore=0 malwarescore=0 bulkscore=0 phishscore=0 mlxscore=0 spamscore=0 suspectscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507010102 On 01-Jul-25 15:42, Luca Weiss wrote: > On Tue Jul 1, 2025 at 1:16 PM CEST, Dmitry Baryshkov wrote: >> On Mon, Jun 30, 2025 at 10:01:35AM +0200, Luca Weiss wrote: >>> Hi Konrad, >>> >>> On Fri Jun 27, 2025 at 5:14 PM CEST, Luca Weiss wrote: >>>> On Fri Jun 27, 2025 at 5:10 PM CEST, Konrad Dybcio wrote: >>>>> On 6/25/25 11:12 AM, Luca Weiss wrote: >>>>>> Document and add the clock drivers for GCC, CAMCC, DISPCC, GPUCC and >>>>>> VIDEOCC on the SM7635 SoC. >>>>>> >>>>>> Signed-off-by: Luca Weiss >>>>>> --- >>>>>> Luca Weiss (10): >>>>>> dt-bindings: clock: qcom: document the SM7635 Global Clock Controller >>>>>> clk: qcom: Add Global Clock controller (GCC) driver for SM7635 >>>>>> dt-bindings: clock: qcom: document the SM7635 Camera Clock Controller >>>>>> clk: qcom: Add Camera Clock controller (CAMCC) driver for SM7635 >>>>>> dt-bindings: clock: qcom: document the SM7635 Display Clock Controller >>>>>> clk: qcom: Add Display Clock controller (DISPCC) driver for SM7635 >>>>>> dt-bindings: clock: qcom: document the SM7635 GPU Clock Controller >>>>>> clk: qcom: Add Graphics Clock controller (GPUCC) driver for SM7635 >>>>>> dt-bindings: clock: qcom: document the SM7635 Video Clock Controller >>>>>> clk: qcom: Add Video Clock controller (VIDEOCC) driver for SM7635 >>>>> >>>>> We had a massive yak shaving patchset go in this season, please move >>>>> the magic settings in .probe to qcom_cc_driver_data {} >>>> >>>> Okay cool, I found them >>>> https://lore.kernel.org/linux-arm-msm/174970084192.547582.612305407582982706.b4-ty@kernel.org/ >>> >>> For camcc, gpucc and videocc it seems quite simple to follow these >>> changes. >>> >>> For dispcc I don't know what to do with this line. >>> >>> /* Enable clock gating for MDP clocks */ >>> regmap_update_bits(regmap, DISP_CC_MISC_CMD, 0x10, 0x10); >> >> Use clk_regs_configure() callback to set this bit. > > Got it, found an example on the lists. > >> >>> >>> Do I just keep the regmap references in this probe function and just >>> move the clk_lucid_ole_pll_configure & qcom_branch_set_clk_en to the >>> config struct? >>> >>> And similar for gcc, I can move the qcom_branch_set_clk_en calls there >>> but the qcom_cc_register_rcg_dfs needs to be kept. >> >> Would you mind extnding struct qcom_cc_desc with args to call >> qcom_cc_register_rcg_dfs() and call it from qcom_cc_really_probe()? > > Something like this? Not quite sure when (in what order) this should be > called, is that place fine? > > I'd include a patch then in the v2 of this series. > > diff --git a/drivers/clk/qcom/common.c b/drivers/clk/qcom/common.c > index b3838d885db2..d53f290c6121 100644 > --- a/drivers/clk/qcom/common.c > +++ b/drivers/clk/qcom/common.c > @@ -390,6 +390,14 @@ int qcom_cc_really_probe(struct device *dev, > goto put_rpm; > } > > + if (desc->dfs_rcgs && desc->num_dfs_rcgs) { > + ret = qcom_cc_register_rcg_dfs(regmap, > + desc->dfs_rcgs, > + desc->num_dfs_rcgs); > + if (ret) > + goto put_rpm; > + } These were previously registered a bit earlier, but this should be good as well Konrad