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Wed, 30 Oct 2024 05:55:08 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA04.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 49U5t7io027161 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 30 Oct 2024 05:55:08 GMT Received: from [10.239.29.179] (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 29 Oct 2024 22:55:02 -0700 Message-ID: <250bce05-a095-4eb3-a445-70bbf4366526@quicinc.com> Date: Wed, 30 Oct 2024 13:54:59 +0800 Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v7 6/7] PCI: qcom: Disable ASPM L0s and remove BDF2SID mapping config for X1E80100 SoC From: Qiang Yu To: Johan Hovold CC: , , , , , , , , , , , , , , , , , , , , , , , , References: <20241017030412.265000-1-quic_qianyu@quicinc.com> <20241017030412.265000-7-quic_qianyu@quicinc.com> <91395c5e-22a0-4117-a4b5-4985284289ab@quicinc.com> Content-Language: en-US In-Reply-To: <91395c5e-22a0-4117-a4b5-4985284289ab@quicinc.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 6otyPrzF45iN6J6U6RMBnPJR0HbuqtmZ X-Proofpoint-ORIG-GUID: 6otyPrzF45iN6J6U6RMBnPJR0HbuqtmZ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 bulkscore=0 adultscore=0 mlxscore=0 priorityscore=1501 mlxlogscore=659 impostorscore=0 lowpriorityscore=0 malwarescore=0 clxscore=1015 spamscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410300045 On 10/24/2024 2:42 PM, Qiang Yu wrote: > > On 10/18/2024 10:06 PM, Johan Hovold wrote: >> Please use a more concise subject (e.g. try to stay within 72 chars) >> than: >> >>     PCI: qcom: Disable ASPM L0s and remove BDF2SID mapping config for >> X1E80100 SoC >> >> Here you could drop "SoC", maybe "ASPM" and "config" for example. >> >> On Wed, Oct 16, 2024 at 08:04:11PM -0700, Qiang Yu wrote: >>> Currently, the cfg_1_9_0 which is being used for X1E80100 has >>> config_sid >>> callback in its ops and doesn't disable ASPM L0s. However, as same as >>> SC8280X, PCIe controllers on X1E80100 are connected to SMMUv3, hence >>> don't >>> need config_sid() callback and hardware team has recommended to disable >>> L0s as it is broken in the controller. Hence reuse cfg_sc8280xp for >>> X1E80100. >> Since the x1e80100 dtsi, like sc8280xp, do not specify an iommu-map, >> that bit is effectively just a cleanup and all this patch does is to >> disable L0s. >> >> Please rephrase to make this clear. This will also allow you to make the >> Subject even shorter (no need to mention the SID bit in Subject). >> >> Also say something about how L0s is broken so that it is more clear what >> the effect of this patch is. On sc8280xp enabling L0s lead to >> correctable errors for example. > Need more time to confirm the exact reason about disabling L0s. > Will update if get any progress Hi Johan Hovold I confirmed with HW team and SW team. L0s is not supported on X1E80100, it is not fully verified. So we don't want to enable it. Thanks, Qiang Yu > > Thanks, > Qiang >> >>> Fixes: 6d0c39324c5f ("PCI: qcom: Add X1E80100 PCIe support") >>> Cc: stable@vger.kernel.org >> Johan