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Mon, 19 Jan 2026 10:21:41 -0800 (PST) Message-ID: <2649d775-e33d-439b-af52-8bcddb9823c4@tuxon.dev> Date: Mon, 19 Jan 2026 20:21:40 +0200 Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 11/16] PCI: rzg3s-host: Add PCIe Gen3 (8.0 GT/s) link speed support To: John Madieu , claudiu.beznea.uj@bp.renesas.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, geert+renesas@glider.be, krzk+dt@kernel.org Cc: robh@kernel.org, bhelgaas@google.com, conor+dt@kernel.org, magnus.damm@gmail.com, biju.das.jz@bp.renesas.com, linux-pci@vger.kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, john.madieu@gmail.com References: <20260114153337.46765-1-john.madieu.xa@bp.renesas.com> <20260114153337.46765-12-john.madieu.xa@bp.renesas.com> Content-Language: en-US From: Claudiu Beznea In-Reply-To: <20260114153337.46765-12-john.madieu.xa@bp.renesas.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 1/14/26 17:33, John Madieu wrote: > Extend the link speed configuration to support Gen3 (8.0 GT/s) in addition > to Gen2 (5.0 GT/s). This is required for RZ/G3E PCIe host support, which is > Gen3 capable. > > Instead of relying on DT max-link-speed for configuration, read the hardware > capabilities from the PCI_EXP_LNKCAP register to determine the maximum > supported speed. The DT max-link-speed property is now only used as an > optional limit when explicitly specified, which aligns with PCIe subsystem > expectations. > > Signed-off-by: John Madieu Reviewed-by: Claudiu Beznea