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([2a02:2f04:6103:4200:a4c6:4e84:e72c:19fd]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-45b66bbcf19sm66990015e9.4.2025.08.28.22.03.25 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 28 Aug 2025 22:03:29 -0700 (PDT) Message-ID: <27d76eac-6141-45db-a347-edfc3bb593d4@tuxon.dev> Date: Fri, 29 Aug 2025 08:03:24 +0300 Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 4/9] dt-bindings: PCI: renesas,r9a08g045s33-pcie: Add documentation for the PCIe IP on Renesas RZ/G3S To: Bjorn Helgaas Cc: bhelgaas@google.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, catalin.marinas@arm.com, will@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de, lizhi.hou@amd.com, linux-pci@vger.kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, Claudiu Beznea , Wolfram Sang References: <20250828193605.GA957994@bhelgaas> Content-Language: en-US From: claudiu beznea In-Reply-To: <20250828193605.GA957994@bhelgaas> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Hi, Bjorn, On 8/28/25 22:36, Bjorn Helgaas wrote: > On Thu, Aug 28, 2025 at 10:11:55PM +0300, claudiu beznea wrote: >> On 8/8/25 14:25, Claudiu Beznea wrote: >>> On 08.07.2025 19:34, Bjorn Helgaas wrote: >>>> On Fri, Jul 04, 2025 at 07:14:04PM +0300, Claudiu wrote: >>>>> From: Claudiu Beznea >>>>> >>>>> The PCIe IP available on the Renesas RZ/G3S complies with the PCI Express >>>>> Base Specification 4.0. It is designed for root complex applications and >>>>> features a single-lane (x1) implementation. Add documentation for it. >> ... > >> Renesas HW team replied to me that there are no clock, reset, or interrupt >> signals dedicated specifically to the Root Port. All these signals are >> shared across the PCIe system. >> >> Taking this and your suggestions into account, I have prepared the following >> device tree: >> >> pcie: pcie@11e40000 { >> compatible = "renesas,r9a08g045-pcie"; >> reg = <0 0x11e40000 0 0x10000>; >> ranges = <0x02000000 0 0x30000000 0 0x30000000 0 0x8000000>; >> /* Map all possible DRAM ranges (4 GB). */ >> dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0x1 0x0>; >> bus-range = <0x0 0xff>; >> interrupts = , >> , >> , >> , >> , >> , >> , >> , >> , >> , >> , >> , >> , >> , >> , >> ; >> interrupt-names = "serr", "serr_cor", "serr_nonfatal", >> "serr_fatal", "axi_err", "inta", >> "intb", "intc", "intd", "msi", >> "link_bandwidth", "pm_pme", "dma", >> "pcie_evt", "msg", "all"; >> #interrupt-cells = <1>; >> interrupt-controller; >> interrupt-map-mask = <0 0 0 7>; >> interrupt-map = <0 0 0 1 &pcie 0 0 0 0>, /* INTA */ >> <0 0 0 2 &pcie 0 0 0 1>, /* INTB */ >> <0 0 0 3 &pcie 0 0 0 2>, /* INTC */ >> <0 0 0 4 &pcie 0 0 0 3>; /* INTD */ >> clocks = <&cpg CPG_MOD R9A08G045_PCI_ACLK>, >> <&cpg CPG_MOD R9A08G045_PCI_CLKL1PM>; >> clock-names = "aclk", "pm"; >> resets = <&cpg R9A08G045_PCI_ARESETN>, >> <&cpg R9A08G045_PCI_RST_B>, >> <&cpg R9A08G045_PCI_RST_GP_B>, >> <&cpg R9A08G045_PCI_RST_PS_B>, >> <&cpg R9A08G045_PCI_RST_RSM_B>, >> <&cpg R9A08G045_PCI_RST_CFG_B>, >> <&cpg R9A08G045_PCI_RST_LOAD_B>; >> reset-names = "aresetn", "rst_b", "rst_gp_b", "rst_ps_b", >> "rst_rsm_b", "rst_cfg_b", "rst_load_b"; >> power-domains = <&cpg>; >> device_type = "pci"; >> #address-cells = <3>; >> #size-cells = <2>; >> renesas,sysc = <&sysc>; >> status = "disabled"; >> >> pcie_port0: pcie@0,0 { >> reg = <0x0 0x0 0x0 0x0 0x0>; >> ranges; >> clocks = <&versa3 5>; >> clock-names = "ref"; >> device_type = "pci"; >> vendor-id = <0x1912>; >> device-id = <0x0033>; >> bus-range = <0x1 0xff>; > > I don't think you need this bus-range. The bus range for the > hierarchy below a Root Port is discoverable and configurable via > config space. Thank you for the pointer. I'll update and send a new version. Claudiu