From: Heiko Stuebner <heiko@sntech.de>
To: Lin Huang <hl@rock-chips.com>
Cc: dbasehore@chromium.org, shawn.lin@rock-chips.com,
briannorris@chromium.org, linux-rockchip@lists.infradead.org,
dianders@chromium.org, linux-clk@vger.kernel.org
Subject: Re: [PATCH v3 2/2] arm64: dts: rockchip: assign clock rate for some cpll child clock
Date: Fri, 23 Mar 2018 09:45:22 +0100 [thread overview]
Message-ID: <2857663.tlolacRkt7@phil> (raw)
In-Reply-To: <1521511589-17844-2-git-send-email-hl@rock-chips.com>
Am Dienstag, 20. März 2018, 03:06:29 CET schrieb Lin Huang:
> These clocks do not assign default clock frequency, and use the
> default cru register value to get frequency, so if cpll increase
> frequency, these clocks also increase their frequency, that may
> exceed their signed off frequency. So assign default clock for
> them to avoid it.
>
> NOTE: on none of the boards currently in mainline do we expect
> CPLL to be anything other than 800 MHz, but some future boards
> might have it. It's still good to be explicit about the clock
> rates to make diffing against future boards easier and also to
> rely less on BIOS muxing.
>
> Change-Id: If79368aeda5c51dbf2a3b6659f17052a2ae4a401
> Signed-off-by: Lin Huang <hl@rock-chips.com>
> Reviewed-by: Douglas Anderson <dianders@chromium.org>
applied for 4.17 (but will most likely move to 4.18) with some changes:
- dropped Change-Id
- fixed duplicate assigned clocks for dp node
- grouped aclk_vio and aclk_hdcp into one line in cru nodes
- moved assigned clocks
Heiko
next prev parent reply other threads:[~2018-03-23 8:45 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-03-20 2:06 [PATCH v3 1/2] clk: rockchip: assign correct id for pclk_ddr and hclk_sd in rk3399 Lin Huang
2018-03-20 2:06 ` [PATCH v3 2/2] arm64: dts: rockchip: assign clock rate for some cpll child clock Lin Huang
2018-03-20 2:12 ` Shawn Lin
2018-03-20 2:23 ` hl
2018-03-20 7:00 ` Heiko Stübner
2018-03-23 8:45 ` Heiko Stuebner [this message]
2018-03-23 8:26 ` [PATCH v3 1/2] clk: rockchip: assign correct id for pclk_ddr and hclk_sd in rk3399 Heiko Stuebner
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