From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EA19EB67D; Tue, 1 Oct 2024 10:00:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727776835; cv=none; b=L/EcmWbhUk1tLyh/yZA92m5fgTsNXB+FmV38pSDrYtWbc1MIIx7M4j0x9AulyP62cqXTEjpdtO9rmZchadpNmButQB1VEhLmRc0fOksAcSAom/MrmCjBHM4IAVdnvCgVNcayM3h1ldedfkfQhJ/t4E3cQa9aRymzAmDOn/yje4Q= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727776835; c=relaxed/simple; bh=L18kY3Hi4NirIDL3N4HZfh4hTLuUjuq/kXl6br9Vuus=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=PJocmqni0D3nuuWqKNPs9SzLx6mV89pRy0Y9Q2WiVhmrcfpXYjhifuVXSO0sdTvuJGFOel8G1k5nndiWTaAenRdNIVxl5RE0QtCy7hqGUJ5ejmPmCiIeLf3VRWikx5Nd+yzG+4CLjtLMbaiaMyxFjqha7k4qzfHcLNCO4zYKmIs= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Cs03Zo/F; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Cs03Zo/F" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 33108C4CEC6; Tue, 1 Oct 2024 10:00:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1727776834; bh=L18kY3Hi4NirIDL3N4HZfh4hTLuUjuq/kXl6br9Vuus=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=Cs03Zo/FEqO4lAHTZKDnzIGcaqclATvBJNez8GLjHDpl7ojkgLRsOiEetGA9mZe0r b4fi7Z8czM3hOMzed0PxROamiF/d1jY52i7xt+IIWm7Gl0Ybq8Kb+is8A+Hlh+HKbD OiHdmLD0xOLj1PAXqqMfThk9hz5vkHYhmhJqlVODyJ97vJ5JmjpncME5YjW0oEm+Sn +TqCYhXFLgeja8TvPmJVuapiwXgwQkq4GnBKd59xBliCPvYugUdmRxayIsaccOfPr7 ljk+OhI1LS0qJNKQTjgbSrn82WxKNGRt5At7Fap3Js5l+To/E90s7vEIk6e5iW/uD2 XrI2cAF4bmE7A== Message-ID: <2b3566dd-71ac-4ef7-abdc-524277879aa6@kernel.org> Date: Tue, 1 Oct 2024 12:00:27 +0200 Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] clk: samsung: fsd: Mark PLL_CAM_CSI as critical To: Inbaraj E , 'Stephen Boyd' , alim.akhtar@samsung.com, cw00.choi@samsung.com, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, mturquette@baylibre.com, s.nawrocki@samsung.com Cc: pankaj.dubey@samsung.com, gost.dev@samsung.com References: <20240917101016.23238-1-inbaraj.e@samsung.com> <0d43a00985a815c1869ebc6c441a2aed.sboyd@kernel.org> <00f001db0a87$cd9ddfa0$68d99ee0$@samsung.com> <633ff284-101d-4651-833e-a6b01626c9a1@kernel.org> <011401db0b13$cbd045f0$6370d1d0$@samsung.com> <1c6c56f7-bdda-4e14-9910-80e0cda0d631@kernel.org> <03ca01db13e3$bc12e360$3438aa20$@samsung.com> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 01/10/2024 11:24, Inbaraj E wrote: >>>>>>>> CSI stop streaming through pm_runtime_put system is getting >> halted. >>>>>>>> So marking PLL_CAM_CSI as critical to prevent disabling. >>>>>>>> >>>>>>>> Signed-off-by: Inbaraj E >>>>>>>> --- >>>>>>> >>>>>>> Please add a fixes tag. Although this is likely a band-aid fix >>>>>>> because marking something critical leaves it enabled forever. >>>>>> >>>>>> Sure, will add fixes tag. As per HW manual, this PLL_CAM_CSI is >>>>>> supplying clock even for CMU SFR access of CSI block, so we can't >>>>>> gate this. >>>>> >>>>> Hm, I am not so sure. The CMU driver should just take appropriate clock. >>>>> Sprinkling CLK_CRITICAL looks as substitute of missing clock >>>>> handling/ >>>> >>>> As per HW design, PLL_CAM_CSI is responsible for suppling clock to >>>> CSI SFR, CMU SFR and some internal block of CAM_CSI. In this some of >>>> the clock is not handled by any driver but it is required for CSI to >>>> work properly. For example CSI NOC clock. So this is the reason we are >> marking PLL_CAM_CSI as critical. >>>> >>> >>> This is clock hierarchy for CMU_CAM_CSI block. >>> >>> PLL_CAM_CSI -----> DIVIDER --------> CSI_SFR clock >>> | >>> |----> DIVIDER --------> CMU_SFR clock >>> | >>> |----> DIVIDER --------> CSI NOC clock. >>> >> >> And what is the problem in adding proper handling in the driver? You just >> described case valid for 99% of SoC components. > > Hi Kryzstof, > > Sorry, but it seems I was not able to explain the issue. Let me add more > details: > So for CSI IP we have two clocks as ACLK and PCLK which needs to be > handled by the driver during start and stop streaming. > > In BLK_CSI we have CSI IP along with other bunch supporting modules such > as CMU_CSI, NOC_CSI, CSI_SFR. For all these components of BLK_CSI we have > a single top level parent PLL clock as PLL_CAM_CSI. > > Now if we look into CSI driver perspective it needs only ACLK and PCLK > clocks for it's operations. But to access CMU SFRs (including ACLK/PCLK > or any other CMU SFR of BLK_CSI) we need parent clock keep supplying > clocks. While we try to gate ACLK clock, due to propagation logic of clock > gating the CCF scans all the clocks from leaf level to the parent clock > and tries to gate clocks if enable/disable ops is valid for any such > clock. > > Issue here is that we are trying to gate PLL_CAM_CSI which itself is > accessible only when this clock is enabled. In fact none of CMU_SFR will > be accessible as soon as PLL_CAM_CSI is gated. CSI driver is not intended Obviously, but your CMU is taking the necessary clock and enabled it so what is the problem? > to gate this PLL clock but only the leaf level clock which is supplying to > CSI IP. So in absence of any alternate source of clock hierarchy which > can supply clock for CMU_CSI we can't gate PLL_CAM_CSI. > > Please let us know if you have any other queries why we are insisting on > marking PLL_CAM_CSI as CRITICAL clock. This is so far quite obvious - just like in all other cases, you need the top clock taken by proper driver. I don't think you are looking at right drivers and right problem here. Best regards, Krzysztof