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Wed, 03 Apr 2024 10:49:32 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 433AnNUd006151 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 3 Apr 2024 10:49:23 GMT Received: from [10.218.10.146] (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Wed, 3 Apr 2024 03:49:18 -0700 Message-ID: <2e70f208-5a8e-3feb-d484-23b78c70d08f@quicinc.com> Date: Wed, 3 Apr 2024 16:19:14 +0530 Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.11.2 Subject: Re: [PATCH 7/7] clk: qcom: Add GPUCC driver support for SM4450 To: Dmitry Baryshkov CC: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Vinod Koul , Vladimir Zapolskiy , , , , Taniya Das , Jagadeesh Kona , Imran Shaik , Satya Priya Kakitapalli References: <20240330182817.3272224-1-quic_ajipan@quicinc.com> <20240330182817.3272224-8-quic_ajipan@quicinc.com> <9106b0eb-e15d-f2fa-d681-4017412c4a76@quicinc.com> Content-Language: en-US From: Ajit Pandey In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: JKcuvSykRRqScDu95eStN6zVVCh2_z2h X-Proofpoint-ORIG-GUID: JKcuvSykRRqScDu95eStN6zVVCh2_z2h X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-04-03_10,2024-04-01_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 bulkscore=0 clxscore=1015 suspectscore=0 mlxlogscore=999 adultscore=0 priorityscore=1501 spamscore=0 mlxscore=0 lowpriorityscore=0 phishscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2403210001 definitions=main-2404030075 On 4/3/2024 12:53 AM, Dmitry Baryshkov wrote: > On Tue, 2 Apr 2024 at 21:26, Ajit Pandey wrote: >> >> >> >> On 3/31/2024 7:09 AM, Dmitry Baryshkov wrote: >>> On Sat, 30 Mar 2024 at 20:30, Ajit Pandey wrote: >>>> >>>> Add Graphics Clock Controller (GPUCC) support for SM4450 platform. >>>> >>>> Signed-off-by: Ajit Pandey >>>> --- >>>> drivers/clk/qcom/Kconfig | 9 + >>>> drivers/clk/qcom/Makefile | 1 + >>>> drivers/clk/qcom/gpucc-sm4450.c | 806 ++++++++++++++++++++++++++++++++ >>>> 3 files changed, 816 insertions(+) >>>> create mode 100644 drivers/clk/qcom/gpucc-sm4450.c >>>> >>> >>> [skipped] >>> >>>> +static int gpu_cc_sm4450_probe(struct platform_device *pdev) >>>> +{ >>>> + struct regmap *regmap; >>>> + >>>> + regmap = qcom_cc_map(pdev, &gpu_cc_sm4450_desc); >>>> + if (IS_ERR(regmap)) >>>> + return PTR_ERR(regmap); >>>> + >>>> + clk_lucid_evo_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config); >>>> + clk_lucid_evo_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config); >>>> + >>>> + /* Keep some clocks always enabled */ >>>> + qcom_branch_set_clk_en(regmap, 0x93a4); /* GPU_CC_CB_CLK */ >>>> + qcom_branch_set_clk_en(regmap, 0x9004); /* GPU_CC_CXO_AON_CLK */ >>>> + qcom_branch_set_clk_en(regmap, 0x900c); /* GPU_CC_DEMET_CLK */ >>> >>> Why? At least other drivers model these three clocks properly. >>> >> These clocks are POR on in SM4450 and required to be kept always enabled >> for GPU functionality hence keep them enabled from probe only. > > Please, check how this is handled on the other platforms, please. > Hint: `git grep GPU_CC_DEMET_CLK` > yeah these clocks are modeled and handled via always enabled clk ops (clk_branch2_aon_ops) in few other platforms like SM8450, SM8650 which also do same functionality and keep them in always enabled POR state, while we kept them enabled from GPUCC probe in SM8550. Since we need such clock to be always enabled irrespective of consumer votes I guess modeling with aon_ops isn't really required and we can simply keep them enabled in probe similar to other always on clocks. >> >>>> + >>>> + return qcom_cc_really_probe(pdev, &gpu_cc_sm4450_desc, regmap); >>>> +} >>>> + >>>> +static struct platform_driver gpu_cc_sm4450_driver = { >>>> + .probe = gpu_cc_sm4450_probe, >>>> + .driver = { >>>> + .name = "gpucc-sm4450", >>>> + .of_match_table = gpu_cc_sm4450_match_table, >>>> + }, >>>> +}; >>>> + >>>> +module_platform_driver(gpu_cc_sm4450_driver); >>>> + >>>> +MODULE_DESCRIPTION("QTI GPUCC SM4450 Driver"); >>>> +MODULE_LICENSE("GPL"); >>>> -- >>>> 2.25.1 >>>> >>>> >>> >>> >> >> -- >> Thanks, and Regards >> Ajit > > > -- Thanks, and Regards Ajit