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Fri, 17 Jul 2026 02:30:22 -0700 (PDT) X-Received: by 2002:a17:903:3c46:b0:2c9:97a8:afef with SMTP id d9443c01a7336-2cf349f4a51mr17752525ad.40.1784280621313; Fri, 17 Jul 2026 02:30:21 -0700 (PDT) Received: from [10.217.216.90] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2cf344f4481sm7415285ad.32.2026.07.17.02.30.13 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 17 Jul 2026 02:30:20 -0700 (PDT) Message-ID: <2e9a211d-a877-419a-ba8d-40bfc42e65ef@oss.qualcomm.com> Date: Fri, 17 Jul 2026 15:00:11 +0530 Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 1/3] dt-bindings: clock: qcom: glymur-gcc: Add missing CX power domain To: Bjorn Andersson Cc: Abel Vesa , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Maulik Shah , Dmitry Baryshkov , Jyothi Kumar Seerapu , Konrad Dybcio , Brian Masney , Krzysztof Kozlowski , Sibi Sankar , Pankaj Patil , Akhil P Oommen , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jishnu Prakash , Raviteja Laggyshetty , Kamal Wadhwa , Qiang Yu , Manaf Meethalavalappu Pallikunhi , Abel Vesa References: <20260715-glymur-fix-gcc-cx-scaling-v3-0-72eb5adad156@oss.qualcomm.com> <20260715-glymur-fix-gcc-cx-scaling-v3-1-72eb5adad156@oss.qualcomm.com> <4b543abe-2482-4381-b41e-623cdf5be9a2@oss.qualcomm.com> <316fd37b-9936-4bca-8521-9a11ee65cbd6@oss.qualcomm.com> Content-Language: en-US From: Taniya Das In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Info: AW1haW4tMjYwNzE3MDA5NCBTYWx0ZWRfX/z1UzYbYfFYK D4oxbWbQnfV4s5CpmTBWKeBTBdgNhfmhIJaXiCR7mg7aqAuieIsNZj8MgobJiA0LnRcUmki2GDz fwygd0xdYFzJQJN7X1fBlZeseqRlj68= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzE3MDA5NCBTYWx0ZWRfXz9wEKkEYLTV7 ZObxhusl6Ubg4xso7fmPDZqvjBi8Ox1fJvbf249seT6whE4Pery2ZdRGmenfi4VFt1IYce4eqFU yT4czWv1KujE6JE/jN2PPnnMLHpu2hsrS4X2LpnXGObfJ6gq1KLo/bDQlCmhyciT3TeZVSJcS0A mc5EhI1TRswQyAUzYHtDsGCkvNeWVm8ZQ9X6Bn6whurCj+400ikEYef2I8nXL30WzxHXppXzqJc jV2ieU4cW7w+pY8zMxJVLF5C0VUglZ/SQw1A3bXukiaW32HMCRErpInCJ3OFY3wiAvfQ/w+Gc/5 W2h5LkkVY3DeKlZwjUdpUFmyCvfRA2XA41ZtLw4ezFbBSc/KGnmjC1YbpoeFD+Uk9Oi2LbUALSt XgDxjN2ZwisAh07hISgvNOM/hWXhxZyk8wxQyxWTb2dkInvyyKDDEYYBNnjRhgjOlBkOwU5nPGP +9LACvVYY/IjCh9buAA== X-Proofpoint-GUID: LEbhK8JDAu_DWMuKa0cgvRwGz4umGS8q X-Proofpoint-ORIG-GUID: LEbhK8JDAu_DWMuKa0cgvRwGz4umGS8q X-Authority-Analysis: v=2.4 cv=e/M2j6p/ c=1 sm=1 tr=0 ts=6a59f62f cx=c_pps a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=EUspDBNiAAAA:8 a=ZdHkocIOR6SBK6D-yKIA:9 a=QEXdDO2ut3YA:10 a=GvdueXVYPmCkWapjIL-Q:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-17_02,2026-07-15_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 impostorscore=0 suspectscore=0 phishscore=0 priorityscore=1501 spamscore=0 malwarescore=0 clxscore=1015 lowpriorityscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607170094 On 7/17/2026 6:45 AM, Bjorn Andersson wrote: > On Thu, Jul 16, 2026 at 04:42:11PM +0530, Taniya Das wrote: >> >> >> On 7/16/2026 12:52 PM, Abel Vesa wrote: >>> On 26-07-16 10:13:48, Taniya Das wrote: >>>> >>>> >>>> On 7/15/2026 6:59 PM, Abel Vesa wrote: >>>>> The GDSCs provided by the Glymur GCC are supplied by the RPMh CX power >>>>> domain. Model that parent domain in the GCC binding so the provider can >>>>> describe the dependency in devicetree. >>>>> >>>>> Add a single CX power-domain entry to the binding and make it required, >>>>> matching the hardware description needed by the GCC node. >>>>> >>>>> Fixes: ee2d967030fe ("dt-bindings: clock: qcom: document the Glymur Global Clock Controller") >>>>> Signed-off-by: Abel Vesa >>>>> --- >>>>> Documentation/devicetree/bindings/clock/qcom,glymur-gcc.yaml | 8 ++++++++ >>>>> 1 file changed, 8 insertions(+) >>>> >>>> >>>> Abel, I feel we should add the 'required-opps' as well which will ensure >>>> the clock controllers minimum voltage requirement. >>> >>> But it was agreed in v1 that we should not add the required-opps. So we >>> dropped it in v2. >>> >> >> Okay, sorry, may be I missed that comment. >> >> >>> Can you give more details to why you think it is needed ? >> >> My reasoning is that if a clock controller requires a rail, it is >> preferable to explicitly specify the required operating level rather >> than rely on system/client vote. This makes the dependency >> self-contained and easier to reason about. Clients that require a higher >> operating level than the clock controller's minimum requirement remain >> free to vote for a higher level as needed. >> > > You're expressing this in generic terms, can you please provide the > concrete example of what this would look for in the Glymur GCC case? > Yes, Bjorn, this is indeed a general requirement for a clock controller. In Glymur I do see that CX could drop to retention corner in case there is no vote from any subsystem and so it is better to vote from clock controller a level above retention using the required-opps. > What is the required-opps for the Glymur GCC? LOW_SVS(rpmhpd_opp_low_svs) corner should be good for GCC controller. -- Thanks, Taniya Das