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Wed, 26 Jun 2024 14:39:35 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA03.qualcomm.com (8.17.1.19/8.17.1.19) with ESMTPS id 45QEdX4O020731 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 26 Jun 2024 14:39:33 GMT Received: from [10.50.52.175] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 26 Jun 2024 07:39:24 -0700 Message-ID: <302298ef-7827-49e1-8b0f-04467cb38ad7@quicinc.com> Date: Wed, 26 Jun 2024 20:09:15 +0530 Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH V4 5/7] clk: qcom: Add NSS clock Controller driver for IPQ9574 To: Andrew Lunn CC: , , , , , , , , , , , , , , , , , , , , , , , References: <20240625070536.3043630-1-quic_devipriy@quicinc.com> <20240625070536.3043630-6-quic_devipriy@quicinc.com> Content-Language: en-US From: Devi Priya In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: A22KNXbNeEJN8TyLa0AY4ccsaLyiPzaX X-Proofpoint-GUID: A22KNXbNeEJN8TyLa0AY4ccsaLyiPzaX X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-06-26_07,2024-06-25_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 mlxlogscore=841 adultscore=0 bulkscore=0 lowpriorityscore=0 impostorscore=0 malwarescore=0 mlxscore=0 suspectscore=0 priorityscore=1501 clxscore=1011 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2406140001 definitions=main-2406260107 On 6/25/2024 8:09 PM, Andrew Lunn wrote: >> +static struct clk_alpha_pll ubi32_pll_main = { >> + .offset = 0x28000, >> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_NSS_HUAYRA], >> + .flags = SUPPORTS_DYNAMIC_UPDATE, >> + .clkr = { >> + .hw.init = &(const struct clk_init_data) { >> + .name = "ubi32_pll_main", >> + .parent_data = &(const struct clk_parent_data) { >> + .index = DT_XO, >> + }, >> + .num_parents = 1, >> + .ops = &clk_alpha_pll_huayra_ops, >> + }, >> + }, >> +}; >> + >> +static struct clk_alpha_pll_postdiv ubi32_pll = { >> + .offset = 0x28000, >> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_NSS_HUAYRA], >> + .width = 2, >> + .clkr.hw.init = &(const struct clk_init_data) { >> + .name = "ubi32_pll", >> + .parent_hws = (const struct clk_hw *[]) { >> + &ubi32_pll_main.clkr.hw >> + }, >> + .num_parents = 1, >> + .ops = &clk_alpha_pll_postdiv_ro_ops, >> + .flags = CLK_SET_RATE_PARENT, >> + }, >> +}; > > Can these structures be made const? You have quite a few different > structures in this driver, some of which are const, and some which are > not. > Sure, will check and update this in V6 Thanks, Devi Priya > Andrew >