From: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
To: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Cc: Bjorn Andersson <andersson@kernel.org>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
Brian Masney <bmasney@redhat.com>, Val Packett <val@packett.cool>,
Marek Szyprowski <m.szyprowski@samsung.com>,
linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org
Subject: Re: [PATCH] Revert "clk: qcom: dispcc-sm8250: Enable parents for pixel clocks"
Date: Mon, 20 Jul 2026 21:21:03 +0300 [thread overview]
Message-ID: <31d1ac01-ccd2-4abc-9828-be120f095de4@linaro.org> (raw)
In-Reply-To: <bjgad2qs6pt2cn5pr353qaelxa3gtpaqfoxjnrwfhwbty4g75f@ngu4ddk5jeyf>
On 7/20/26 18:00, Dmitry Baryshkov wrote:
> On Wed, Jul 01, 2026 at 03:11:47AM +0300, Vladimir Zapolskiy wrote:
>> This reverts commit acf7a91d0b0e9e3ef374944021de62062125b7e4.
>>
>> The commit causes quite severe problems in runtime due to the introduced
>> cyclic clock dependency:
>>
>> * dsi@ae9400 platform device and its probe depends on dispcc clocks,
>> * the reverted commit links dispcc clocks enablement to mdss_dsiX_phy clocks,
>> * at this stage DSI PHY PLL cannot be locked to complete driver initialization,
>> the parent clocks for DISPCC provided mdss_pclkX clocks can not be enabled.
>>
>> On RB5 board with no connected display panel on boot I get this error report:
>>
>> DSI PLL(0) lock failed, status=0x00000000
>> PLL(0) lock failed
>
> Why can't it be locked at this stage? Is it underpowered? Or is the code
> trying to lock it on some random, unsupported value?
Since there is no display panel attached, I believe DSI PLL clocks should
not be enabled at all, however the reverted commit requires it to happen.
I don't have a panel for RB5 to test, if the PLL clocks can be locked or
not, when there is an attached panel.
In general I believe the problem is plainly related to the established
cyclic dependency as it's stated above, and in any case the reverted
commit is a clear regression for RB5 board with no panel.
>> dsi0_phy_pll_out_dsiclk already disabled
>> WARNING: drivers/clk/clk.c:1188 at clk_core_disable+0xa4/0xac, CPU#4: kworker/u32:1/61
>> ...
>> dsi0_phy_pll_out_dsiclk already unprepared
>> WARNING: drivers/clk/clk.c:1047 at clk_core_unprepare+0xe4/0x104, CPU#4: kworker/u32:1/61
>> ...
>> Tainted: [W]=WARN
>>
>> The problem has been already reported and discussed before [1], the original
>> commit was done for "preventing potential stability issues" reason, and this
>> time fixing a potential issue introduced the actual one unfortunately.
>>
>> [1] https://lore.kernel.org/linux-arm-msm/2f5b98a4-80a6-4611-9615-ab0202a8c455@samsung.com/
>>
>> Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
>> ---
>> drivers/clk/qcom/dispcc-sm8250.c | 4 ++--
>> 1 file changed, 2 insertions(+), 2 deletions(-)
>>
--
Best wishes,
Vladimir
next prev parent reply other threads:[~2026-07-20 18:21 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-01 0:11 [PATCH] Revert "clk: qcom: dispcc-sm8250: Enable parents for pixel clocks" Vladimir Zapolskiy
2026-07-20 13:09 ` Vladimir Zapolskiy
2026-07-20 15:00 ` Dmitry Baryshkov
2026-07-20 18:21 ` Vladimir Zapolskiy [this message]
2026-07-20 20:54 ` Dmitry Baryshkov
2026-07-20 22:39 ` Vladimir Zapolskiy
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