clk-renesas-pcie (9FGV0241) does not work

clk-renesas-pcie (9FGV0241) does not work

[Alexander Stein]

Hi,

CC'ing Marek as original author.

I'm trying to use the clk-renesas-pcie driver for 9FGV0241 on my board.
But apparently it doesn't work. After digging into it IMHO the i2c transfer 
are not correct.
The datasheet [1] states that for reading the following sequence applies:
1. Start
2. W slave address
3. W beginning byte
4. Repeated start
5. R slave address
6. data byte count (from slave)
7. beginning byte (from slave)
...
x. Stop

So before each read there is an additional byte containing (an apparently 
configurable) amount of bytes to be transferred. This is also what I see in u-
boot:
> => i2c md 0x6a 0 9
> 0000: 08 ff 06 ff 5f ff 01 02 08    ...._....

The first ff, here on offset 1, is actually the reset default register/byte 0.
01 02 (offsets 6 & 7) are the ID registers at byte 5 & 6.

The write access is quite similar, the amount of bytes to be written has to be 
sent first. So the data byte count is completely ignored, IMHO which is why 
this doesn't work. Am I'm missing something? How can this be fixed?

Best regards,
Alexander

[1] https://www.renesas.com/us/en/document/dst/9fgv0241-datasheet?r=37495

Re: clk-renesas-pcie (9FGV0241) does not work

[Marek Vasut]

On 8/26/22 10:50, Alexander Stein wrote:
> Hi,

Hi,

> CC'ing Marek as original author.
> 
> I'm trying to use the clk-renesas-pcie driver for 9FGV0241 on my board.
> But apparently it doesn't work. After digging into it IMHO the i2c transfer
> are not correct.
> The datasheet [1] states that for reading the following sequence applies:
> 1. Start
> 2. W slave address
> 3. W beginning byte
> 4. Repeated start
> 5. R slave address
> 6. data byte count (from slave)
> 7. beginning byte (from slave)
> ...
> x. Stop
> 
> So before each read there is an additional byte containing (an apparently
> configurable) amount of bytes to be transferred. This is also what I see in u-
> boot:
>> => i2c md 0x6a 0 9
>> 0000: 08 ff 06 ff 5f ff 01 02 08    ...._....
> 
> The first ff, here on offset 1, is actually the reset default register/byte 0.
> 01 02 (offsets 6 & 7) are the ID registers at byte 5 & 6.
> 
> The write access is quite similar, the amount of bytes to be written has to be
> sent first. So the data byte count is completely ignored, IMHO which is why
> this doesn't work. Am I'm missing something? How can this be fixed?

Can you please test the following patch?

https://patchwork.kernel.org/project/linux-clk/patch/20220910232015.216329-1-marex@denx.de/