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Mon, 19 Jan 2026 10:14:04 -0800 (PST) Message-ID: <34bd51e6-c93d-40fd-bf5a-8f476c4e1776@tuxon.dev> Date: Mon, 19 Jan 2026 20:14:02 +0200 Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 06/16] PCI: rzg3s-host: Make SYSC register offsets SoC-specific To: John Madieu , claudiu.beznea.uj@bp.renesas.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, geert+renesas@glider.be, krzk+dt@kernel.org Cc: robh@kernel.org, bhelgaas@google.com, conor+dt@kernel.org, magnus.damm@gmail.com, biju.das.jz@bp.renesas.com, linux-pci@vger.kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, john.madieu@gmail.com References: <20260114153337.46765-1-john.madieu.xa@bp.renesas.com> <20260114153337.46765-7-john.madieu.xa@bp.renesas.com> Content-Language: en-US From: Claudiu Beznea In-Reply-To: <20260114153337.46765-7-john.madieu.xa@bp.renesas.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Hi, John, On 1/14/26 17:33, John Madieu wrote: > In preparation for adding RZ/G3E support, move the RST_RSM_B register > offset and mask into a SoC-specific data structure. Compared with RZ/G3S, > the RZ/G3E SYSC controls different functionalities for the PCIe controller. > > Make SYSC operations conditional on the presence of register offset > information, allowing the driver to handle SoCs that don't use the > RST_RSM_B signal. > > Signed-off-by: John Madieu > --- > drivers/pci/controller/pcie-rzg3s-host.c | 93 +++++++++++++++++------- > 1 file changed, 67 insertions(+), 26 deletions(-) > > diff --git a/drivers/pci/controller/pcie-rzg3s-host.c b/drivers/pci/controller/pcie-rzg3s-host.c > index 205b60421be1..44728771afa3 100644 > --- a/drivers/pci/controller/pcie-rzg3s-host.c > +++ b/drivers/pci/controller/pcie-rzg3s-host.c > @@ -159,10 +159,6 @@ > > #define RZG3S_PCI_CFG_PCIEC 0x60 > > -/* System controller registers */ > -#define RZG3S_SYS_PCIE_RST_RSM_B 0xd74 > -#define RZG3S_SYS_PCIE_RST_RSM_B_MASK BIT(0) > - > /* Maximum number of windows */ > #define RZG3S_MAX_WINDOWS 8 > > @@ -174,6 +170,34 @@ > /* Timeouts experimentally determined */ > #define RZG3S_REQ_ISSUE_TIMEOUT_US 2500 > > +/** > + * struct rzg3s_sysc_function - System Controller register function descriptor > + * @offset: Register offset from the System Controller base address > + * @mask: Bit mask for the function within the register > + */ > +struct rzg3s_sysc_function { > + u32 offset; > + u32 mask; > +}; > + > +/** > + * struct rzg3s_sysc_info - RZ/G3S System Controller function info > + * @rst_rsm_b: Reset RSM_B function descriptor > + */ > +struct rzg3s_sysc_info { > + struct rzg3s_sysc_function rst_rsm_b; > +}; > + > +/** > + * struct rzg3s_sysc - RZ/G3S System Controller descriptor > + * @regmap: System controller regmap > + * @info: System controller info > + */ > +struct rzg3s_sysc { > + struct regmap *regmap; > + const struct rzg3s_sysc_info *info; > +}; > + > /** > * struct rzg3s_pcie_msi - RZ/G3S PCIe MSI data structure > * @domain: IRQ domain > @@ -203,6 +227,7 @@ struct rzg3s_pcie_host; > * power-on > * @cfg_resets: array with the resets that need to be de-asserted after > * configuration > + * @sysc_info: SYSC functionalities > * @num_power_resets: number of power resets > * @num_cfg_resets: number of configuration resets > */ > @@ -210,6 +235,7 @@ struct rzg3s_pcie_soc_data { > int (*init_phy)(struct rzg3s_pcie_host *host); > const char * const *power_resets; > const char * const *cfg_resets; > + struct rzg3s_sysc_info sysc_info; > u8 num_power_resets; > u8 num_cfg_resets; > }; > @@ -233,7 +259,7 @@ struct rzg3s_pcie_port { > * @dev: struct device > * @power_resets: reset control signals that should be set after power up > * @cfg_resets: reset control signals that should be set after configuration > - * @sysc: SYSC regmap > + * @sysc: SYSC descriptor > * @intx_domain: INTx IRQ domain > * @data: SoC specific data > * @msi: MSI data structure > @@ -248,7 +274,7 @@ struct rzg3s_pcie_host { > struct device *dev; > struct reset_control_bulk_data *power_resets; > struct reset_control_bulk_data *cfg_resets; > - struct regmap *sysc; > + struct rzg3s_sysc *sysc; > struct irq_domain *intx_domain; > const struct rzg3s_pcie_soc_data *data; > struct rzg3s_pcie_msi msi; > @@ -1516,6 +1542,7 @@ static int rzg3s_pcie_probe(struct platform_device *pdev) > struct device_node *sysc_np __free(device_node) = > of_parse_phandle(np, "renesas,sysc", 0); > struct rzg3s_pcie_host *host; > + struct rzg3s_sysc *sysc; > int ret; > > bridge = devm_pci_alloc_host_bridge(dev, sizeof(*host)); > @@ -1527,6 +1554,13 @@ static int rzg3s_pcie_probe(struct platform_device *pdev) > host->data = device_get_match_data(dev); > platform_set_drvdata(pdev, host); > > + host->sysc = devm_kzalloc(dev, sizeof(*host->sysc), GFP_KERNEL); > + if (!host->sysc) > + return -ENOMEM; > + > + sysc = host->sysc; > + sysc->info = &host->data->sysc_info; > + > host->axi = devm_platform_ioremap_resource(pdev, 0); > if (IS_ERR(host->axi)) > return PTR_ERR(host->axi); > @@ -1540,15 +1574,16 @@ static int rzg3s_pcie_probe(struct platform_device *pdev) > if (ret) > return ret; > > - host->sysc = syscon_node_to_regmap(sysc_np); > - if (IS_ERR(host->sysc)) { > - ret = PTR_ERR(host->sysc); > + sysc->regmap = syscon_node_to_regmap(sysc_np); > + if (IS_ERR(sysc->regmap)) { > + ret = PTR_ERR(sysc->regmap); > goto port_refclk_put; > } > > - ret = regmap_update_bits(host->sysc, RZG3S_SYS_PCIE_RST_RSM_B, > - RZG3S_SYS_PCIE_RST_RSM_B_MASK, > - FIELD_PREP(RZG3S_SYS_PCIE_RST_RSM_B_MASK, 1)); > + ret = regmap_update_bits(sysc->regmap, > + sysc->info->rst_rsm_b.offset, This can stay on the previous line to spare one extra line of code. The rest LGTM. Thank you, Claudiu