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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7acd3246d33sm1064594b3a.13.2025.11.03.19.35.54 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 03 Nov 2025 19:35:58 -0800 (PST) Message-ID: <359f88fb-a207-499f-aad0-e12ea3da222b@oss.qualcomm.com> Date: Tue, 4 Nov 2025 11:35:53 +0800 Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 5/6] clk: qcom: Add TCSR clock driver for Kaanapali To: Taniya Das , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , jingyi.wang@oss.qualcomm.com Cc: Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20251030-gcc_kaanapali-v2-v2-0-a774a587af6f@oss.qualcomm.com> <20251030-gcc_kaanapali-v2-v2-5-a774a587af6f@oss.qualcomm.com> From: "Aiqun(Maria) Yu" Content-Language: en-US In-Reply-To: <20251030-gcc_kaanapali-v2-v2-5-a774a587af6f@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=APHuRV3Y c=1 sm=1 tr=0 ts=690974a0 cx=c_pps a=mDZGXZTwRPZaeRUbqKGCBw==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=6UeiqGixMTsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=vSTseKTzBe5nLB2U_wEA:9 a=QEXdDO2ut3YA:10 a=zc0IvFSfCIW2DFIPzwfm:22 X-Proofpoint-GUID: CGsBArMBfItQ-fxw7NB18Wd73JdgpJCW X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTA0MDAyNyBTYWx0ZWRfXx96cutoHDk+J b++YM5YgtcC5H/bruEoV2KjipnPT8fA3vmLHO1PdJg+4r2yx6nvPYBA+leCk3/TpbaUfgT8MaCP OkisX8B2ltSzy6zeFpXY4cPIOnraKjxeOCnJR/Z7sapRtjVQhmlVhRqhoqcWh4aWwftza8mFTuP 1mmPBb71ZiPbdVFJytOasF3/CXBQQIWdwohsNQICLYq88WE2o0ZYPsx7vJHHAc5sFRfJKrJ6Fwz s4vGzHqi1EsrDsQzrc9uD+hcBhGMTxGwcTu5N4oWfrfh6zGE4YF0YIU7sGiSWG0BuYFy1X2CvOH FAAXfQxJ7zPE7XBfNPwkppTTVmkFcbkfAoN1TsFIOdpAOqX0hN0lAoFof5Q5zsRHklNoQ6B2xVK 7RknJ3i7/KuWcHezvHZzL62zhjIGmg== X-Proofpoint-ORIG-GUID: CGsBArMBfItQ-fxw7NB18Wd73JdgpJCW X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-03_06,2025-11-03_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 clxscore=1015 impostorscore=0 priorityscore=1501 phishscore=0 suspectscore=0 adultscore=0 bulkscore=0 spamscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2511040027 On 10/30/2025 7:09 PM, Taniya Das wrote: > Add the TCSR clock controller that provides the refclks on Kaanapali > platform for PCIe, USB and UFS subsystems. > > Signed-off-by: Jingyi Wang > Signed-off-by: Taniya Das > --- > drivers/clk/qcom/Kconfig | 8 ++ > drivers/clk/qcom/Makefile | 1 + > drivers/clk/qcom/tcsrcc-kaanapali.c | 141 ++++++++++++++++++++++++++++++++++++ > 3 files changed, 150 insertions(+) > > diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig > index 4a78099e706c2cee5162d837cad3723db75039d0..8ec1803af76cb87da59ca3ef28127c06f3e26d2b 100644 > --- a/drivers/clk/qcom/Kconfig > +++ b/drivers/clk/qcom/Kconfig > @@ -46,6 +46,14 @@ config CLK_GLYMUR_TCSRCC > Support for the TCSR clock controller on GLYMUR devices. > Say Y if you want to use peripheral devices such as USB/PCIe/EDP. > > +config CLK_KAANAPALI_TCSRCC > + tristate "KAANAPALI TCSR Clock Controller" > + depends on ARM64 || COMPILE_TEST > + select QCOM_GDSC > + help > + Support for the TCSR clock controller on Kaanapali devices. > + Say Y if you want to use peripheral devices such as PCIe, USB, UFS. > + > config CLK_X1E80100_CAMCC > tristate "X1E80100 Camera Clock Controller" > depends on ARM64 || COMPILE_TEST > diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile > index 5a0fd1d843c87a6f0a805706fcfad91c3f705340..2350631814779ad086d5c8304b250b0cc2f5203b 100644 > --- a/drivers/clk/qcom/Makefile > +++ b/drivers/clk/qcom/Makefile > @@ -24,6 +24,7 @@ obj-$(CONFIG_CLK_GFM_LPASS_SM8250) += lpass-gfm-sm8250.o > obj-$(CONFIG_CLK_GLYMUR_DISPCC) += dispcc-glymur.o > obj-$(CONFIG_CLK_GLYMUR_GCC) += gcc-glymur.o > obj-$(CONFIG_CLK_GLYMUR_TCSRCC) += tcsrcc-glymur.o > +obj-$(CONFIG_CLK_KAANAPALI_TCSRCC) += tcsrcc-kaanapali.o > obj-$(CONFIG_CLK_X1E80100_CAMCC) += camcc-x1e80100.o > obj-$(CONFIG_CLK_X1E80100_DISPCC) += dispcc-x1e80100.o > obj-$(CONFIG_CLK_X1E80100_GCC) += gcc-x1e80100.o > diff --git a/drivers/clk/qcom/tcsrcc-kaanapali.c b/drivers/clk/qcom/tcsrcc-kaanapali.c > new file mode 100644 > index 0000000000000000000000000000000000000000..14cfa75e892cc5ee1b03909f8c03d92de8ae2cd6 > --- /dev/null > +++ b/drivers/clk/qcom/tcsrcc-kaanapali.c > @@ -0,0 +1,141 @@ > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +/* > + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. > + */ > + > +#include > +#include > +#include > +#include > +#include > + > +#include > + > +#include "clk-branch.h" > +#include "clk-regmap.h" > +#include "clk-regmap-divider.h" > +#include "clk-regmap-mux.h" > +#include "common.h" > + > +enum { > + DT_BI_TCXO_PAD, > +}; > + > +static struct clk_branch tcsr_pcie_0_clkref_en = { > + .halt_reg = 0x0, > + .halt_check = BRANCH_HALT_DELAY, > + .clkr = { > + .enable_reg = 0x0, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "tcsr_pcie_0_clkref_en", > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch tcsr_ufs_clkref_en = { > + .halt_reg = 0x10, > + .halt_check = BRANCH_HALT_DELAY, > + .clkr = { > + .enable_reg = 0x10, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "tcsr_ufs_clkref_en", > + .parent_data = &(const struct clk_parent_data){ > + .index = DT_BI_TCXO_PAD, > + }, > + .num_parents = 1, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch tcsr_usb2_clkref_en = { > + .halt_reg = 0x18, > + .halt_check = BRANCH_HALT_DELAY, > + .clkr = { > + .enable_reg = 0x18, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "tcsr_usb2_clkref_en", > + .parent_data = &(const struct clk_parent_data){ > + .index = DT_BI_TCXO_PAD, > + }, > + .num_parents = 1, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch tcsr_usb3_clkref_en = { > + .halt_reg = 0x8, > + .halt_check = BRANCH_HALT_DELAY, > + .clkr = { > + .enable_reg = 0x8, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "tcsr_usb3_clkref_en", > + .parent_data = &(const struct clk_parent_data){ > + .index = DT_BI_TCXO_PAD, > + }, > + .num_parents = 1, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_regmap *tcsr_cc_kaanapali_clocks[] = { > + [TCSR_PCIE_0_CLKREF_EN] = &tcsr_pcie_0_clkref_en.clkr, > + [TCSR_UFS_CLKREF_EN] = &tcsr_ufs_clkref_en.clkr, > + [TCSR_USB2_CLKREF_EN] = &tcsr_usb2_clkref_en.clkr, > + [TCSR_USB3_CLKREF_EN] = &tcsr_usb3_clkref_en.clkr, > +}; > + > +static const struct regmap_config tcsr_cc_kaanapali_regmap_config = { > + .reg_bits = 32, > + .reg_stride = 4, > + .val_bits = 32, > + .max_register = 0x18, > + .fast_io = true, > +}; > + > +static const struct qcom_cc_desc tcsr_cc_kaanapali_desc = { > + .config = &tcsr_cc_kaanapali_regmap_config, > + .clks = tcsr_cc_kaanapali_clocks, > + .num_clks = ARRAY_SIZE(tcsr_cc_kaanapali_clocks), > +}; > + > +static const struct of_device_id tcsr_cc_kaanapali_match_table[] = { > + { .compatible = "qcom,kaanapali-tcsr" }, > + { } > +}; > +MODULE_DEVICE_TABLE(of, tcsr_cc_kaanapali_match_table); > + > +static int tcsr_cc_kaanapali_probe(struct platform_device *pdev) > +{ > + return qcom_cc_probe(pdev, &tcsr_cc_kaanapali_desc); > +} > + > +static struct platform_driver tcsr_cc_kaanapali_driver = { > + .probe = tcsr_cc_kaanapali_probe, > + .driver = { > + .name = "tcsr_cc-kaanapali", > + .of_match_table = tcsr_cc_kaanapali_match_table, > + }, > +}; > + > +static int __init tcsr_cc_kaanapali_init(void) > +{ > + return platform_driver_register(&tcsr_cc_kaanapali_driver); > +} > +subsys_initcall(tcsr_cc_kaanapali_init); > + > +static void __exit tcsr_cc_kaanapali_exit(void) > +{ > + platform_driver_unregister(&tcsr_cc_kaanapali_driver); > +} > +module_exit(tcsr_cc_kaanapali_exit); > + > +MODULE_DESCRIPTION("QTI TCSR_CC KAANAPALI Driver"); > +MODULE_LICENSE("GPL"); > Remind for review. I can see the previous comments was well addressed. -- Thx and BRs, Aiqun(Maria) Yu