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[91.159.24.186]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5990da119c1sm806260e87.18.2025.12.16.02.47.47 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 16 Dec 2025 02:47:47 -0800 (PST) Message-ID: <3658e6cc-755c-4b38-aec7-b8bfdd7c8bd2@linaro.org> Date: Tue, 16 Dec 2025 12:47:46 +0200 Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 05/11] dt-bindings: clock: qcom: Add support for CAMCC for Kaanapali Content-Language: ru-RU To: Taniya Das , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Maxime Coquelin , Alexandre Torgue , Konrad Dybcio Cc: Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org References: <20251125-kaanapali-mmcc-v2-v2-0-fb44e78f300b@oss.qualcomm.com> <20251125-kaanapali-mmcc-v2-v2-5-fb44e78f300b@oss.qualcomm.com> From: Vladimir Zapolskiy In-Reply-To: <20251125-kaanapali-mmcc-v2-v2-5-fb44e78f300b@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Hi Taniya. On 11/25/25 19:45, Taniya Das wrote: > Update the compatible and the bindings for CAMCC support on Kaanapali > SoC. > > Signed-off-by: Taniya Das > --- > .../bindings/clock/qcom,sm8450-camcc.yaml | 6 + > .../clock/qcom,kaanapali-cambistmclkcc.h | 33 +++++ > include/dt-bindings/clock/qcom,kaanapali-camcc.h | 147 +++++++++++++++++++++ > 3 files changed, 186 insertions(+) > > diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml > index c1e06f39431e68a3cd2f6c2dba84be2a3c143bb1..3ec9bf4d82ad3b0fbb3e58fe312a416b3580c30c 100644 > --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml > +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml > @@ -15,6 +15,8 @@ description: | > domains on SM8450. > > See also: > + include/dt-bindings/clock/qcom,kaanapali-camcc.h > + include/dt-bindings/clock/qcom,kaanapali-cambistmclkcc.h > include/dt-bindings/clock/qcom,sm8450-camcc.h > include/dt-bindings/clock/qcom,sm8550-camcc.h > include/dt-bindings/clock/qcom,sm8650-camcc.h > @@ -22,6 +24,8 @@ description: | > properties: > compatible: > enum: > + - qcom,kaanapali-cambistmclkcc > + - qcom,kaanapali-camcc I do have right the same review comment as the given for SM8750 CAMCC one. The introduced qcom,kaanapali-cambistmclkcc does not inherit reset controller or power domain controller properties, thus it should not be added to the list of regular camera clock contollers. Please create a new dt schema file for qcom,kaanapali-cambistmclkcc and qcom,sm8750-cambistmclkcc IP descriptions. > - qcom,sm8450-camcc > - qcom,sm8475-camcc > - qcom,sm8550-camcc > @@ -63,6 +67,8 @@ allOf: > compatible: > contains: > enum: > + - qcom,kaanapali-cambistmclkcc > + - qcom,kaanapali-camcc > - qcom,sc8280xp-camcc > - qcom,sm8450-camcc > - qcom,sm8550-camcc > diff --git a/include/dt-bindings/clock/qcom,kaanapali-cambistmclkcc.h b/include/dt-bindings/clock/qcom,kaanapali-cambistmclkcc.h > new file mode 100644 > index 0000000000000000000000000000000000000000..ddb083b5289ecc5ddbf9ce0b8afa5e2b3bd7ccad > --- /dev/null > +++ b/include/dt-bindings/clock/qcom,kaanapali-cambistmclkcc.h > @@ -0,0 +1,33 @@ > +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ > +/* > + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. > + */ > + > +#ifndef _DT_BINDINGS_CLK_QCOM_CAM_BIST_MCLK_CC_KAANAPALI_H > +#define _DT_BINDINGS_CLK_QCOM_CAM_BIST_MCLK_CC_KAANAPALI_H > + > +/* CAM_BIST_MCLK_CC clocks */ > +#define CAM_BIST_MCLK_CC_DEBUG_CLK 0 > +#define CAM_BIST_MCLK_CC_DEBUG_DIV_CLK_SRC 1 > +#define CAM_BIST_MCLK_CC_MCLK0_CLK 2 > +#define CAM_BIST_MCLK_CC_MCLK0_CLK_SRC 3 > +#define CAM_BIST_MCLK_CC_MCLK1_CLK 4 > +#define CAM_BIST_MCLK_CC_MCLK1_CLK_SRC 5 > +#define CAM_BIST_MCLK_CC_MCLK2_CLK 6 > +#define CAM_BIST_MCLK_CC_MCLK2_CLK_SRC 7 > +#define CAM_BIST_MCLK_CC_MCLK3_CLK 8 > +#define CAM_BIST_MCLK_CC_MCLK3_CLK_SRC 9 > +#define CAM_BIST_MCLK_CC_MCLK4_CLK 10 > +#define CAM_BIST_MCLK_CC_MCLK4_CLK_SRC 11 > +#define CAM_BIST_MCLK_CC_MCLK5_CLK 12 > +#define CAM_BIST_MCLK_CC_MCLK5_CLK_SRC 13 > +#define CAM_BIST_MCLK_CC_MCLK6_CLK 14 > +#define CAM_BIST_MCLK_CC_MCLK6_CLK_SRC 15 > +#define CAM_BIST_MCLK_CC_MCLK7_CLK 16 > +#define CAM_BIST_MCLK_CC_MCLK7_CLK_SRC 17 > +#define CAM_BIST_MCLK_CC_PLL0 18 > +#define CAM_BIST_MCLK_CC_PLL_TEST_CLK 19 > +#define CAM_BIST_MCLK_CC_PLL_TEST_DIV_CLK_SRC 20 > +#define CAM_BIST_MCLK_CC_SLEEP_CLK 21 > + > +#endif -- Best wishes, Vladimir