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Thu, 21 Mar 2024 11:33:55 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 42LBXsYG018083 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 21 Mar 2024 11:33:54 GMT Received: from [10.218.5.19] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Thu, 21 Mar 2024 04:33:48 -0700 Message-ID: <37942292-fb99-4d3b-9933-50d338e87661@quicinc.com> Date: Thu, 21 Mar 2024 17:03:45 +0530 Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH V2 RESEND 3/6] clk: qcom: videocc-sm8550: Add SM8650 video clock controller Content-Language: en-US To: Dmitry Baryshkov CC: Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , Vladimir Zapolskiy , , , , , Taniya Das , Satya Priya Kakitapalli , Ajit Pandey , Imran Shaik References: <20240321092529.13362-1-quic_jkona@quicinc.com> <20240321092529.13362-4-quic_jkona@quicinc.com> From: Jagadeesh Kona In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: bt3LftOV1EX1LBcHb8MIbxP5q2D-YnDu X-Proofpoint-GUID: bt3LftOV1EX1LBcHb8MIbxP5q2D-YnDu X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-03-21_08,2024-03-18_03,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 bulkscore=0 clxscore=1015 lowpriorityscore=0 phishscore=0 mlxlogscore=999 suspectscore=0 spamscore=0 priorityscore=1501 malwarescore=0 adultscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2403140001 definitions=main-2403210081 On 3/21/2024 3:33 PM, Dmitry Baryshkov wrote: > On Thu, 21 Mar 2024 at 11:27, Jagadeesh Kona wrote: >> >> Add support to the SM8650 video clock controller by extending >> the SM8550 video clock controller, which is mostly identical >> but SM8650 has few additional clocks and minor differences. >> >> Signed-off-by: Jagadeesh Kona > > Reviewed-by: Dmitry Baryshkov > > > >> @@ -411,6 +540,7 @@ static int video_cc_sm8550_probe(struct platform_device *pdev) >> { >> struct regmap *regmap; >> int ret; >> + u32 offset = 0x8140; > > Nit: this variable seems misnamed. Please rename to something like > sleep_clk_offset; > Thanks Dmitry for your review. Yes, will rename this in the next series. Thanks, Jagadeesh >> >> ret = devm_pm_runtime_enable(&pdev->dev); >> if (ret) >> @@ -426,12 +556,27 @@ static int video_cc_sm8550_probe(struct platform_device *pdev) >> return PTR_ERR(regmap); >> } >> >> + if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8650-videocc")) { >> + offset = 0x8150; >> + video_cc_pll0_config.l = 0x1e; >> + video_cc_pll0_config.alpha = 0xa000; >> + video_cc_pll1_config.l = 0x2b; >> + video_cc_pll1_config.alpha = 0xc000; >> + video_cc_mvs0_clk_src.freq_tbl = ftbl_video_cc_mvs0_clk_src_sm8650; >> + video_cc_mvs1_clk_src.freq_tbl = ftbl_video_cc_mvs1_clk_src_sm8650; >> + video_cc_sm8550_clocks[VIDEO_CC_MVS0_SHIFT_CLK] = &video_cc_mvs0_shift_clk.clkr; >> + video_cc_sm8550_clocks[VIDEO_CC_MVS0C_SHIFT_CLK] = &video_cc_mvs0c_shift_clk.clkr; >> + video_cc_sm8550_clocks[VIDEO_CC_MVS1_SHIFT_CLK] = &video_cc_mvs1_shift_clk.clkr; >> + video_cc_sm8550_clocks[VIDEO_CC_MVS1C_SHIFT_CLK] = &video_cc_mvs1c_shift_clk.clkr; >> + video_cc_sm8550_clocks[VIDEO_CC_XO_CLK_SRC] = &video_cc_xo_clk_src.clkr; >> + } >> + >> clk_lucid_ole_pll_configure(&video_cc_pll0, regmap, &video_cc_pll0_config); >> clk_lucid_ole_pll_configure(&video_cc_pll1, regmap, &video_cc_pll1_config); >> >> /* Keep some clocks always-on */ >> qcom_branch_set_clk_en(regmap, 0x80f4); /* VIDEO_CC_AHB_CLK */ >> - qcom_branch_set_clk_en(regmap, 0x8140); /* VIDEO_CC_SLEEP_CLK */ >> + qcom_branch_set_clk_en(regmap, offset); /* VIDEO_CC_SLEEP_CLK */ >> qcom_branch_set_clk_en(regmap, 0x8124); /* VIDEO_CC_XO_CLK */ >> >> ret = qcom_cc_really_probe(pdev, &video_cc_sm8550_desc, regmap); >> -- >> 2.43.0 >> >> > >