From: Taniya Das <taniya.das@oss.qualcomm.com>
To: Konrad Dybcio <konradybcio@kernel.org>,
Bjorn Andersson <andersson@kernel.org>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>,
Luca Weiss <luca.weiss@fairphone.com>,
Dmitry Baryshkov <lumag@kernel.org>,
Ajit Pandey <quic_ajipan@quicinc.com>,
Taniya Das <quic_tdas@quicinc.com>,
Jagadeesh Kona <quic_jkona@quicinc.com>
Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
linux-kernel@vger.kernel.org,
Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Subject: Re: [PATCH 5/5] clk: qcom: dispcc[01]-sa8775p: Fix DSI byte clock rate setting
Date: Thu, 5 Mar 2026 11:43:47 +0530 [thread overview]
Message-ID: <38302cbf-d832-49de-8e8e-06ca3dd1ce6f@oss.qualcomm.com> (raw)
In-Reply-To: <20260304-topic-dsi_byte_fixup-v1-5-b79b29f83176@oss.qualcomm.com>
On 3/4/2026 7:18 PM, Konrad Dybcio wrote:
> The clock tree for byte_clk_src is as follows:
>
> ┌──────byte0_clk_src─────┐
> │ │
> byte0_clk byte0_div_clk_src
> │
> byte0_intf_clk
>
> If both of its direct children have CLK_SET_RATE_PARENT with different
> requests, byte0_clk_src (and its parent) will be reconfigured. In this
> case, byte0_intf should strictly follow the rate of byte0_clk (with
> some adjustments based on PHY mode).
>
> Remove CLK_SET_RATE_PARENT from byte0_div_clk_src to avoid this issue.
>
> Fixes: e700bfd2f976 ("clk: qcom: Add support for Display clock Controllers on SA8775P")
> Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> ---
> drivers/clk/qcom/dispcc0-sa8775p.c | 2 --
> drivers/clk/qcom/dispcc1-sa8775p.c | 2 --
> 2 files changed, 4 deletions(-)
Reviewed-by: Taniya Das <taniya.das@oss.qualcomm.com>
--
Thanks,
Taniya Das
next prev parent reply other threads:[~2026-03-05 6:13 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-04 13:48 [PATCH 0/5] DSI byte clock setting fixup Konrad Dybcio
2026-03-04 13:48 ` [PATCH 1/5] clk: qcom: dispcc-glymur: Fix DSI byte clock rate setting Konrad Dybcio
2026-03-04 14:26 ` Dmitry Baryshkov
2026-03-05 6:12 ` Taniya Das
2026-03-04 13:48 ` [PATCH 2/5] clk: qcom: dispcc-kaanapali: " Konrad Dybcio
2026-03-04 14:27 ` Dmitry Baryshkov
2026-03-05 6:13 ` Taniya Das
2026-03-04 13:48 ` [PATCH 3/5] clk: qcom: dispcc-milos: " Konrad Dybcio
2026-03-04 14:27 ` Dmitry Baryshkov
2026-03-05 6:16 ` Taniya Das
2026-03-04 13:48 ` [PATCH 4/5] clk: qcom: dispcc-sm4450: " Konrad Dybcio
2026-03-04 14:27 ` Dmitry Baryshkov
2026-03-05 6:14 ` Taniya Das
2026-03-04 13:48 ` [PATCH 5/5] clk: qcom: dispcc[01]-sa8775p: " Konrad Dybcio
2026-03-04 14:27 ` Dmitry Baryshkov
2026-03-05 6:13 ` Taniya Das [this message]
2026-03-10 2:45 ` [PATCH 0/5] DSI byte clock setting fixup Bjorn Andersson
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