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From: "Johnson Wang (王聖鑫)" <Johnson.Wang@mediatek.com>
To: "sboyd@kernel.org" <sboyd@kernel.org>,
	"angelogioacchino.delregno@collabora.com" 
	<angelogioacchino.delregno@collabora.com>,
	"robh+dt@kernel.org" <robh+dt@kernel.org>,
	"krzysztof.kozlowski+dt@linaro.org" 
	<krzysztof.kozlowski+dt@linaro.org>
Cc: "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"linux-mediatek@lists.infradead.org"
	<linux-mediatek@lists.infradead.org>,
	"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
	"Kuan-Hsin Lee (李冠新)" <Kuan-Hsin.Lee@mediatek.com>,
	Project_Global_Chrome_Upstream_Group
	<Project_Global_Chrome_Upstream_Group@mediatek.com>,
	"Yu-Chang Wang (王煜樟)" <Yu-Chang.Wang@mediatek.com>,
	"linux-arm-kernel@lists.infradead.org"
	<linux-arm-kernel@lists.infradead.org>,
	"linux-clk@vger.kernel.org" <linux-clk@vger.kernel.org>,
	"Edward-JW Yang (楊哲維)" <Edward-JW.Yang@mediatek.com>
Subject: Re: [PATCH v4 2/4] dt-bindings: arm: mediatek: Add new bindings of MediaTek frequency hopping
Date: Tue, 1 Nov 2022 12:26:05 +0000	[thread overview]
Message-ID: <3abb912267895b39829e62ea2ce1c830adcf0a70.camel@mediatek.com> (raw)
In-Reply-To: <b5e4a2332942722f4138e5bf758f61e15dbad92e.camel@mediatek.com>

On Fri, 2022-10-21 at 11:17 +0000, Johnson Wang (王聖鑫) wrote:
> On Mon, 2022-10-17 at 12:04 -0700, Stephen Boyd wrote:
> > Quoting Johnson Wang (王聖鑫) (2022-10-17 05:55:09)
> > > On Fri, 2022-10-14 at 13:42 -0700, Stephen Boyd wrote:
> > > > Quoting Johnson Wang (2022-10-13 04:23:34)
> > > > > +  - |
> > > > > +    #include <dt-bindings/clock/mt8186-clk.h>
> > > > > +    fhctl: fhctl@1000ce00 {
> > > > 
> > > > Is it a clock-controller? 'fhctl' isn't a generic node name.
> > > > 
> > > 
> > > This node is used for determining if PLLs adopt "hopping" method
> > > to
> > > adjust their frequency.
> > > It doesn't provide any clock but actually change the behavior of
> > > some
> > > PLLs with new .set_rate callback.
> > > Do you think this node acts like one kind of clock-controller?
> > 
> > Why can't we add the reg and properties to the node that implements
> > the
> > PLL?
> 
> Hi Stephen,
> 
> Now we use standard clocks property to get clock indices from
> apmixedsys node.
> 
> If we integrate the reg and properties into apmixedsys node, we have
> to
> figure out another way to get indices... (I think one node shouldn't
> take itself as input?)
> 
> There is an idea in my mind. Add these prperties into apmixedsys
> node.
> 
> 	mediatek,hopping-clocks = <CLK_APMIXED_MAINPLL>,
> 			          <CLK_APMIXED_MSDCPLL>;
> 	mediatek,ssc-percent = <2 3>;
> 
> 
> But I don't really know if this violates some rules.
> Could you please give us some suggestion?
> Thanks!
> 
> BRs,
> Johnson Wang

Hi Stephen,

A gentle ping for this.

Could you please give me some advices if you prefer intergrating these
into one node?

Thank you very much!


BRs,
Johnson Wang

  reply	other threads:[~2022-11-01 12:26 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-10-13 11:23 [PATCH v4 0/4] Introduce MediaTek frequency hopping driver Johnson Wang
2022-10-13 11:23 ` [PATCH v4 1/4] clk: mediatek: Export PLL operations symbols Johnson Wang
2022-10-13 12:00   ` AngeloGioacchino Del Regno
2022-10-13 11:23 ` [PATCH v4 2/4] dt-bindings: arm: mediatek: Add new bindings of MediaTek frequency hopping Johnson Wang
2022-10-14 20:42   ` Stephen Boyd
2022-10-17 12:55     ` Johnson Wang (王聖鑫)
     [not found]       ` <20221017190501.0B85AC433C1@smtp.kernel.org>
2022-10-21 11:17         ` Johnson Wang (王聖鑫)
2022-11-01 12:26           ` Johnson Wang (王聖鑫) [this message]
2022-10-13 11:23 ` [PATCH v4 3/4] clk: mediatek: Add new clock driver to handle FHCTL hardware Johnson Wang
2022-10-13 12:00   ` AngeloGioacchino Del Regno
2022-10-13 11:23 ` [PATCH v4 4/4] clk: mediatek: Change PLL register API for MT8186 Johnson Wang
2022-10-13 12:00   ` AngeloGioacchino Del Regno

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