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[82.243.161.21]) by smtp.gmail.com with ESMTPSA id u19sm4487071wmc.7.2019.03.29.16.07.54 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 29 Mar 2019 16:07:55 -0700 (PDT) Message-ID: <3bef1bb26e9eff0cfc20cd4bb78a5d7cea4c5076.camel@baylibre.com> Subject: Re: [PATCH 1/3] clk: meson: mpll: properly handle spread spectrum From: Jerome Brunet To: Martin Blumenstingl Cc: Neil Armstrong , linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Date: Sat, 30 Mar 2019 00:07:53 +0100 In-Reply-To: References: <20190329153325.23869-1-jbrunet@baylibre.com> <20190329153325.23869-2-jbrunet@baylibre.com> Content-Type: text/plain; charset="UTF-8" User-Agent: Evolution 3.30.5 (3.30.5-1.fc29) MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org On Fri, 2019-03-29 at 20:39 +0100, Martin Blumenstingl wrote: > Hi Jerome, > > On Fri, Mar 29, 2019 at 4:34 PM Jerome Brunet wrote: > > The bit 'SSEN' available on some MPLL DSS outputs is not related to the > > fractional part of the divider but to the function called > > 'Spread Spectrum'. > > > > This function might be used to solve EM issues by adding a jitter on > > clock signal. This widens the signal spectrum and weakens the peaks in it. > > > > While spread spectrum might be useful for some application, it is > > problematic for others, such as audio. > > > > This patch introduce a new flag to the MPLL driver to enable (or not) the > > spread spectrum function. > > > > Fixes: 1f737ffa13ef ("clk: meson: mpll: fix mpll0 fractional part ignored") > > Signed-off-by: Jerome Brunet > > --- > > drivers/clk/meson/clk-mpll.c | 9 ++++++--- > > drivers/clk/meson/clk-mpll.h | 1 + > > 2 files changed, 7 insertions(+), 3 deletions(-) > > > > diff --git a/drivers/clk/meson/clk-mpll.c b/drivers/clk/meson/clk-mpll.c > > index 64d31c8ba3d0..2d39a8bc367c 100644 > > --- a/drivers/clk/meson/clk-mpll.c > > +++ b/drivers/clk/meson/clk-mpll.c > > @@ -141,9 +141,12 @@ static void mpll_init(struct clk_hw *hw) > > /* Enable the fractional part */ > > meson_parm_write(clk->map, &mpll->sdm_en, 1); > > > > - /* Set additional fractional part enable if required */ > > - if (MESON_PARM_APPLICABLE(&mpll->ssen)) > > - meson_parm_write(clk->map, &mpll->ssen, 1); > > + /* Set spread spectrum if possible */ > > + if (MESON_PARM_APPLICABLE(&mpll->ssen)) { > > + unsigned int ss = > > + mpll->flags & CLK_MESON_MPLL_SPREAD_SPECTRUM ? 1 : 0; > > + meson_parm_write(clk->map, &mpll->ssen, ss); > > + } > this changes the "ssen" flag on all supported clocks from 1 (before > this patch) to 0 (after this patch). > is this on purpose and how does it affect existing clocks? Yes, none of our application require spread spectrum The fact is that only 2 MPLL had this bit, mpll0 on gx (without effect) and mpll0 on axg: actually spread spectrum impacts mpll2, making it unusable, as explained in the related patch > > based on the original commit 1f737ffa13ef ("clk: meson: mpll: fix > mpll0 fractional part ignored") it seems that > CLK_MESON_MPLL_SPREAD_SPECTRUM should be set for mpll0 (at least on > GXBB and Meson8b) > There a patch specifically targeting gxbb. I have checked on GXL and this bit had no effect (fractional part still on, no spread spectrum) So either we fixed something since then or I messed up when doing the patch initially. Feel free to cross check > > Martin