Re: [PATCH 3/3] clk: amlogic: s4: remove unused data

[Chuan Liu <chuan.liu@amlogic.com>]

Hi Jerome:

Thank you for pointing out.


On 12/21/2024 1:17 AM, Jerome Brunet wrote:
> [ EXTERNAL EMAIL ]
>
> Following the removal of the big clk_regmap clock table from the
> s4-peripherals clock controller driver, it appears some clocks are unused,
> which means these are not exported or even registered.


I have confirmed here that these clocks are used for the demodulator
of DTV (Digital Television). The DTV-related driver will use these
clocks.


>
> In all likelihood, these clocks have not been tested. Remove the unused
> clocks for now. These can added back later when they have been properly
> tested.


I will complete these clocks later after testing.


> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
> ---
>   drivers/clk/meson/s4-peripherals.c | 112 -------------------------------------
>   1 file changed, 112 deletions(-)
>
> diff --git a/drivers/clk/meson/s4-peripherals.c b/drivers/clk/meson/s4-peripherals.c
> index 91c7b10c2b68c626dd1d6164ea855370aae71485..72b990fc0de8e4e2c83d0fc3b4c6e3fc1fc96367 100644
> --- a/drivers/clk/meson/s4-peripherals.c
> +++ b/drivers/clk/meson/s4-peripherals.c
> @@ -3129,118 +3129,6 @@ static struct clk_regmap s4_gen_clk = {
>          },
>   };
>
> -static const struct clk_parent_data s4_adc_extclk_in_parent_data[]  = {
> -       { .fw_name = "xtal", },
> -       { .fw_name = "fclk_div4", },
> -       { .fw_name = "fclk_div3", },
> -       { .fw_name = "fclk_div5", },
> -       { .fw_name = "fclk_div7", },
> -       { .fw_name = "mpll2", },
> -       { .fw_name = "gp0_pll", },
> -       { .fw_name = "hifi_pll", },
> -};
> -
> -static struct clk_regmap s4_adc_extclk_in_mux = {
> -       .data = &(struct clk_regmap_mux_data) {
> -               .offset = CLKCTRL_DEMOD_CLK_CTRL,
> -               .mask = 0x7,
> -               .shift = 25,
> -       },
> -       .hw.init = &(struct clk_init_data){
> -               .name = "adc_extclk_in_mux",
> -               .ops = &clk_regmap_mux_ops,
> -               .parent_data = s4_adc_extclk_in_parent_data,
> -               .num_parents = ARRAY_SIZE(s4_adc_extclk_in_parent_data),
> -               .flags = 0,
> -       },
> -};
> -
> -static struct clk_regmap s4_adc_extclk_in_div = {
> -       .data = &(struct clk_regmap_div_data) {
> -               .offset = CLKCTRL_DEMOD_CLK_CTRL,
> -               .shift = 16,
> -               .width = 7,
> -       },
> -       .hw.init = &(struct clk_init_data){
> -               .name = "adc_extclk_in_div",
> -               .ops = &clk_regmap_divider_ops,
> -               .parent_hws = (const struct clk_hw *[]) {
> -                       &s4_adc_extclk_in_mux.hw
> -               },
> -               .num_parents = 1,
> -               .flags = CLK_SET_RATE_PARENT,
> -       },
> -};
> -
> -static struct clk_regmap s4_adc_extclk_in_gate = {
> -       .data = &(struct clk_regmap_gate_data) {
> -               .offset = CLKCTRL_DEMOD_CLK_CTRL,
> -               .bit_idx = 24,
> -       },
> -       .hw.init = &(struct clk_init_data){
> -               .name = "adc_extclk_in",
> -               .ops = &clk_regmap_gate_ops,
> -               .parent_hws = (const struct clk_hw *[]) {
> -                       &s4_adc_extclk_in_div.hw
> -               },
> -               .num_parents = 1,
> -               .flags = CLK_SET_RATE_PARENT,
> -       },
> -};
> -
> -static struct clk_regmap s4_demod_core_clk_mux = {
> -       .data = &(struct clk_regmap_mux_data) {
> -               .offset = CLKCTRL_DEMOD_CLK_CTRL,
> -               .mask = 0x3,
> -               .shift = 9,
> -       },
> -       .hw.init = &(struct clk_init_data){
> -               .name = "demod_core_clk_mux",
> -               .ops = &clk_regmap_mux_ops,
> -               .parent_data = (const struct clk_parent_data []) {
> -                       { .fw_name = "xtal", },
> -                       { .fw_name = "fclk_div7", },
> -                       { .fw_name = "fclk_div4", },
> -                       { .hw = &s4_adc_extclk_in_gate.hw }
> -               },
> -               .num_parents = 4,
> -               .flags = CLK_SET_RATE_PARENT,
> -       },
> -};
> -
> -static struct clk_regmap s4_demod_core_clk_div = {
> -       .data = &(struct clk_regmap_div_data) {
> -               .offset = CLKCTRL_DEMOD_CLK_CTRL,
> -               .shift = 0,
> -               .width = 7,
> -       },
> -       .hw.init = &(struct clk_init_data){
> -               .name = "demod_core_clk_div",
> -               .ops = &clk_regmap_divider_ops,
> -               .parent_hws = (const struct clk_hw *[]) {
> -                       &s4_demod_core_clk_mux.hw
> -               },
> -               .num_parents = 1,
> -               .flags = CLK_SET_RATE_PARENT,
> -       },
> -};
> -
> -static struct clk_regmap s4_demod_core_clk_gate = {
> -       .data = &(struct clk_regmap_gate_data) {
> -               .offset = CLKCTRL_DEMOD_CLK_CTRL,
> -               .bit_idx = 8,
> -       },
> -       .hw.init = &(struct clk_init_data){
> -               .name = "demod_core_clk",
> -               .ops = &clk_regmap_gate_ops,
> -               .parent_hws = (const struct clk_hw *[]) {
> -                       &s4_demod_core_clk_div.hw
> -               },
> -               .num_parents = 1,
> -               .flags = CLK_SET_RATE_PARENT,
> -       },
> -};
> -
>   #define MESON_GATE(_name, _reg, _bit) \
>          MESON_PCLK(_name, _reg, _bit, &s4_sys_clk.hw)
>
>
> --
> 2.45.2
>
>
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