Re: [RFC PATCH v2 4/4] clk: renesas: Add RZ/V2H(P) CPG driver

Geert Uytterhoeven
2024-06-26T10:14:27Z

On Tue, Jun 11, 2024 at 1:32 AM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Add RZ/V2H(P) CPG driver.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> v1->v2
> - Updated commit description
> - Dropped pll_clk1/clk2_offset
> - Made r9a09g057_mod_clks/r9a09g057_resets as static const
> - Now using register indexes

Thanks for the update!

> --- /dev/null
> +++ b/drivers/clk/renesas/r9a09g057-cpg.c

> +static const struct rzv2h_mod_clk r9a09g057_mod_clks[] = {
> + DEF_MOD("scif_0_clk_pck", CLK_PLLCM33_DIV16, 8, 15, 4, 15),

So this relates to module clock 8 * 16 + 15 = 143 in DTS...

> +};
> +
> +static const struct rzv2h_reset r9a09g057_resets[] = {
> + DEF_RST(9, 5, 4, 6), /* SCIF_0_RST_SYSTEM_N */
> +};
> +
> +static const unsigned int r9a09g057_crit_mod_clks[] __initconst = {
> + MOD_CLK_BASE + 5, /* ICU_0_PCLK_I */
> + MOD_CLK_BASE + 19, /* GIC_0_GICCLK */

So these relate to module clocks 5 and 19 in DTS.

Actually none of these clocks are created in the driver yet, so I think
these critical clocks belong to the patch that will introduce them.

I am wondering if critical clocks should just use a flag in DEF_MOD()
instead...

The rest LGTM.

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds