From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A2C4378F39; Sun, 17 May 2026 08:27:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779006466; cv=none; b=RHyVTJR4O2DlxK5jpIEW4gN8fzozXrM9OAT2ADsu4dGosQeYUdw3B0sSTe44GhW6mqB5VtFppJ0n9poU7KWOREr+XA51HoMiYiEwdOk43NDQ0NzLSeQ9CP/qFrcJZiC8ESZFvHXDppZH9I7hp+OcvQYug2fDoVCnrKfvNhuj4iQ= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779006466; c=relaxed/simple; bh=TkXa2plHaTy8FdH9xHBYQ1KXuU8I1xR2SgjbAKvMc9E=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=E/g0ACZ0l63BsHLvmN9qANLO2lAnKtsQm4oOyX3ZME/2O/iZBVw71FscSf/oh0TGUGSOCfZeFaUNsYZbRJ6bbU260bMbnIiq96Cn+syTJEnnqq1zxh/nB6e/T7Y/sqtIBwYRwTM7G+lyLw08Vnp8sECHT5aaGUFS9BwCwCFuo9g= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=nbDljtzO; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="nbDljtzO" Received: by smtp.kernel.org (Postfix) with ESMTPSA id A2F71C2BCB0; Sun, 17 May 2026 08:27:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1779006466; bh=TkXa2plHaTy8FdH9xHBYQ1KXuU8I1xR2SgjbAKvMc9E=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=nbDljtzOPfJHAt4PnuNlAYHPPDDbY5fOtF2gj5nyX8I5xCFgA1rmuLrb0Hx9arCui /HvFq9r8NtSmJ/bIgfQ16Avte0hSuCYp4yUG9drkJVFsszBwi4f4P6BtEhZsv+unFP GmnysJGCgXnP7BDih+DR+1endMmeXFgjYepz/m7q/GmdVLD5ky2CZw7BHCy3Fv5Qr7 1jpuIs6N2/KexQy5YSymBfmOezTUAjCS29xpIzVd5lcyP3/6B4Z52LRQdm2or+dna1 KirRzAjfmNbqo4eYdxFeo8KAJABZJD5H3AFcubydn7wJ4wNLx2f+StdcfOX3GTwrXH +7aaicBKPAvZA== Message-ID: <408f587b-76c2-4fdd-bbe1-89414270b4ee@kernel.org> Date: Sun, 17 May 2026 10:27:39 +0200 Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 1/4] dt-bindings: clock: qcom: Add QREF regulator supplies for glymur To: Qiang Yu Cc: Bjorn Andersson , Michael Turquette , Stephen Boyd , Brian Masney , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Taniya Das , Konrad Dybcio , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, krishna.chundru@oss.qualcomm.com References: <20260506-qref_vote_0506-v3-0-5ab71d2e6f16@oss.qualcomm.com> <20260506-qref_vote_0506-v3-1-5ab71d2e6f16@oss.qualcomm.com> <20260514-outgoing-literate-dove-2e2a73@quoll> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 17/05/2026 07:39, Qiang Yu wrote: > On Thu, May 14, 2026 at 12:22:17PM +0200, Krzysztof Kozlowski wrote: >> On Wed, May 06, 2026 at 01:43:51AM -0700, Qiang Yu wrote: >>> Add regulator supply properties for the Glymur TCSR QREF/REFGEN blocks >>> required by clkref clocks. >>> >>> The vdda-qreftx*, vdda-qrefrpt*, and vdda-qrefrx* supplies map to common >>> QREF TX/RPT/RX components, while SoC-specific topology and instance count >>> differ. Document them here for qcom,glymur-tcsr. >>> >>> Signed-off-by: Qiang Yu >>> --- >>> .../bindings/clock/qcom,sm8550-tcsr.yaml | 57 ++++++++++++++++++++++ >>> 1 file changed, 57 insertions(+) >>> >>> diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml >>> index 1ccdf4b0f5dd..57921cb63230 100644 >>> --- a/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml >>> +++ b/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml >>> @@ -51,6 +51,63 @@ properties: >>> '#reset-cells': >>> const: 1 >>> >>> + vdda-refgen-0p9-supply: true >>> + vdda-refgen-1p2-supply: true >>> + vdda-qrefrx0-0p9-supply: true >>> + vdda-qrefrx1-0p9-supply: true >>> + vdda-qrefrx2-0p9-supply: true >>> + vdda-qrefrx4-0p9-supply: true >>> + vdda-qrefrx5-0p9-supply: true >>> + vdda-qreftx0-0p9-supply: true >>> + vdda-qreftx0-1p2-supply: true >>> + vdda-qreftx1-0p9-supply: true >>> + vdda-qrefrpt0-0p9-supply: true >>> + vdda-qrefrpt1-0p9-supply: true >>> + vdda-qrefrpt2-0p9-supply: true >>> + vdda-qrefrpt3-0p9-supply: true >>> + vdda-qrefrpt4-0p9-supply: true >> >> Either I do not understand your previous explanation: >> CXO -> TX0 -> RPT0 -> RPT1 -> RPT2 -> RX2 -> PCIe4_PHY >> >> or this is still wrong. There is no TCSR here, so this proves nothing. >> If TCSR is TX0, then you do not have five of them... >> >> My previous comment stay - you are not describing the actual hardware >> here. >> > The CXO network "-> TX0 -> RPT0 -> RPT1 -> RPT2 -> RX2 ->" is referred to > as the QREF block, and each component is controlled by the tcsr_clkref_en > registers. Still no clue what this -> relation is. Again, describe the hardware. > > If a PHY receives its reference clock from QREF, it will have a clkref_en > register. However, this register may be located in different regions > depending on the target. On glymur it resides in TCSR, so I added these > LDOs QREF required in tcsr yaml. Registers are not described as supplies. Best regards, Krzysztof