* [PATCH 0/7] clk: rockchip: rk3328 fixes in preparation of graphics support
@ 2018-01-22 14:15 Heiko Stuebner
2018-01-22 14:15 ` [PATCH 1/7] clk: rockchip: fix hclk_vio_niu on rk3328 Heiko Stuebner
` (7 more replies)
0 siblings, 8 replies; 10+ messages in thread
From: Heiko Stuebner @ 2018-01-22 14:15 UTC (permalink / raw)
To: linux-clk
Cc: mturquette, sboyd, linux-rockchip, robh+dt, mark.rutland,
devicetree, yang.zheng, zhangqing, Heiko Stuebner
Fix some clock issues on rk3328 to make way for the upcoming graphics
support on rk3328.
Heiko Stuebner (6):
clk: rockchip: fix hclk_vio_niu on rk3328
clk: rockchip: remove HCLK_VIO from rk3328 dt header
clk: rockchip: export sclk_hdmi_sfc on rk3328
clk: rockchip: protect all remaining rk3328 interconnect clocks
clk: rockchip: remove ignore_unused flag from rk3328 vio_h2p clocks
clk: rockchip: document hdmi_phy external input for rk3328
Zheng Yang (1):
clk: rockchip: add flags for rk3328 dclk_lcdc
.../bindings/clock/rockchip,rk3328-cru.txt | 1 +
drivers/clk/rockchip/clk-rk3328.c | 67 ++++++++++++++--------
include/dt-bindings/clock/rk3328-cru.h | 1 -
3 files changed, 44 insertions(+), 25 deletions(-)
--
2.14.2
^ permalink raw reply [flat|nested] 10+ messages in thread* [PATCH 1/7] clk: rockchip: fix hclk_vio_niu on rk3328 2018-01-22 14:15 [PATCH 0/7] clk: rockchip: rk3328 fixes in preparation of graphics support Heiko Stuebner @ 2018-01-22 14:15 ` Heiko Stuebner 2018-01-22 14:15 ` [PATCH 2/7] clk: rockchip: remove HCLK_VIO from rk3328 dt header Heiko Stuebner ` (6 subsequent siblings) 7 siblings, 0 replies; 10+ messages in thread From: Heiko Stuebner @ 2018-01-22 14:15 UTC (permalink / raw) To: linux-clk Cc: mturquette, sboyd, linux-rockchip, robh+dt, mark.rutland, devicetree, yang.zheng, zhangqing, Heiko Stuebner The clock wrongly was called hclk_vio and exported, while it actually is a clock of the interconnect-vio connection and should therefore be always on till we actually model the interconnect. So fix that and don't export it as HCLK_VIO. Signed-off-by: Heiko Stuebner <heiko@sntech.de> --- drivers/clk/rockchip/clk-rk3328.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/clk/rockchip/clk-rk3328.c b/drivers/clk/rockchip/clk-rk3328.c index b04f29774ee7..17816aec206a 100644 --- a/drivers/clk/rockchip/clk-rk3328.c +++ b/drivers/clk/rockchip/clk-rk3328.c @@ -727,7 +727,7 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = { GATE(0, "pclk_vio_h2p", "hclk_vio_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(21), 13, GFLAGS), GATE(0, "hclk_vio_h2p", "hclk_vio_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(21), 14, GFLAGS), GATE(HCLK_HDCP, "hclk_hdcp", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(22), 0, GFLAGS), - GATE(HCLK_VIO, "hclk_vio", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(22), 1, GFLAGS), + GATE(0, "hclk_vio_niu", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(22), 1, GFLAGS), GATE(PCLK_HDMI, "pclk_hdmi", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(22), 4, GFLAGS), GATE(PCLK_HDCP, "pclk_hdcp", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(22), 5, GFLAGS), @@ -861,6 +861,7 @@ static const char *const rk3328_critical_clocks[] __initconst = { "aclk_rga_niu", "pclk_vio_h2p", "hclk_vio_h2p", + "hclk_vio_niu", }; static void __init rk3328_clk_init(struct device_node *np) -- 2.14.2 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 2/7] clk: rockchip: remove HCLK_VIO from rk3328 dt header 2018-01-22 14:15 [PATCH 0/7] clk: rockchip: rk3328 fixes in preparation of graphics support Heiko Stuebner 2018-01-22 14:15 ` [PATCH 1/7] clk: rockchip: fix hclk_vio_niu on rk3328 Heiko Stuebner @ 2018-01-22 14:15 ` Heiko Stuebner 2018-01-22 14:15 ` [PATCH 3/7] clk: rockchip: export sclk_hdmi_sfc on rk3328 Heiko Stuebner ` (5 subsequent siblings) 7 siblings, 0 replies; 10+ messages in thread From: Heiko Stuebner @ 2018-01-22 14:15 UTC (permalink / raw) To: linux-clk Cc: mturquette, sboyd, linux-rockchip, robh+dt, mark.rutland, devicetree, yang.zheng, zhangqing, Heiko Stuebner This clock is not hclk_vio but hclk_vio_niu, the clock for the interconnect output. The clock got fixed and the id was never used in this incorrect form, so remove it. Signed-off-by: Heiko Stuebner <heiko@sntech.de> --- include/dt-bindings/clock/rk3328-cru.h | 1 - 1 file changed, 1 deletion(-) diff --git a/include/dt-bindings/clock/rk3328-cru.h b/include/dt-bindings/clock/rk3328-cru.h index d2b26a4b43eb..a82a0109faff 100644 --- a/include/dt-bindings/clock/rk3328-cru.h +++ b/include/dt-bindings/clock/rk3328-cru.h @@ -193,7 +193,6 @@ #define HCLK_VPU_PRE 324 #define HCLK_VIO_PRE 325 #define HCLK_VPU 326 -#define HCLK_VIO 327 #define HCLK_BUS_PRE 328 #define HCLK_PERI_PRE 329 #define HCLK_H264 330 -- 2.14.2 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 3/7] clk: rockchip: export sclk_hdmi_sfc on rk3328 2018-01-22 14:15 [PATCH 0/7] clk: rockchip: rk3328 fixes in preparation of graphics support Heiko Stuebner 2018-01-22 14:15 ` [PATCH 1/7] clk: rockchip: fix hclk_vio_niu on rk3328 Heiko Stuebner 2018-01-22 14:15 ` [PATCH 2/7] clk: rockchip: remove HCLK_VIO from rk3328 dt header Heiko Stuebner @ 2018-01-22 14:15 ` Heiko Stuebner 2018-01-22 14:15 ` [PATCH 4/7] clk: rockchip: protect all remaining rk3328 interconnect clocks Heiko Stuebner ` (4 subsequent siblings) 7 siblings, 0 replies; 10+ messages in thread From: Heiko Stuebner @ 2018-01-22 14:15 UTC (permalink / raw) To: linux-clk Cc: mturquette, sboyd, linux-rockchip, robh+dt, mark.rutland, devicetree, yang.zheng, zhangqing, Heiko Stuebner This clock is one of the dw-hdmi supplying clocks and thus needs to be exported. Signed-off-by: Heiko Stuebner <heiko@sntech.de> --- drivers/clk/rockchip/clk-rk3328.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/rockchip/clk-rk3328.c b/drivers/clk/rockchip/clk-rk3328.c index 17816aec206a..b7a28f2814e2 100644 --- a/drivers/clk/rockchip/clk-rk3328.c +++ b/drivers/clk/rockchip/clk-rk3328.c @@ -588,7 +588,7 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = { COMPOSITE(ACLK_VOP_PRE, "aclk_vop_pre", mux_4plls_p, 0, RK3328_CLKSEL_CON(39), 6, 2, MFLAGS, 0, 5, DFLAGS, RK3328_CLKGATE_CON(5), 5, GFLAGS), - GATE(0, "clk_hdmi_sfc", "xin24m", 0, + GATE(SCLK_HDMI_SFC, "sclk_hdmi_sfc", "xin24m", 0, RK3328_CLKGATE_CON(5), 4, GFLAGS), COMPOSITE_NODIV(0, "clk_cif_src", mux_2plls_p, 0, -- 2.14.2 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 4/7] clk: rockchip: protect all remaining rk3328 interconnect clocks 2018-01-22 14:15 [PATCH 0/7] clk: rockchip: rk3328 fixes in preparation of graphics support Heiko Stuebner ` (2 preceding siblings ...) 2018-01-22 14:15 ` [PATCH 3/7] clk: rockchip: export sclk_hdmi_sfc on rk3328 Heiko Stuebner @ 2018-01-22 14:15 ` Heiko Stuebner 2018-01-22 14:15 ` [PATCH 5/7] clk: rockchip: remove ignore_unused flag from rk3328 vio_h2p clocks Heiko Stuebner ` (3 subsequent siblings) 7 siblings, 0 replies; 10+ messages in thread From: Heiko Stuebner @ 2018-01-22 14:15 UTC (permalink / raw) To: linux-clk Cc: mturquette, sboyd, linux-rockchip, robh+dt, mark.rutland, devicetree, yang.zheng, zhangqing, Heiko Stuebner NIU clocks are supplying the interconnect connections to specific peripherals and are currently not controlled in any way. So to prevent things falling apart at strange moments, mark all niu clocks as critical. Most of them where marked as CLK_IGNORE_UNUSED, but that doesn't help if a parent clock then gets disabled. Signed-off-by: Heiko Stuebner <heiko@sntech.de> --- drivers/clk/rockchip/clk-rk3328.c | 56 ++++++++++++++++++++++++++------------- 1 file changed, 37 insertions(+), 19 deletions(-) diff --git a/drivers/clk/rockchip/clk-rk3328.c b/drivers/clk/rockchip/clk-rk3328.c index b7a28f2814e2..c5b381ab23b1 100644 --- a/drivers/clk/rockchip/clk-rk3328.c +++ b/drivers/clk/rockchip/clk-rk3328.c @@ -304,7 +304,7 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = { COMPOSITE_NOMUX(0, "aclk_core", "armclk", CLK_IGNORE_UNUSED, RK3328_CLKSEL_CON(1), 4, 3, DFLAGS | CLK_DIVIDER_READ_ONLY, RK3328_CLKGATE_CON(7), 1, GFLAGS), - GATE(0, "aclk_core_niu", "aclk_core", CLK_IGNORE_UNUSED, + GATE(0, "aclk_core_niu", "aclk_core", 0, RK3328_CLKGATE_CON(13), 0, GFLAGS), GATE(0, "aclk_gic400", "aclk_core", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(13), 1, GFLAGS), @@ -318,7 +318,7 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = { RK3328_CLKGATE_CON(6), 6, GFLAGS), GATE(ACLK_GPU, "aclk_gpu", "aclk_gpu_pre", CLK_SET_RATE_PARENT, RK3328_CLKGATE_CON(14), 0, GFLAGS), - GATE(0, "aclk_gpu_niu", "aclk_gpu_pre", CLK_IGNORE_UNUSED, + GATE(0, "aclk_gpu_niu", "aclk_gpu_pre", 0, RK3328_CLKGATE_CON(14), 1, GFLAGS), /* PD_DDR */ @@ -513,9 +513,9 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = { RK3328_CLKGATE_CON(24), 0, GFLAGS), GATE(HCLK_RKVDEC, "hclk_rkvdec", "hclk_rkvdec_pre", CLK_SET_RATE_PARENT, RK3328_CLKGATE_CON(24), 1, GFLAGS), - GATE(0, "aclk_rkvdec_niu", "aclk_rkvdec_pre", CLK_IGNORE_UNUSED, + GATE(0, "aclk_rkvdec_niu", "aclk_rkvdec_pre", 0, RK3328_CLKGATE_CON(24), 2, GFLAGS), - GATE(0, "hclk_rkvdec_niu", "hclk_rkvdec_pre", CLK_IGNORE_UNUSED, + GATE(0, "hclk_rkvdec_niu", "hclk_rkvdec_pre", 0, RK3328_CLKGATE_CON(24), 3, GFLAGS), COMPOSITE(SCLK_VDEC_CABAC, "sclk_vdec_cabac", mux_4plls_p, 0, @@ -535,9 +535,9 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = { RK3328_CLKGATE_CON(23), 0, GFLAGS), GATE(HCLK_VPU, "hclk_vpu", "hclk_vpu_pre", CLK_SET_RATE_PARENT, RK3328_CLKGATE_CON(23), 1, GFLAGS), - GATE(0, "aclk_vpu_niu", "aclk_vpu_pre", CLK_IGNORE_UNUSED, + GATE(0, "aclk_vpu_niu", "aclk_vpu_pre", 0, RK3328_CLKGATE_CON(23), 2, GFLAGS), - GATE(0, "hclk_vpu_niu", "hclk_vpu_pre", CLK_IGNORE_UNUSED, + GATE(0, "hclk_vpu_niu", "hclk_vpu_pre", 0, RK3328_CLKGATE_CON(23), 3, GFLAGS), COMPOSITE(ACLK_RKVENC, "aclk_rkvenc", mux_4plls_p, 0, @@ -545,9 +545,9 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = { RK3328_CLKGATE_CON(6), 3, GFLAGS), FACTOR_GATE(HCLK_RKVENC, "hclk_rkvenc", "aclk_rkvenc", 0, 1, 4, RK3328_CLKGATE_CON(11), 4, GFLAGS), - GATE(0, "aclk_rkvenc_niu", "aclk_rkvenc", CLK_IGNORE_UNUSED, + GATE(0, "aclk_rkvenc_niu", "aclk_rkvenc", 0, RK3328_CLKGATE_CON(25), 0, GFLAGS), - GATE(0, "hclk_rkvenc_niu", "hclk_rkvenc", CLK_IGNORE_UNUSED, + GATE(0, "hclk_rkvenc_niu", "hclk_rkvenc", 0, RK3328_CLKGATE_CON(25), 1, GFLAGS), GATE(ACLK_H265, "aclk_h265", "aclk_rkvenc", 0, RK3328_CLKGATE_CON(25), 0, GFLAGS), @@ -709,14 +709,14 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = { /* PD_VOP */ GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 0, RK3328_CLKGATE_CON(21), 10, GFLAGS), - GATE(0, "aclk_rga_niu", "aclk_rga_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(22), 3, GFLAGS), + GATE(0, "aclk_rga_niu", "aclk_rga_pre", 0, RK3328_CLKGATE_CON(22), 3, GFLAGS), GATE(ACLK_VOP, "aclk_vop", "aclk_vop_pre", 0, RK3328_CLKGATE_CON(21), 2, GFLAGS), - GATE(0, "aclk_vop_niu", "aclk_vop_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(21), 4, GFLAGS), + GATE(0, "aclk_vop_niu", "aclk_vop_pre", 0, RK3328_CLKGATE_CON(21), 4, GFLAGS), GATE(ACLK_IEP, "aclk_iep", "aclk_vio_pre", 0, RK3328_CLKGATE_CON(21), 6, GFLAGS), GATE(ACLK_CIF, "aclk_cif", "aclk_vio_pre", 0, RK3328_CLKGATE_CON(21), 8, GFLAGS), GATE(ACLK_HDCP, "aclk_hdcp", "aclk_vio_pre", 0, RK3328_CLKGATE_CON(21), 15, GFLAGS), - GATE(0, "aclk_vio_niu", "aclk_vio_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(22), 2, GFLAGS), + GATE(0, "aclk_vio_niu", "aclk_vio_pre", 0, RK3328_CLKGATE_CON(22), 2, GFLAGS), GATE(HCLK_VOP, "hclk_vop", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(21), 3, GFLAGS), GATE(0, "hclk_vop_niu", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(21), 5, GFLAGS), @@ -743,19 +743,19 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = { GATE(HCLK_HOST0_ARB, "hclk_host0_arb", "hclk_peri", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(19), 7, GFLAGS), GATE(HCLK_OTG, "hclk_otg", "hclk_peri", 0, RK3328_CLKGATE_CON(19), 8, GFLAGS), GATE(HCLK_OTG_PMU, "hclk_otg_pmu", "hclk_peri", 0, RK3328_CLKGATE_CON(19), 9, GFLAGS), - GATE(0, "hclk_peri_niu", "hclk_peri", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(19), 12, GFLAGS), - GATE(0, "pclk_peri_niu", "hclk_peri", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(19), 13, GFLAGS), + GATE(0, "hclk_peri_niu", "hclk_peri", 0, RK3328_CLKGATE_CON(19), 12, GFLAGS), + GATE(0, "pclk_peri_niu", "hclk_peri", 0, RK3328_CLKGATE_CON(19), 13, GFLAGS), /* PD_GMAC */ GATE(ACLK_MAC2PHY, "aclk_mac2phy", "aclk_gmac", 0, RK3328_CLKGATE_CON(26), 0, GFLAGS), GATE(ACLK_MAC2IO, "aclk_mac2io", "aclk_gmac", 0, RK3328_CLKGATE_CON(26), 2, GFLAGS), - GATE(0, "aclk_gmac_niu", "aclk_gmac", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(26), 4, GFLAGS), + GATE(0, "aclk_gmac_niu", "aclk_gmac", 0, RK3328_CLKGATE_CON(26), 4, GFLAGS), GATE(PCLK_MAC2PHY, "pclk_mac2phy", "pclk_gmac", 0, RK3328_CLKGATE_CON(26), 1, GFLAGS), GATE(PCLK_MAC2IO, "pclk_mac2io", "pclk_gmac", 0, RK3328_CLKGATE_CON(26), 3, GFLAGS), - GATE(0, "pclk_gmac_niu", "pclk_gmac", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(26), 5, GFLAGS), + GATE(0, "pclk_gmac_niu", "pclk_gmac", 0, RK3328_CLKGATE_CON(26), 5, GFLAGS), /* PD_BUS */ - GATE(0, "aclk_bus_niu", "aclk_bus_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(15), 12, GFLAGS), + GATE(0, "aclk_bus_niu", "aclk_bus_pre", 0, RK3328_CLKGATE_CON(15), 12, GFLAGS), GATE(ACLK_DCF, "aclk_dcf", "aclk_bus_pre", 0, RK3328_CLKGATE_CON(15), 11, GFLAGS), GATE(ACLK_TSP, "aclk_tsp", "aclk_bus_pre", 0, RK3328_CLKGATE_CON(17), 12, GFLAGS), GATE(0, "aclk_intmem", "aclk_bus_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(15), 0, GFLAGS), @@ -769,10 +769,10 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = { GATE(HCLK_TSP, "hclk_tsp", "hclk_bus_pre", 0, RK3328_CLKGATE_CON(17), 11, GFLAGS), GATE(HCLK_CRYPTO_MST, "hclk_crypto_mst", "hclk_bus_pre", 0, RK3328_CLKGATE_CON(15), 7, GFLAGS), GATE(HCLK_CRYPTO_SLV, "hclk_crypto_slv", "hclk_bus_pre", 0, RK3328_CLKGATE_CON(15), 8, GFLAGS), - GATE(0, "hclk_bus_niu", "hclk_bus_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(15), 13, GFLAGS), + GATE(0, "hclk_bus_niu", "hclk_bus_pre", 0, RK3328_CLKGATE_CON(15), 13, GFLAGS), GATE(HCLK_PDM, "hclk_pdm", "hclk_bus_pre", 0, RK3328_CLKGATE_CON(28), 0, GFLAGS), - GATE(0, "pclk_bus_niu", "pclk_bus", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(15), 14, GFLAGS), + GATE(0, "pclk_bus_niu", "pclk_bus", 0, RK3328_CLKGATE_CON(15), 14, GFLAGS), GATE(0, "pclk_efuse", "pclk_bus", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(15), 9, GFLAGS), GATE(0, "pclk_otp", "pclk_bus", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(28), 4, GFLAGS), GATE(PCLK_I2C0, "pclk_i2c0", "pclk_bus", 0, RK3328_CLKGATE_CON(15), 10, GFLAGS), @@ -807,7 +807,7 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = { GATE(0, "pclk_acodecphy", "pclk_phy_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 5, GFLAGS), GATE(PCLK_HDMIPHY, "pclk_hdmiphy", "pclk_phy_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 7, GFLAGS), GATE(0, "pclk_vdacphy", "pclk_phy_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 8, GFLAGS), - GATE(0, "pclk_phy_niu", "pclk_phy_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(15), 15, GFLAGS), + GATE(0, "pclk_phy_niu", "pclk_phy_pre", 0, RK3328_CLKGATE_CON(15), 15, GFLAGS), /* PD_MMC */ MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "sclk_sdmmc", @@ -833,11 +833,16 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = { static const char *const rk3328_critical_clocks[] __initconst = { "aclk_bus", + "aclk_bus_niu", "pclk_bus", + "pclk_bus_niu", "hclk_bus", + "hclk_bus_niu", "aclk_peri", "hclk_peri", + "hclk_peri_niu", "pclk_peri", + "pclk_peri_niu", "pclk_dbg", "aclk_core_niu", "aclk_gic400", @@ -861,7 +866,20 @@ static const char *const rk3328_critical_clocks[] __initconst = { "aclk_rga_niu", "pclk_vio_h2p", "hclk_vio_h2p", + "aclk_vio_niu", "hclk_vio_niu", + "aclk_vop_niu", + "hclk_vop_niu", + "aclk_gpu_niu", + "aclk_rkvdec_niu", + "hclk_rkvdec_niu", + "aclk_vpu_niu", + "hclk_vpu_niu", + "aclk_rkvenc_niu", + "hclk_rkvenc_niu", + "aclk_gmac_niu", + "pclk_gmac_niu", + "pclk_phy_niu", }; static void __init rk3328_clk_init(struct device_node *np) -- 2.14.2 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 5/7] clk: rockchip: remove ignore_unused flag from rk3328 vio_h2p clocks 2018-01-22 14:15 [PATCH 0/7] clk: rockchip: rk3328 fixes in preparation of graphics support Heiko Stuebner ` (3 preceding siblings ...) 2018-01-22 14:15 ` [PATCH 4/7] clk: rockchip: protect all remaining rk3328 interconnect clocks Heiko Stuebner @ 2018-01-22 14:15 ` Heiko Stuebner 2018-01-22 14:15 ` [PATCH 6/7] clk: rockchip: add flags for rk3328 dclk_lcdc Heiko Stuebner ` (2 subsequent siblings) 7 siblings, 0 replies; 10+ messages in thread From: Heiko Stuebner @ 2018-01-22 14:15 UTC (permalink / raw) To: linux-clk Cc: mturquette, sboyd, linux-rockchip, robh+dt, mark.rutland, devicetree, yang.zheng, zhangqing, Heiko Stuebner These are already marked as critical, so there is no need for an additional ignore_unused flag. Signed-off-by: Heiko Stuebner <heiko@sntech.de> --- drivers/clk/rockchip/clk-rk3328.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/rockchip/clk-rk3328.c b/drivers/clk/rockchip/clk-rk3328.c index c5b381ab23b1..983ad5760ce0 100644 --- a/drivers/clk/rockchip/clk-rk3328.c +++ b/drivers/clk/rockchip/clk-rk3328.c @@ -724,8 +724,8 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = { GATE(HCLK_CIF, "hclk_cif", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(21), 9, GFLAGS), GATE(HCLK_RGA, "hclk_rga", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(21), 11, GFLAGS), GATE(0, "hclk_ahb1tom", "hclk_vio_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(21), 12, GFLAGS), - GATE(0, "pclk_vio_h2p", "hclk_vio_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(21), 13, GFLAGS), - GATE(0, "hclk_vio_h2p", "hclk_vio_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(21), 14, GFLAGS), + GATE(0, "pclk_vio_h2p", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(21), 13, GFLAGS), + GATE(0, "hclk_vio_h2p", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(21), 14, GFLAGS), GATE(HCLK_HDCP, "hclk_hdcp", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(22), 0, GFLAGS), GATE(0, "hclk_vio_niu", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(22), 1, GFLAGS), GATE(PCLK_HDMI, "pclk_hdmi", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(22), 4, GFLAGS), -- 2.14.2 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 6/7] clk: rockchip: add flags for rk3328 dclk_lcdc 2018-01-22 14:15 [PATCH 0/7] clk: rockchip: rk3328 fixes in preparation of graphics support Heiko Stuebner ` (4 preceding siblings ...) 2018-01-22 14:15 ` [PATCH 5/7] clk: rockchip: remove ignore_unused flag from rk3328 vio_h2p clocks Heiko Stuebner @ 2018-01-22 14:15 ` Heiko Stuebner 2018-01-22 14:15 ` [PATCH 7/7] clk: rockchip: document hdmi_phy external input for rk3328 Heiko Stuebner 2018-02-12 14:02 ` [PATCH 0/7] clk: rockchip: rk3328 fixes in preparation of graphics support Heiko Stuebner 7 siblings, 0 replies; 10+ messages in thread From: Heiko Stuebner @ 2018-01-22 14:15 UTC (permalink / raw) To: linux-clk Cc: mturquette, sboyd, linux-rockchip, robh+dt, mark.rutland, devicetree, yang.zheng, zhangqing, Zheng Yang, Heiko Stuebner From: Zheng Yang <zhengyang@rock-chips.com> dclk_lcdc can be sourced from a general pll source as well as the hdmiphy's pll output. We will want to set this source by hand (to the system-pll-source in most cases) and also want rate changes to this clock to be able to also touch the pll source clock if needed, so add CLK_SET_RATE_PARENT and CLK_SET_RATE_NO_REPARENT for dclk_lcdc. Signed-off-by: Zheng Yang <zhengyang@rock-chips.com> [ammended commit message] Signed-off-by: Heiko Stuebner <heiko@sntech.de> --- drivers/clk/rockchip/clk-rk3328.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/rockchip/clk-rk3328.c b/drivers/clk/rockchip/clk-rk3328.c index 983ad5760ce0..f680b421b6d5 100644 --- a/drivers/clk/rockchip/clk-rk3328.c +++ b/drivers/clk/rockchip/clk-rk3328.c @@ -602,7 +602,7 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = { RK3328_CLKGATE_CON(5), 6, GFLAGS), DIV(DCLK_HDMIPHY, "dclk_hdmiphy", "dclk_lcdc_src", 0, RK3328_CLKSEL_CON(40), 3, 3, DFLAGS), - MUX(DCLK_LCDC, "dclk_lcdc", mux_dclk_lcdc_p, 0, + MUX(DCLK_LCDC, "dclk_lcdc", mux_dclk_lcdc_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, RK3328_CLKSEL_CON(40), 1, 1, MFLAGS), /* -- 2.14.2 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 7/7] clk: rockchip: document hdmi_phy external input for rk3328 2018-01-22 14:15 [PATCH 0/7] clk: rockchip: rk3328 fixes in preparation of graphics support Heiko Stuebner ` (5 preceding siblings ...) 2018-01-22 14:15 ` [PATCH 6/7] clk: rockchip: add flags for rk3328 dclk_lcdc Heiko Stuebner @ 2018-01-22 14:15 ` Heiko Stuebner 2018-01-29 23:12 ` Rob Herring 2018-02-12 14:02 ` [PATCH 0/7] clk: rockchip: rk3328 fixes in preparation of graphics support Heiko Stuebner 7 siblings, 1 reply; 10+ messages in thread From: Heiko Stuebner @ 2018-01-22 14:15 UTC (permalink / raw) To: linux-clk Cc: mturquette, sboyd, linux-rockchip, robh+dt, mark.rutland, devicetree, yang.zheng, zhangqing, Heiko Stuebner The hdmi-phy block inside the soc also loops its pll output back into the clock controller, so document that already used input clock. Signed-off-by: Heiko Stuebner <heiko@sntech.de> --- Documentation/devicetree/bindings/clock/rockchip,rk3328-cru.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3328-cru.txt b/Documentation/devicetree/bindings/clock/rockchip,rk3328-cru.txt index e71c675ba5da..904ae682ea90 100644 --- a/Documentation/devicetree/bindings/clock/rockchip,rk3328-cru.txt +++ b/Documentation/devicetree/bindings/clock/rockchip,rk3328-cru.txt @@ -32,6 +32,7 @@ clock-output-names: - "clkin_i2s" - external I2S clock - optional, - "gmac_clkin" - external GMAC clock - optional - "phy_50m_out" - output clock of the pll in the mac phy + - "hdmi_phy" - output clock of the hdmi phy pll - optional Example: Clock controller node: -- 2.14.2 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH 7/7] clk: rockchip: document hdmi_phy external input for rk3328 2018-01-22 14:15 ` [PATCH 7/7] clk: rockchip: document hdmi_phy external input for rk3328 Heiko Stuebner @ 2018-01-29 23:12 ` Rob Herring 0 siblings, 0 replies; 10+ messages in thread From: Rob Herring @ 2018-01-29 23:12 UTC (permalink / raw) To: Heiko Stuebner Cc: linux-clk, mturquette, sboyd, linux-rockchip, mark.rutland, devicetree, yang.zheng, zhangqing On Mon, Jan 22, 2018 at 03:15:30PM +0100, Heiko Stuebner wrote: > The hdmi-phy block inside the soc also loops its pll output back > into the clock controller, so document that already used input clock. > > Signed-off-by: Heiko Stuebner <heiko@sntech.de> > --- > Documentation/devicetree/bindings/clock/rockchip,rk3328-cru.txt | 1 + > 1 file changed, 1 insertion(+) Reviewed-by: Rob Herring <robh@kernel.org> ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 0/7] clk: rockchip: rk3328 fixes in preparation of graphics support 2018-01-22 14:15 [PATCH 0/7] clk: rockchip: rk3328 fixes in preparation of graphics support Heiko Stuebner ` (6 preceding siblings ...) 2018-01-22 14:15 ` [PATCH 7/7] clk: rockchip: document hdmi_phy external input for rk3328 Heiko Stuebner @ 2018-02-12 14:02 ` Heiko Stuebner 7 siblings, 0 replies; 10+ messages in thread From: Heiko Stuebner @ 2018-02-12 14:02 UTC (permalink / raw) To: linux-clk Cc: mturquette, sboyd, linux-rockchip, robh+dt, mark.rutland, devicetree, yang.zheng, zhangqing Am Montag, 22. Januar 2018, 15:15:23 CET schrieb Heiko Stuebner: > Fix some clock issues on rk3328 to make way for the upcoming graphics > support on rk3328. > > Heiko Stuebner (6): > clk: rockchip: fix hclk_vio_niu on rk3328 > clk: rockchip: remove HCLK_VIO from rk3328 dt header > clk: rockchip: export sclk_hdmi_sfc on rk3328 > clk: rockchip: protect all remaining rk3328 interconnect clocks > clk: rockchip: remove ignore_unused flag from rk3328 vio_h2p clocks > clk: rockchip: document hdmi_phy external input for rk3328 > > Zheng Yang (1): > clk: rockchip: add flags for rk3328 dclk_lcdc applied for 4.17 ^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2018-02-12 14:02 UTC | newest] Thread overview: 10+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2018-01-22 14:15 [PATCH 0/7] clk: rockchip: rk3328 fixes in preparation of graphics support Heiko Stuebner 2018-01-22 14:15 ` [PATCH 1/7] clk: rockchip: fix hclk_vio_niu on rk3328 Heiko Stuebner 2018-01-22 14:15 ` [PATCH 2/7] clk: rockchip: remove HCLK_VIO from rk3328 dt header Heiko Stuebner 2018-01-22 14:15 ` [PATCH 3/7] clk: rockchip: export sclk_hdmi_sfc on rk3328 Heiko Stuebner 2018-01-22 14:15 ` [PATCH 4/7] clk: rockchip: protect all remaining rk3328 interconnect clocks Heiko Stuebner 2018-01-22 14:15 ` [PATCH 5/7] clk: rockchip: remove ignore_unused flag from rk3328 vio_h2p clocks Heiko Stuebner 2018-01-22 14:15 ` [PATCH 6/7] clk: rockchip: add flags for rk3328 dclk_lcdc Heiko Stuebner 2018-01-22 14:15 ` [PATCH 7/7] clk: rockchip: document hdmi_phy external input for rk3328 Heiko Stuebner 2018-01-29 23:12 ` Rob Herring 2018-02-12 14:02 ` [PATCH 0/7] clk: rockchip: rk3328 fixes in preparation of graphics support Heiko Stuebner
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