Re: [PATCH V1 4/8] pinctrl: qcom: Add IPQ9574 pinctrl driver

Konrad Dybcio
2023-01-25T23:51:52Z

On 24.01.2023 15:15, devi priya wrote:
> Add pinctrl definitions for the TLMM of IPQ9574
>
> Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
> Signed-off-by: devi priya <quic_devipriy@quicinc.com>
> ---
[...]

> +enum ipq9574_functions {
> + msm_mux_atest_char,
> + msm_mux_atest_char0,
> + msm_mux_atest_char1,
> + msm_mux_atest_char2,
> + msm_mux_atest_char3,
> + msm_mux_audio_pdm0,
> + msm_mux_audio_pdm1,
> + msm_mux_audio_pri,
> + msm_mux_audio_sec,
> + msm_mux_blsp0_spi,
> + msm_mux_blsp0_uart,
> + msm_mux_blsp1_i2c,
> + msm_mux_blsp1_spi,
> + msm_mux_blsp1_uart,
> + msm_mux_blsp2_i2c,
> + msm_mux_blsp2_spi,
> + msm_mux_blsp2_uart,
> + msm_mux_blsp3_i2c,
> + msm_mux_blsp3_spi,
> + msm_mux_blsp3_uart,
> + msm_mux_blsp4_i2c,
> + msm_mux_blsp4_spi,
> + msm_mux_blsp4_uart,
> + msm_mux_blsp5_i2c,
> + msm_mux_blsp5_uart,
> + msm_mux_cri_trng0,
> + msm_mux_cri_trng1,
> + msm_mux_cri_trng2,
> + msm_mux_cri_trng3,
> + msm_mux_cxc0,
> + msm_mux_cxc1,
> + msm_mux_dbg_out,
> + msm_mux_dwc_ddrphy,
> + msm_mux_gcc_plltest,
> + msm_mux_gcc_tlmm,
> + msm_mux_gpio,

> + msm_mux_mac00,
> + msm_mux_mac01,
> + msm_mux_mac10,
> + msm_mux_mac11,
msm_mux_mac?

> + msm_mux_mdc,
> + msm_mux_mdio,
> + msm_mux_pcie0_clk,
> + msm_mux_pcie0_wake,
> + msm_mux_pcie1_clk,
> + msm_mux_pcie1_wake,
> + msm_mux_pcie2_clk,
> + msm_mux_pcie2_wake,
> + msm_mux_pcie3_clk,
> + msm_mux_pcie3_wake,
> + msm_mux_prng_rosc0,
> + msm_mux_prng_rosc1,
> + msm_mux_prng_rosc2,
> + msm_mux_prng_rosc3,

> + msm_mux_pta1_0,
> + msm_mux_pta1_1,
> + msm_mux_pta1_2,
> + msm_mux_pta20,
> + msm_mux_pta21,
msm_mux_pta?

> + msm_mux_pwm00,
> + msm_mux_pwm01,
> + msm_mux_pwm02,
> + msm_mux_pwm03,
> + msm_mux_pwm04,
> + msm_mux_pwm10,
> + msm_mux_pwm11,
> + msm_mux_pwm12,
> + msm_mux_pwm13,
> + msm_mux_pwm14,
> + msm_mux_pwm20,
> + msm_mux_pwm21,
> + msm_mux_pwm22,
> + msm_mux_pwm23,
> + msm_mux_pwm24,
> + msm_mux_pwm30,
> + msm_mux_pwm31,
> + msm_mux_pwm32,
> + msm_mux_pwm33,
msm_mux_pwm?

[...]

> +
> +static const int ipq9574_reserved_gpios[] = {
> + 59, -1
> +};
We know it's necessary and it's good that you take care
of it, but it would be even nicer if you left a comment
explaining why the rx0/pwm23/qdss_tracedata_a gpio can
not be accessed and what it's used for.

Konrad
> +
> +static const struct msm_pinctrl_soc_data ipq9574_pinctrl = {
> + .pins = ipq9574_pins,
> + .npins = ARRAY_SIZE(ipq9574_pins),
> + .functions = ipq9574_functions,
> + .nfunctions = ARRAY_SIZE(ipq9574_functions),
> + .groups = ipq9574_groups,
> + .ngroups = ARRAY_SIZE(ipq9574_groups),
> + .reserved_gpios = ipq9574_reserved_gpios,
> + .ngpios = 65,
> +};
> +
> +static int ipq9574_pinctrl_probe(struct platform_device *pdev)
> +{
> + return msm_pinctrl_probe(pdev, &ipq9574_pinctrl);
> +}
> +
> +static const struct of_device_id ipq9574_pinctrl_of_match[] = {
> + { .compatible = "qcom,ipq9574-tlmm", },
> + { },
> +};
> +
> +static struct platform_driver ipq9574_pinctrl_driver = {
> + .driver = {
> + .name = "ipq9574-tlmm",
> + .of_match_table = ipq9574_pinctrl_of_match,
> + },
> + .probe = ipq9574_pinctrl_probe,
> + .remove = msm_pinctrl_remove,
> +};
> +
> +static int __init ipq9574_pinctrl_init(void)
> +{
> + return platform_driver_register(&ipq9574_pinctrl_driver);
> +}
> +arch_initcall(ipq9574_pinctrl_init);
> +
> +static void __exit ipq9574_pinctrl_exit(void)
> +{
> + platform_driver_unregister(&ipq9574_pinctrl_driver);
> +}
> +module_exit(ipq9574_pinctrl_exit);
> +
> +MODULE_DESCRIPTION("QTI IPQ9574 TLMM driver");
> +MODULE_LICENSE("GPL");
> +MODULE_DEVICE_TABLE(of, ipq9574_pinctrl_of_match);