From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
To: Chanho Park <chanho61.park@samsung.com>,
Sylwester Nawrocki <s.nawrocki@samsung.com>,
Tomasz Figa <tomasz.figa@gmail.com>,
Chanwoo Choi <cw00.choi@samsung.com>,
Alim Akhtar <alim.akhtar@samsung.com>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
Cc: Sam Protsenko <semen.protsenko@linaro.org>,
linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
linux-samsung-soc@vger.kernel.org
Subject: Re: [PATCH 03/12] clk: samsung: add top clock support for Exynos Auto v9 SoC
Date: Tue, 3 May 2022 11:13:37 +0200 [thread overview]
Message-ID: <42df6765-0589-bc34-7d20-a05ef3e2d057@linaro.org> (raw)
In-Reply-To: <20220502090230.12853-4-chanho61.park@samsung.com>
On 02/05/2022 11:02, Chanho Park wrote:
Thank you for your patch. There is something to discuss/improve.
> + MUX(MOUT_CLKCMU_NPU_BUS, "mout_clkcmu_npu_bus", mout_clkcmu_npu_bus_p,
> + CLK_CON_MUX_MUX_CLKCMU_NPU_BUS, 0, 3),
> +
> + /* PERIC0 */
> + MUX(MOUT_CLKCMU_PERIC0_BUS, "mout_clkcmu_peric0_bus",
> + mout_clkcmu_peric0_bus_p, CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS, 0, 1),
> + MUX(MOUT_CLKCMU_PERIC0_IP, "mout_clkcmu_peric0_ip",
> + mout_clkcmu_peric0_bus_p, CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP, 0, 1),
> +
> + /* PERIC1 */
> + MUX(MOUT_CLKCMU_PERIC1_BUS, "mout_clkcmu_peric1_bus",
> + mout_clkcmu_peric0_bus_p, CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS, 0, 1),
> + MUX(MOUT_CLKCMU_PERIC1_IP, "mout_clkcmu_peric1_ip",
> + mout_clkcmu_peric0_bus_p, CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP, 0, 1),
> +
> + /* PERIS */
> + MUX(MOUT_CLKCMU_PERIS_BUS, "mout_clkcmu_peris_bus",
> + mout_clkcmu_peric0_bus_p, CLK_CON_MUX_MUX_CLKCMU_PERIS_BUS, 0, 1),
> +
Unneeded blank line
> +};
> +
> +static const struct samsung_div_clock top_div_clks[] __initconst = {
> + /* CMU_TOP_PURECLKCOMP */
> + DIV(DOUT_SHARED0_DIV3, "dout_shared0_div3", "mout_shared0_pll",
> + CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2),
> + DIV(DOUT_SHARED0_DIV2, "dout_shared0_div2", "mout_shared0_pll",
> + CLK_CON_DIV_PLL_SHARED0_DIV2, 0, 1),
> +
> + DIV(DOUT_SHARED1_DIV3, "dout_shared1_div3", "mout_shared1_pll",
> + CLK_CON_DIV_PLL_SHARED1_DIV3, 0, 2),
> + DIV(DOUT_SHARED1_DIV2, "dout_shared1_div2", "mout_shared1_pll",
> + CLK_CON_DIV_PLL_SHARED1_DIV2, 0, 1),
> + DIV(DOUT_SHARED1_DIV4, "dout_shared1_div4", "dout_shared1_div2",
> + CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1),
> +
> + DIV(DOUT_SHARED2_DIV3, "dout_shared2_div3", "mout_shared2_pll",
> + CLK_CON_DIV_PLL_SHARED2_DIV3, 0, 2),
> + DIV(DOUT_SHARED2_DIV2, "dout_shared2_div2", "mout_shared2_pll",
> + CLK_CON_DIV_PLL_SHARED2_DIV2, 0, 1),
> + DIV(DOUT_SHARED2_DIV4, "dout_shared2_div4", "dout_shared2_div2",
> + CLK_CON_DIV_PLL_SHARED2_DIV4, 0, 1),
> +
> + DIV(DOUT_SHARED4_DIV2, "dout_shared4_div2", "mout_shared4_pll",
> + CLK_CON_DIV_PLL_SHARED4_DIV2, 0, 1),
> + DIV(DOUT_SHARED4_DIV4, "dout_shared4_div4", "dout_shared4_div2",
> + CLK_CON_DIV_PLL_SHARED4_DIV4, 0, 1),
> +
> + /* BOOST */
> + DIV(DOUT_CLKCMU_CMU_BOOST, "dout_clkcmu_cmu_boost",
> + "gout_clkcmu_cmu_boost", CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST, 0, 2),
> +
> + /* ACC */
> + DIV(DOUT_CLKCMU_ACC_BUS, "dout_clkcmu_acc_bus", "gout_clkcmu_acc_bus",
> + CLK_CON_DIV_CLKCMU_ACC_BUS, 0, 4),
> +
> + /* APM */
> + DIV(DOUT_CLKCMU_APM_BUS, "dout_clkcmu_apm_bus", "gout_clkcmu_apm_bus",
> + CLK_CON_DIV_CLKCMU_APM_BUS, 0, 3),
> +
> + /* AUD */
> + DIV(DOUT_CLKCMU_AUD_CPU, "dout_clkcmu_aud_cpu", "gout_clkcmu_aud_cpu",
> + CLK_CON_DIV_CLKCMU_AUD_CPU, 0, 3),
> + DIV(DOUT_CLKCMU_AUD_BUS, "dout_clkcmu_aud_bus", "gout_clkcmu_aud_bus",
> + CLK_CON_DIV_CLKCMU_AUD_BUS, 0, 4),
> +
> + /* BUSC */
> + DIV(DOUT_CLKCMU_BUSC_BUS, "dout_clkcmu_busc_bus",
> + "gout_clkcmu_busc_bus", CLK_CON_DIV_CLKCMU_BUSC_BUS, 0, 4),
> +
> + /* BUSMC */
> + DIV(DOUT_CLKCMU_BUSMC_BUS, "dout_clkcmu_busmc_bus",
> + "gout_clkcmu_busmc_bus", CLK_CON_DIV_CLKCMU_BUSMC_BUS, 0, 4),
> +
> + /* CORE */
> + DIV(DOUT_CLKCMU_CORE_BUS, "dout_clkcmu_core_bus",
> + "gout_clkcmu_core_bus", CLK_CON_DIV_CLKCMU_CORE_BUS, 0, 4),
> +
> + /* CPUCL0 */
> + DIV(DOUT_CLKCMU_CPUCL0_SWITCH, "dout_clkcmu_cpucl0_switch",
> + "gout_clkcmu_cpucl0_switch", CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH,
> + 0, 3),
> + DIV(DOUT_CLKCMU_CPUCL0_CLUSTER, "dout_clkcmu_cpucl0_cluster",
> + "gout_clkcmu_cpucl0_cluster", CLK_CON_DIV_CLKCMU_CPUCL0_CLUSTER,
> + 0, 3),
> +
> + /* CPUCL1 */
> + DIV(DOUT_CLKCMU_CPUCL1_SWITCH, "dout_clkcmu_cpucl1_switch",
> + "gout_clkcmu_cpucl1_switch", CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH,
> + 0, 3),
> + DIV(DOUT_CLKCMU_CPUCL1_CLUSTER, "dout_clkcmu_cpucl1_cluster",
> + "gout_clkcmu_cpucl1_cluster", CLK_CON_DIV_CLKCMU_CPUCL1_CLUSTER,
> + 0, 3),
> +
> + /* DPTX */
> + DIV(DOUT_CLKCMU_DPTX_BUS, "dout_clkcmu_dptx_bus",
> + "gout_clkcmu_dptx_bus", CLK_CON_DIV_CLKCMU_DPTX_BUS, 0, 4),
> + DIV(DOUT_CLKCMU_DPTX_DPGTC, "dout_clkcmu_dptx_dpgtc",
> + "gout_clkcmu_dptx_dpgtc", CLK_CON_DIV_CLKCMU_DPTX_DPGTC, 0, 3),
> +
> + /* DPUM */
> + DIV(DOUT_CLKCMU_DPUM_BUS, "dout_clkcmu_dpum_bus",
> + "gout_clkcmu_dpum_bus", CLK_CON_DIV_CLKCMU_DPUM_BUS, 0, 4),
> +
> + /* DPUS */
> + DIV(DOUT_CLKCMU_DPUS0_BUS, "dout_clkcmu_dpus0_bus",
> + "gout_clkcmu_dpus0_bus", CLK_CON_DIV_CLKCMU_DPUS0_BUS, 0, 4),
> + DIV(DOUT_CLKCMU_DPUS1_BUS, "dout_clkcmu_dpus1_bus",
> + "gout_clkcmu_dpus1_bus", CLK_CON_DIV_CLKCMU_DPUS1_BUS, 0, 4),
> +
> + /* FSYS0 */
> + DIV(DOUT_CLKCMU_FSYS0_BUS, "dout_clkcmu_fsys0_bus",
> + "gout_clkcmu_fsys0_bus", CLK_CON_DIV_CLKCMU_FSYS0_BUS, 0, 4),
> +
> + /* FSYS1 */
> + DIV(DOUT_CLKCMU_FSYS1_BUS, "dout_clkcmu_fsys1_bus",
> + "gout_clkcmu_fsys1_bus", CLK_CON_DIV_CLKCMU_FSYS1_BUS, 0, 4),
> + DIV(DOUT_CLKCMU_FSYS1_USBDRD, "dout_clkcmu_fsys1_usbdrd",
> + "gout_clkcmu_fsys1_usbdrd", CLK_CON_DIV_CLKCMU_FSYS1_USBDRD, 0, 4),
> +
> + /* FSYS2 */
> + DIV(DOUT_CLKCMU_FSYS2_BUS, "dout_clkcmu_fsys2_bus",
> + "gout_clkcmu_fsys2_bus", CLK_CON_DIV_CLKCMU_FSYS2_BUS, 0, 4),
> + DIV(DOUT_CLKCMU_FSYS2_UFS_EMBD, "dout_clkcmu_fsys2_ufs_embd",
> + "gout_clkcmu_fsys2_ufs_embd", CLK_CON_DIV_CLKCMU_FSYS2_UFS_EMBD,
> + 0, 3),
> + DIV(DOUT_CLKCMU_FSYS2_ETHERNET, "dout_clkcmu_fsys2_ethernet",
> + "gout_clkcmu_fsys2_ethernet", CLK_CON_DIV_CLKCMU_FSYS2_ETHERNET,
> + 0, 3),
> +
> + /* G2D */
> + DIV(DOUT_CLKCMU_G2D_G2D, "dout_clkcmu_g2d_g2d", "gout_clkcmu_g2d_g2d",
> + CLK_CON_DIV_CLKCMU_G2D_G2D, 0, 4),
> + DIV(DOUT_CLKCMU_G2D_MSCL, "dout_clkcmu_g2d_mscl",
> + "gout_clkcmu_g2d_mscl", CLK_CON_DIV_CLKCMU_G2D_MSCL, 0, 4),
> +
> + /* G3D0 */
> + DIV(DOUT_CLKCMU_G3D00_SWITCH, "dout_clkcmu_g3d00_switch",
> + "gout_clkcmu_g3d00_switch", CLK_CON_DIV_CLKCMU_G3D00_SWITCH, 0, 3),
> + DIV(DOUT_CLKCMU_G3D01_SWITCH, "dout_clkcmu_g3d01_switch",
> + "gout_clkcmu_g3d01_switch", CLK_CON_DIV_CLKCMU_G3D01_SWITCH, 0, 3),
> +
> + /* G3D1 */
> + DIV(DOUT_CLKCMU_G3D1_SWITCH, "dout_clkcmu_g3d1_switch",
> + "gout_clkcmu_g3d1_switch", CLK_CON_DIV_CLKCMU_G3D1_SWITCH, 0, 3),
> +
> + /* ISPB */
> + DIV(DOUT_CLKCMU_ISPB_BUS, "dout_clkcmu_ispb_bus",
> + "gout_clkcmu_ispb_bus", CLK_CON_DIV_CLKCMU_ISPB_BUS, 0, 4),
> +
> + /* MFC */
> + DIV(DOUT_CLKCMU_MFC_MFC, "dout_clkcmu_mfc_mfc", "gout_clkcmu_mfc_mfc",
> + CLK_CON_DIV_CLKCMU_MFC_MFC, 0, 4),
> + DIV(DOUT_CLKCMU_MFC_WFD, "dout_clkcmu_mfc_wfd", "gout_clkcmu_mfc_wfd",
> + CLK_CON_DIV_CLKCMU_MFC_WFD, 0, 4),
> +
> + /* MIF */
> + DIV(DOUT_CLKCMU_MIF_BUSP, "dout_clkcmu_mif_busp",
> + "gout_clkcmu_mif_busp", CLK_CON_DIV_CLKCMU_MIF_BUSP, 0, 4),
> +
> + /* NPU */
> + DIV(DOUT_CLKCMU_NPU_BUS, "dout_clkcmu_npu_bus", "gout_clkcmu_npu_bus",
> + CLK_CON_DIV_CLKCMU_NPU_BUS, 0, 4),
> +
> + /* PERIC0 */
> + DIV(DOUT_CLKCMU_PERIC0_BUS, "dout_clkcmu_peric0_bus",
> + "gout_clkcmu_peric0_bus", CLK_CON_DIV_CLKCMU_PERIC0_BUS, 0, 4),
> + DIV(DOUT_CLKCMU_PERIC0_IP, "dout_clkcmu_peric0_ip",
> + "gout_clkcmu_peric0_ip", CLK_CON_DIV_CLKCMU_PERIC0_IP, 0, 4),
> +
> + /* PERIC1 */
> + DIV(DOUT_CLKCMU_PERIC1_BUS, "dout_clkcmu_peric1_bus",
> + "gout_clkcmu_peric1_bus", CLK_CON_DIV_CLKCMU_PERIC1_BUS, 0, 4),
> + DIV(DOUT_CLKCMU_PERIC1_IP, "dout_clkcmu_peric1_ip",
> + "gout_clkcmu_peric1_ip", CLK_CON_DIV_CLKCMU_PERIC1_IP, 0, 4),
> +
> + /* PERIS */
> + DIV(DOUT_CLKCMU_PERIS_BUS, "dout_clkcmu_peris_bus",
> + "gout_clkcmu_peris_bus", CLK_CON_DIV_CLKCMU_PERIS_BUS, 0, 4),
> +};
> +
> +static
> +const
const goes to line above (with static).
struct samsung_fixed_factor_clock top_fixed_factor_clks[] __initconst = {
> + FFACTOR(DOUT_CLKCMU_FSYS0_PCIE, "dout_clkcmu_fsys0_pcie",
> + "gout_clkcmu_fsys0_pcie", 1, 4, 0),
> +};
> +
> +static const struct samsung_gate_clock top_gate_clks[] __initconst = {
> + /* BOOST */
> + GATE(GOUT_CLKCMU_CMU_BOOST, "gout_clkcmu_cmu_boost",
> + "mout_clkcmu_cmu_boost", CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST,
> + 21, 0, 0),
> +
> + GATE(GOUT_CLKCMU_CPUCL0_BOOST, "gout_clkcmu_cpucl0_boost",
> + "dout_cmu_boost", CLK_CON_GAT_CLKCMU_CMU_CPUCL0_BOOST, 21, 0, 0),
> + GATE(GOUT_CLKCMU_CPUCL1_BOOST, "gout_clkcmu_cpucl1_boost",
> + "dout_cmu_boost", CLK_CON_GAT_CLKCMU_CMU_CPUCL1_BOOST, 21, 0, 0),
> + GATE(GOUT_CLKCMU_CORE_BOOST, "gout_clkcmu_core_boost",
> + "dout_cmu_boost", CLK_CON_GAT_CLKCMU_CMU_CORE_BOOST, 21, 0, 0),
> + GATE(GOUT_CLKCMU_BUSC_BOOST, "gout_clkcmu_busc_boost",
> + "dout_cmu_boost", CLK_CON_GAT_CLKCMU_CMU_BUSC_BOOST, 21, 0, 0),
> +
> + GATE(GOUT_CLKCMU_BUSMC_BOOST, "gout_clkcmu_busmc_boost",
> + "dout_cmu_boost", CLK_CON_GAT_CLKCMU_CMU_BUSMC_BOOST, 21, 0, 0),
> + GATE(GOUT_CLKCMU_MIF_BOOST, "gout_clkcmu_mif_boost", "dout_cmu_boost",
> + CLK_CON_GAT_CLKCMU_CMU_MIF_BOOST, 21, 0, 0),
> +
> + /* ACC */
> + GATE(GOUT_CLKCMU_ACC_BUS, "gout_clkcmu_acc_bus", "mout_clkcmu_acc_bus",
> + CLK_CON_GAT_GATE_CLKCMU_ACC_BUS, 21, 0, 0),
> +
> + /* APM */
> + GATE(GOUT_CLKCMU_APM_BUS, "gout_clkcmu_apm_bus", "mout_clkcmu_apm_bus",
> + CLK_CON_GAT_GATE_CLKCMU_APM_BUS, 21, CLK_IGNORE_UNUSED, 0),
> +
> + /* AUD */
> + GATE(GOUT_CLKCMU_AUD_CPU, "gout_clkcmu_aud_cpu", "mout_clkcmu_aud_cpu",
> + CLK_CON_GAT_GATE_CLKCMU_AUD_CPU, 21, 0, 0),
> + GATE(GOUT_CLKCMU_AUD_BUS, "gout_clkcmu_aud_bus", "mout_clkcmu_aud_bus",
> + CLK_CON_GAT_GATE_CLKCMU_AUD_BUS, 21, 0, 0),
> +
> + /* BUSC */
> + GATE(GOUT_CLKCMU_BUSC_BUS, "gout_clkcmu_busc_bus",
> + "mout_clkcmu_busc_bus", CLK_CON_GAT_GATE_CLKCMU_BUSC_BUS, 21,
> + CLK_IS_CRITICAL, 0),
> +
> + /* BUSMC */
> + GATE(GOUT_CLKCMU_BUSMC_BUS, "gout_clkcmu_busmc_bus",
> + "mout_clkcmu_busmc_bus", CLK_CON_GAT_GATE_CLKCMU_BUSMC_BUS, 21,
> + CLK_IS_CRITICAL, 0),
> +
> + /* CORE */
> + GATE(GOUT_CLKCMU_CORE_BUS, "gout_clkcmu_core_bus",
> + "mout_clkcmu_core_bus", CLK_CON_GAT_GATE_CLKCMU_CORE_BUS,
> + 21, 0, 0),
> +
> + /* CPUCL0 */
> + GATE(GOUT_CLKCMU_CPUCL0_SWITCH, "gout_clkcmu_cpucl0_switch",
> + "mout_clkcmu_cpucl0_switch",
> + CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH, 21, CLK_IGNORE_UNUSED, 0),
> + GATE(GOUT_CLKCMU_CPUCL0_CLUSTER, "gout_clkcmu_cpucl0_cluster",
> + "mout_clkcmu_cpucl0_cluster",
> + CLK_CON_GAT_GATE_CLKCMU_CPUCL0_CLUSTER, 21, CLK_IGNORE_UNUSED, 0),
> +
> + /* CPUCL1 */
> + GATE(GOUT_CLKCMU_CPUCL1_SWITCH, "gout_clkcmu_cpucl1_switch",
> + "mout_clkcmu_cpucl1_switch",
> + CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH, 21, CLK_IGNORE_UNUSED, 0),
> + GATE(GOUT_CLKCMU_CPUCL1_CLUSTER, "gout_clkcmu_cpucl1_cluster",
> + "mout_clkcmu_cpucl1_cluster",
> + CLK_CON_GAT_GATE_CLKCMU_CPUCL1_CLUSTER, 21, CLK_IGNORE_UNUSED, 0),
> +
> + /* DPTX */
> + GATE(GOUT_CLKCMU_DPTX_BUS, "gout_clkcmu_dptx_bus",
> + "mout_clkcmu_dptx_bus", CLK_CON_GAT_GATE_CLKCMU_DPTX_BUS,
> + 21, 0, 0),
> + GATE(GOUT_CLKCMU_DPTX_DPGTC, "gout_clkcmu_dptx_dpgtc",
> + "mout_clkcmu_dptx_dpgtc", CLK_CON_GAT_GATE_CLKCMU_DPTX_DPGTC,
> + 21, 0, 0),
> +
> + /* DPUM */
> + GATE(GOUT_CLKCMU_DPUM_BUS, "gout_clkcmu_dpum_bus",
> + "mout_clkcmu_dpum_bus", CLK_CON_GAT_GATE_CLKCMU_DPUM_BUS,
> + 21, 0, 0),
> +
> + /* DPUS */
> + GATE(GOUT_CLKCMU_DPUS0_BUS, "gout_clkcmu_dpus0_bus",
> + "mout_clkcmu_dpus0_bus", CLK_CON_GAT_GATE_CLKCMU_DPUS0_BUS,
> + 21, 0, 0),
> + GATE(GOUT_CLKCMU_DPUS1_BUS, "gout_clkcmu_dpus1_bus",
> + "mout_clkcmu_dpus1_bus", CLK_CON_GAT_GATE_CLKCMU_DPUS1_BUS,
> + 21, 0, 0),
> +
> + /* FSYS0 */
> + GATE(GOUT_CLKCMU_FSYS0_BUS, "gout_clkcmu_fsys0_bus",
> + "mout_clkcmu_fsys0_bus", CLK_CON_GAT_GATE_CLKCMU_FSYS0_BUS,
> + 21, 0, 0),
> + GATE(GOUT_CLKCMU_FSYS0_PCIE, "gout_clkcmu_fsys0_pcie",
> + "mout_clkcmu_fsys0_pcie", CLK_CON_GAT_GATE_CLKCMU_FSYS0_PCIE,
> + 21, 0, 0),
> +
> + /* FSYS1 */
> + GATE(GOUT_CLKCMU_FSYS1_BUS, "gout_clkcmu_fsys1_bus",
> + "mout_clkcmu_fsys1_bus", CLK_CON_GAT_GATE_CLKCMU_FSYS1_BUS,
> + 21, 0, 0),
> + GATE(GOUT_CLKCMU_FSYS1_USBDRD, "gout_clkcmu_fsys1_usbdrd",
> + "mout_clkcmu_fsys1_usbdrd", CLK_CON_GAT_GATE_CLKCMU_FSYS1_USBDRD,
> + 21, 0, 0),
> + GATE(GOUT_CLKCMU_FSYS1_MMC_CARD, "gout_clkcmu_fsys1_mmc_card",
> + "mout_clkcmu_fsys1_mmc_card",
> + CLK_CON_GAT_GATE_CLKCMU_FSYS1_MMC_CARD, 21, 0, 0),
> +
> + /* FSYS2 */
> + GATE(GOUT_CLKCMU_FSYS2_BUS, "gout_clkcmu_fsys2_bus",
> + "mout_clkcmu_fsys2_bus", CLK_CON_GAT_GATE_CLKCMU_FSYS2_BUS,
> + 21, 0, 0),
> + GATE(GOUT_CLKCMU_FSYS2_UFS_EMBD, "gout_clkcmu_fsys2_ufs_embd",
> + "mout_clkcmu_fsys2_ufs_embd",
> + CLK_CON_GAT_GATE_CLKCMU_FSYS2_UFS_EMBD, 21, 0, 0),
> + GATE(GOUT_CLKCMU_FSYS2_ETHERNET, "gout_clkcmu_fsys2_ethernet",
> + "mout_clkcmu_fsys2_ethernet",
> + CLK_CON_GAT_GATE_CLKCMU_FSYS2_ETHERNET, 21, 0, 0),
> +
> + /* G2D */
> + GATE(GOUT_CLKCMU_G2D_G2D, "gout_clkcmu_g2d_g2d",
> + "mout_clkcmu_g2d_g2d", CLK_CON_GAT_GATE_CLKCMU_G2D_G2D, 21, 0, 0),
> + GATE(GOUT_CLKCMU_G2D_MSCL, "gout_clkcmu_g2d_mscl",
> + "mout_clkcmu_g2d_mscl", CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL,
> + 21, 0, 0),
> +
> + /* G3D0 */
> + GATE(GOUT_CLKCMU_G3D00_SWITCH, "gout_clkcmu_g3d00_switch",
> + "mout_clkcmu_g3d00_switch", CLK_CON_GAT_GATE_CLKCMU_G3D00_SWITCH,
> + 21, 0, 0),
> + GATE(GOUT_CLKCMU_G3D01_SWITCH, "gout_clkcmu_g3d01_switch",
> + "mout_clkcmu_g3d01_switch", CLK_CON_GAT_GATE_CLKCMU_G3D01_SWITCH,
> + 21, 0, 0),
> +
> + /* G3D1 */
> + GATE(GOUT_CLKCMU_G3D1_SWITCH, "gout_clkcmu_g3d1_switch",
> + "mout_clkcmu_g3d1_switch", CLK_CON_GAT_GATE_CLKCMU_G3D1_SWITCH,
> + 21, 0, 0),
> +
> + /* ISPB */
> + GATE(GOUT_CLKCMU_ISPB_BUS, "gout_clkcmu_ispb_bus",
> + "mout_clkcmu_ispb_bus", CLK_CON_GAT_GATE_CLKCMU_ISPB_BUS,
> + 21, 0, 0),
> +
> + /* MFC */
> + GATE(GOUT_CLKCMU_MFC_MFC, "gout_clkcmu_mfc_mfc", "mout_clkcmu_mfc_mfc",
> + CLK_CON_GAT_GATE_CLKCMU_MFC_MFC, 21, 0, 0),
> + GATE(GOUT_CLKCMU_MFC_WFD, "gout_clkcmu_mfc_wfd", "mout_clkcmu_mfc_wfd",
> + CLK_CON_GAT_GATE_CLKCMU_MFC_WFD, 21, 0, 0),
> +
> + /* MIF */
> + GATE(GOUT_CLKCMU_MIF_SWITCH, "gout_clkcmu_mif_switch",
> + "mout_clkcmu_mif_switch", CLK_CON_GAT_GATE_CLKCMU_MIF_SWITCH,
> + 21, CLK_IGNORE_UNUSED, 0),
> + GATE(GOUT_CLKCMU_MIF_BUSP, "gout_clkcmu_mif_busp",
> + "mout_clkcmu_mif_busp", CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP,
> + 21, CLK_IGNORE_UNUSED, 0),
> +
> + /* NPU */
> + GATE(GOUT_CLKCMU_NPU_BUS, "gout_clkcmu_npu_bus", "mout_clkcmu_npu_bus",
> + CLK_CON_GAT_GATE_CLKCMU_NPU_BUS, 21, 0, 0),
> +
> + /* PERIC0 */
> + GATE(GOUT_CLKCMU_PERIC0_BUS, "gout_clkcmu_peric0_bus",
> + "mout_clkcmu_peric0_bus", CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS,
> + 21, 0, 0),
> + GATE(GOUT_CLKCMU_PERIC0_IP, "gout_clkcmu_peric0_ip",
> + "mout_clkcmu_peric0_ip", CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP,
> + 21, 0, 0),
> +
> + /* PERIC1 */
> + GATE(GOUT_CLKCMU_PERIC1_BUS, "gout_clkcmu_peric1_bus",
> + "mout_clkcmu_peric1_bus", CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS,
> + 21, 0, 0),
> + GATE(GOUT_CLKCMU_PERIC1_IP, "gout_clkcmu_peric1_ip",
> + "mout_clkcmu_peric1_ip", CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP,
> + 21, 0, 0),
> +
> + /* PERIS */
> + GATE(GOUT_CLKCMU_PERIS_BUS, "gout_clkcmu_peris_bus",
> + "mout_clkcmu_peris_bus", CLK_CON_GAT_GATE_CLKCMU_PERIS_BUS,
> + 21, CLK_IGNORE_UNUSED, 0),
> +
unneeded blank line
Best regards,
Krzysztof
next prev parent reply other threads:[~2022-05-03 9:13 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <CGME20220502090100epcas2p16b7838ebe7831adbe9daa05822b45b82@epcas2p1.samsung.com>
2022-05-02 9:02 ` [PATCH 00/12] initial clock support for exynosauto v9 SoC Chanho Park
2022-05-02 9:02 ` [PATCH 01/12] dt-bindings: clock: add Exynos Auto v9 SoC CMU bindings Chanho Park
2022-05-02 15:33 ` Rob Herring
2022-05-02 23:25 ` Chanho Park
2022-05-03 9:07 ` Krzysztof Kozlowski
2022-05-03 10:06 ` Chanho Park
2022-05-02 9:02 ` [PATCH 02/12] dt-bindings: clock: add clock binding definitions for Exynos Auto v9 Chanho Park
2022-05-03 9:08 ` Krzysztof Kozlowski
2022-05-03 10:08 ` Chanho Park
2022-05-02 9:02 ` [PATCH 03/12] clk: samsung: add top clock support for Exynos Auto v9 SoC Chanho Park
2022-05-03 9:13 ` Krzysztof Kozlowski [this message]
2022-05-03 10:24 ` Chanho Park
2022-05-02 9:02 ` [PATCH 04/12] clk: samsung: exynosautov9: add cmu_core clock support Chanho Park
2022-05-03 9:14 ` Krzysztof Kozlowski
2022-05-02 9:02 ` [PATCH 05/12] clk: samsung: exynosautov9: add cmu_peris " Chanho Park
2022-05-03 9:15 ` Krzysztof Kozlowski
2022-05-02 9:02 ` [PATCH 06/12] clk: samsung: exynosautov9: add cmu_busmc " Chanho Park
2022-05-03 9:16 ` Krzysztof Kozlowski
2022-05-02 9:02 ` [PATCH 07/12] clk: samsung: exynosautov9: add cmu_fsys2 " Chanho Park
2022-05-03 9:16 ` Krzysztof Kozlowski
2022-05-02 9:02 ` [PATCH 08/12] clk: samsung: exynosautov9: add cmu_peric0 " Chanho Park
2022-05-03 9:17 ` Krzysztof Kozlowski
2022-05-02 9:02 ` [PATCH 09/12] clk: samsung: exynosautov9: add cmu_peric1 " Chanho Park
2022-05-03 9:17 ` Krzysztof Kozlowski
2022-05-02 9:02 ` [PATCH 10/12] arm64: dts: exynosautov9: add initial cmu clock nodes Chanho Park
2022-05-03 9:20 ` Krzysztof Kozlowski
2022-05-03 9:55 ` Chanho Park
2022-05-02 9:02 ` [PATCH 11/12] arm64: dts: exynosautov9: switch usi clocks Chanho Park
2022-05-02 9:02 ` [PATCH 12/12] arm64: dts: exynosautov9: switch ufs clock node Chanho Park
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