From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: From: Jernej =?utf-8?B?xaBrcmFiZWM=?= To: Chen-Yu Tsai Cc: Rob Herring , Maxime Ripard , Mark Rutland , Mike Turquette , Stephen Boyd , David Airlie , Archit Taneja , Andrzej Hajda , devicetree , linux-arm-kernel , linux-kernel , linux-clk , dri-devel , linux-sunxi Subject: Re: [PATCH 05/27] clk: sunxi-ng: Use u64 for calculation of NM rate Date: Tue, 04 Sep 2018 20:06:52 +0200 Message-ID: <4377030.YGBN1y1aZP@jernej-laptop> In-Reply-To: References: <20180902072643.4917-1-jernej.skrabec@siol.net> <20180902072643.4917-6-jernej.skrabec@siol.net> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" List-ID: Dne torek, 04. september 2018 ob 11:18:47 CEST je Chen-Yu Tsai napisal(a): > On Sun, Sep 2, 2018 at 3:27 PM Jernej Skrabec wrote: > > Allwinner H6 SoC has multiplier N range between 1 and 254. Since parent > > rate is 24MHz, intermediate result when calculating final rate easily > > overflows 32 bit variable. > > > > Because of that, introduce function for calculating clock rate which > > uses 64 bit variable for intermediate result. > > > > Signed-off-by: Jernej Skrabec > > The code looks good. The A80's Video PLLs are also affected by this. > The range for N on the A80 is 12 ~ 255. > > Can you add fixes and stable tags? Sure. > > ChenYu