From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5D7D3C00140 for ; Tue, 2 Aug 2022 07:07:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235644AbiHBHHI (ORCPT ); Tue, 2 Aug 2022 03:07:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46864 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235480AbiHBHGm (ORCPT ); Tue, 2 Aug 2022 03:06:42 -0400 Received: from mail-lj1-x22e.google.com (mail-lj1-x22e.google.com [IPv6:2a00:1450:4864:20::22e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 69693183B0 for ; Tue, 2 Aug 2022 00:06:35 -0700 (PDT) Received: by mail-lj1-x22e.google.com with SMTP id z4so2826ljn.8 for ; Tue, 02 Aug 2022 00:06:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :from:to:cc; bh=YyBYmLXFn5IFerrIXB88rk828Nzxi3yZBlN5vWZi/gM=; b=cqShYtc7B4W7+q0vK7VkTMRnsYgBNGzLw6e2P8pZuRkHXrMnlMerLmoE/2weJs4sSA ocXKFpxuWtWtb1fhSYbnxLu9yBchBRsggPdcY+GsiMqQxQzl00PcrID3nMwsn5j9ljUn Q2q45sZ0s6MZWe2aMQmOCqU3abPyz7zyeyliIBvgJZlj/OJ2VmjEBuPNg2NKYSZqJV2f Ba5lIM6m2qZ7Q8GEkOJJ7xmwxGbFeEGtWqzPlCAIjZVbwXph3xyaIznRTbSr/mrwh18N idKySTQiWRH+Y6UU3DZwyzzDiy5UABGQzp8uHK8B+9SG0ZaLpx4iZXISVU0aDf2GPW/L sVsQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :x-gm-message-state:from:to:cc; bh=YyBYmLXFn5IFerrIXB88rk828Nzxi3yZBlN5vWZi/gM=; b=YhrKvAAE/TThn68euqPenrOR8fUNPGq2k2xkVN1HtJCv68sOGrzxB8/YbM+KC33Fiw 8qpMKtJ1bN4VOwHro3GuOJPLLqQvnWSAf/Gqd3BpYVn4j55bpPq4fFVta/HogBWOnwad Ufpvv/ylpTd9XNyn/2L3WQIK93vVlUlc3R2DuGCla3yqvEZLqnki2RgB5Z8iSVKcg1J2 Y1sy9ZrqHW/rVOPLLRmNvQkfKs/xbzsEOxCZkOFbUb291IXeV7Iy8USZ+luzfA+9XpD3 SAPFTujZSDb3rPW9F8+pesxEcgkyyp3wBknhj6mWI9vKLn7NzmuzCAxignK3jvPnJIKp Dy0w== X-Gm-Message-State: AJIora/bs4BXa41MCByARQ1+9R14mdXqyvUdgCUaZNvAlGs6YWHQLsCn xtqXoubvF2P4m1ak+yfTP7ek8A== X-Google-Smtp-Source: AGRyM1vyFzsFMTCPRJxtHWx7y5a7FMF92v+tAByHTMxUB/MOjUpdCznNzN7CY7oLLyxTnSAivEK0hg== X-Received: by 2002:a2e:bd0a:0:b0:25d:d2a3:7366 with SMTP id n10-20020a2ebd0a000000b0025dd2a37366mr6103917ljq.35.1659423993628; Tue, 02 Aug 2022 00:06:33 -0700 (PDT) Received: from [192.168.1.211] ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id e1-20020a05651236c100b0048afa5daaf3sm629717lfs.123.2022.08.02.00.06.32 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 02 Aug 2022 00:06:33 -0700 (PDT) Message-ID: <43d19449-cf06-2302-b536-4ade5f79c5fd@linaro.org> Date: Tue, 2 Aug 2022 10:06:32 +0300 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.10.0 Subject: Re: [PATCH 2/5] clk: qcom: Allow custom reset ops Content-Language: en-GB To: Akhil P Oommen , freedreno , dri-devel@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, Rob Clark , Bjorn Andersson , Stephen Boyd Cc: Douglas Anderson , Andy Gross , Konrad Dybcio , Michael Turquette , Philipp Zabel , Stephen Boyd , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org References: <1659172664-10345-1-git-send-email-quic_akhilpo@quicinc.com> <20220730144713.2.I4b69f984a97535179acd9637426a1331f84f6646@changeid> From: Dmitry Baryshkov In-Reply-To: <20220730144713.2.I4b69f984a97535179acd9637426a1331f84f6646@changeid> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org On 30/07/2022 12:17, Akhil P Oommen wrote: > Add support to allow soc specific clk drivers to specify a custom reset > operation. A consumer-driver of the reset framework can call > "reset_control_reset()" api to trigger this. > > Signed-off-by: Akhil P Oommen > --- > > drivers/clk/qcom/reset.c | 6 ++++++ > drivers/clk/qcom/reset.h | 2 ++ > 2 files changed, 8 insertions(+) > > diff --git a/drivers/clk/qcom/reset.c b/drivers/clk/qcom/reset.c > index 819d194..4782bf1 100644 > --- a/drivers/clk/qcom/reset.c > +++ b/drivers/clk/qcom/reset.c > @@ -13,6 +13,12 @@ > > static int qcom_reset(struct reset_controller_dev *rcdev, unsigned long id) > { > + struct qcom_reset_controller *rst = to_qcom_reset_controller(rcdev); > + const struct qcom_reset_map *map = &rst->reset_map[id]; > + > + if (map->op) > + return map->op(map); This looks like a hack. For example, assert() and deassert() would still follow the usual pattern of updating the bits. Please at least make them return -EOPNOTSUP if map->op is defined. A slightly better solution would be to make qcom_reset implementation optional (and depending on desc->num_resets being greater than 0). Then you can register your own reset controller implementation from the gpucc driver. > + > rcdev->ops->assert(rcdev, id); > udelay(1); > rcdev->ops->deassert(rcdev, id); > diff --git a/drivers/clk/qcom/reset.h b/drivers/clk/qcom/reset.h > index 2a08b5e..295deeb 100644 > --- a/drivers/clk/qcom/reset.h > +++ b/drivers/clk/qcom/reset.h > @@ -11,6 +11,8 @@ > struct qcom_reset_map { > unsigned int reg; > u8 bit; > + int (*op)(const struct qcom_reset_map *map); > + void *priv; > }; > > struct regmap; -- With best wishes Dmitry