Re: [PATCH v2 03/11] doc/devicetree: Add Aspeed clock bindings

["Heiko Stübner" <heiko@sntech.de>]

Hi Joel,

Am Mittwoch, 27. April 2016, 18:01:00 schrieb Joel Stanley:
> On Thu, Apr 21, 2016 at 8:50 PM, Heiko St=FCbner <heiko@sntech.de> wr=
ote:
> > [+clock-related patches should include clock-maintainers and lists]=

>=20
> Thanks.
>=20
> > Am Donnerstag, 21. April 2016, 17:34:01 schrieb Joel Stanley:
> >> +For example:
> >> +
> >> +     clk_clkin: clk_clkin {
> >> +             #clock-cells =3D <0>;
> >> +             compatible =3D "fixed-clock";
> >> +             clock-frequency =3D <48000000>;
> >> +     };
> >> +
> >> +     clk_hpll: clk_hpll {
> >> +             compatible =3D "aspeed,g4-hpll-clock";
> >> +             #clock-cells =3D <0>;
> >> +             reg =3D <0x1e6e2008 0x4>;
> >> +     };
> >> +
> >> +     clk_apb: clk_apb@1e6e2008 {
> >> +             #clock-cells =3D <0>;
> >> +             compatible =3D "aspeed,g4-apb-clock";
> >> +             reg =3D <0x1e6e2008 0x4>;
> >> +             clocks =3D <&clk_hpll>;
> >> +     };
> >=20
> > You have both the hpll and apb_clk in the same register (probably e=
ven
> > more
> > clocks?) and separate clock instances where each instance will of_i=
omap
> > the
> > register itself (and thus multiple times in general).
>=20
> Yep. I agree that's not ideal.
>=20
> > From what I remember exposing the clock controller as one block (in=
stead
> > of
> > declaring each clock individually in the dts) is still the preferre=
d way
> > but I don't think I can find Mike's mail from back then easily.
>=20
> I can't picture how that would look. I took my lead from the moxart
> clock driver; is there a better example that I should follow?

qcom, samsung, rockchip, hisilicon, imx, ...

I guess the design would depend on the actual layout of your clock- / s=
ystem-
controller - aka what else is contained there.


Heiko