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Fri, 19 Jun 2026 07:31:46 -0700 (PDT) X-Received: by 2002:a05:6830:410c:b0:7e6:6f9f:7446 with SMTP id 46e09a7af769-7e92d9d0f71mr1516270a34.4.1781879506460; Fri, 19 Jun 2026 07:31:46 -0700 (PDT) Received: from [192.168.120.170] ([178.235.128.140]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c0a9a1568dcsm92462266b.51.2026.06.19.07.31.43 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 19 Jun 2026 07:31:45 -0700 (PDT) Message-ID: <45163c0b-e33f-4080-a424-9d0d8942a533@oss.qualcomm.com> Date: Fri, 19 Jun 2026 16:31:42 +0200 Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 08/11] clk: qcom: dispcc-sm8250: Enable parents for pixel clocks To: Marek Szyprowski , Val Packett , Bjorn Andersson , Michael Turquette , Stephen Boyd , Jonathan Marek Cc: Konrad Dybcio , Johan Hovold , Manivannan Sadhasivam , Dmitry Baryshkov , Maximilian Luz , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260312112321.370983-1-val@packett.cool> <20260312112321.370983-9-val@packett.cool> <2f5b98a4-80a6-4611-9615-ab0202a8c455@samsung.com> <6e0d6119-c7ef-40d8-bf0f-6a5b6f6b00cf@samsung.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Authority-Analysis: v=2.4 cv=RZWgzVtv c=1 sm=1 tr=0 ts=6a3552d3 cx=c_pps a=z9lCQkyTxNhZyzAvolXo/A==:117 a=PRfkaYvzSr8QmIIGAkY2Sg==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=CBy3kSv35Q_usJoEGC8A:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=EyFUmsFV_t8cxB2kMr4A:22 X-Proofpoint-ORIG-GUID: 3talIOtMfgeUmPtmazHINSrpUuMGRO9K X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjE5MDEzNyBTYWx0ZWRfX/mIe29aRYDax 0U7yRAD+U/5dIL2aHQF+0ifl2HcvaRdmi2FurT/xZFyCJgdPio6OcsHdH438+i0unOaKNoj+lyv 6gdGGpp5DVMUx/TO/lqJgQX+4reqmOtTUDW4JRBnGKIYBZiIf7oHHLg+BIeR/ngY3fDWf/tp7kq NIzMDac5/3rEvuOkKb0a/LeEfeseIxkVqhTChGQl3BBFjlCkIiPG+KmirqhBqbCbyDkosHJ42+g WYWh8eS56WSGbH6cQszGv/ROXOjXCOFF8+ixIoqY3JntBusrm/sv+v8VsDMAz0JnWIbmcKkHPS1 zffOKAcaQ1h+sJjtlhQIWE2HXLPQm893GpuBikzuJfLu8tUZ1AxFq5vqH//0H92bhv4sYTu26VL 8x1gXo281wX0Ef0uzKQNKg4sHW9q9mDmTKuax83p4TH8vSkr7RFC1o+yrmkKoNC1jgs45kS09J/ LTiqbLUc3pkmd44wcgA== X-Proofpoint-GUID: 3talIOtMfgeUmPtmazHINSrpUuMGRO9K X-Proofpoint-Spam-Info: AW1haW4tMjYwNjE5MDEzNyBTYWx0ZWRfX9zP5GZwUPWYa FPYL+xehniY+A7yLLfnDrlawZgOu78geKQC7yxasWtwnWiryy2RNudJ5tHHxtRnIFW4r+v6kuHJ nZbs1z4YGmHxUiItswc2K9INLN6u/m0= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-19_03,2026-06-18_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 malwarescore=0 clxscore=1015 suspectscore=0 lowpriorityscore=0 priorityscore=1501 adultscore=0 bulkscore=0 phishscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2606190137 On 6/18/26 1:37 PM, Marek Szyprowski wrote: > On 16.06.2026 16:31, Marek Szyprowski wrote: >> On 16.06.2026 13:33, Konrad Dybcio wrote: >>> On 3/20/26 12:32 PM, Marek Szyprowski wrote: >>>> On 12.03.2026 12:12, Val Packett wrote: >>>>> Add CLK_OPS_PARENT_ENABLE to MDSS pixel clock sources to ensure parent >>>>> clocks are enabled during clock operations, preventing potential >>>>> stability issues during display configuration. >>>>> >>>>> Fixes: 80a18f4a8567 ("clk: qcom: Add display clock controller driver for SM8150 and SM8250") >>>>> Signed-off-by: Val Packett >>>> This patch landed in yesterday's linux-next as commit. In my tests I >>>> found that it triggers the following warning on RB5 board: >>> Hi, I was clearing out my inbox.. Is this still happening on the latest >>> next? >> Yes, still happens here with next-20260615. > > > I've just played a bit with that code and RB5 board and found that this issue > happens, because enabling the DSI PLL clock fails for unknown reason. > > > Here is what happens just before the warnings (I've missed that in the initial > report): > > DSI PLL(0) lock failed, status=0x00000000 > PLL(0) lock failed > > It looks that the generic clock code doesn't take care to properly balance > enable/disable in __clk_set_parent_after() when enabling one of the parent > clock fails in __clk_set_parent_before(). Hm, indeed.. Interestingly the return value of clk_core_prepare_enable() (defined static inside clk.c) is never evaluated, across all of the calls Konrad