Re: [PATCH v8 4/9] phy: fsl: Add Lynx 10G SerDes driver

[Sean Anderson <sean.anderson@seco.com>]

On 11/1/22 16:10, Stephen Boyd wrote:
> Quoting Sean Anderson (2022-10-28 09:33:59)
>> On 10/28/22 12:13, Sean Anderson wrote:
>> > On 10/27/22 19:03, Stephen Boyd wrote:
>> >>> +       ref = devm_clk_get(dev, ref_name);
>> >>> +       if (IS_ERR(clk->ref)) {
>> >>> +               ret = PTR_ERR(clk->ref);
>> >>> +               dev_err_probe(dev, ret, "could not get %s\n", ref_name);
>> >>> +               goto out;
>> >>> +       }
>> >>> +
>> >>> +       clk->ref = __clk_get_hw(ref);
>> >>
>> >> Please don't use __clk_get_hw() for this. Instead use struct
>> >> clk_parent_data and set a DT index in the index member to map to this
>> >> clk.
>> > 
>> > OK
>> 
>> Oh, I remember why I did this. I need the reference clock for clk_hw_round_rate,
>> which is AFAICT the only correct way to implement round_rate.
>> 
> 
> Is the reference clk the parent of the clk implementing
> clk_ops::round_rate()?

Yes. We may be able to produce a given output with multiple reference
rates. However, the clock API provides no mechanism to say "Don't ask
for the parent clock to be rate X, you just tried it and the parent
clock can't support it." So instead, we loop over the possible reference
rates and pick the first one which the parent says it can round to.

--Sean