From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DF0321DE4FF; Wed, 30 Oct 2024 07:31:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730273469; cv=none; b=MNAR8tokf2cFxKUZIRV+3XRj83+DAfuVrw0oeKna7u6KhAB43xfdRel91uHGV+7dg134vN+u33Wrk5Uj6UrfJtE7WuANKdWf/y/3PMb22/2xQa1/L4tg+glb2DNYW1q3TUxs/6cZYlCskWTeZOaoTgTIfVIgxUJ7BWoSx5aat8o= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730273469; c=relaxed/simple; bh=fAjMDAmGdqV3C4LaqmDkeJghPf7va/LgPEvMON1fpg0=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=TU0OUQ32IE46ESID3dwFGM5zgGyBfH4+4LCjKu6x0NSfMo0b3DXT89OWnKHwjIO7dEGIGqEo829EbWbhKMo1YA+vDA0wdS3ekx4HgqMZrclOWQGv5Hc2HE0DGjxQZ0NvI9nItIxvmKDlf77VDw1U4HfBdZi3E7+4ARZx44wwGNM= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=KVxGxuho; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="KVxGxuho" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 68E31C4CEE4; Wed, 30 Oct 2024 07:31:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1730273468; bh=fAjMDAmGdqV3C4LaqmDkeJghPf7va/LgPEvMON1fpg0=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=KVxGxuhowT20UZ5a9jxWzgU48leNiWqNjMYCUuJ1mUsIgCYbybvPzAEw+dde74270 yBu7MzSfSQqLskiQgrL6v0K+N+jOZTqwjURcThKhIO2CzSdI33P/Go+/vLx4XXHkXQ dregMU2VXg/bneQWpFh+/4PN0EFaobDNTzp/Eun5R4ntfR0KtvE1uLU59vad0kCx4y JBmNmxlHCEOU84GIkj4bvhAQDjSw2wAJ1/M0qew3QTRQHRusYxYX70Squ2UNQiP01j ye6AfqWmZlxkE0Hi/i3F7Js2hWUI3tR3bkZ6rwRpUsA9rBbnHu/THAD/gPxQ1GstlZ S4dKti0740SVw== Message-ID: <46c19729-b31e-42e3-a6dd-6b43b27348d8@kernel.org> Date: Wed, 30 Oct 2024 08:30:59 +0100 Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 1/6] dt-bindings: clock: qcom: Add GPU clocks for QCS8300 To: Imran Shaik Cc: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Ajit Pandey , Taniya Das , Jagadeesh Kona , Satya Priya Kakitapalli , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20241024-qcs8300-mm-patches-v2-0-76c905060d0a@quicinc.com> <20241024-qcs8300-mm-patches-v2-1-76c905060d0a@quicinc.com> <0487791a-f31b-4427-b13b-b7ab6a80378b@quicinc.com> <9bd4c63b-7c68-4e40-9995-9d569eed15b5@kernel.org> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 8bit On 30/10/2024 07:59, Imran Shaik wrote: > > > On 10/29/2024 3:06 PM, Krzysztof Kozlowski wrote: >> On 29/10/2024 10:23, Imran Shaik wrote: >>> >>> >>> On 10/28/2024 12:35 PM, Krzysztof Kozlowski wrote: >>>> On 28/10/2024 06:15, Imran Shaik wrote: >>>>> >>>>> >>>>> On 10/26/2024 5:50 PM, Krzysztof Kozlowski wrote: >>>>>> On Thu, Oct 24, 2024 at 07:01:14PM +0530, Imran Shaik wrote: >>>>>>> The QCS8300 GPU clock controller is mostly identical to SA8775P, but >>>>>>> QCS8300 has few additional clocks and minor differences. Hence, reuse >>>>>>> SA8775P gpucc bindings and add additional clocks required for QCS8300. >>>>>> >>>>>> IIUC, these clocks are not valid for SA8775p. How do we deal with such >>>>>> cases for other Qualcomm SoCs? >>>>>> >>>>> >>>>> These newly added clocks are not applicable to SA8755P. In the >>>>> gpucc-sa8775p driver, these clocks are marked to NULL for the SA8755P, >>>>> ensuring they are not registered to the CCF. >>>> >>>> I meant bindings. And existing practice. >>>> >>> >>> In the bindings, the same approach is followed in other Qualcomm SoCs as >>> well, where additional clocks are added to the existing identical SoC’s >>> bindings. >>> >>> https://lore.kernel.org/r/20240818204348.197788-2-danila@jiaxyga.com >> >> Exactly, defines are very different, so no, it is not the same approach. >> > > I believe the QCS8300 approach is same as that of SM8475. In the SM8475 > SoC, GPLL2 and GPLL3 are the additional clock bindings compared to the > SM8450. Similarly, in the QCS8300, the GPU_CC_*_ACCU_SHIFT_CLK clock > bindings are additional to the SA8775P. > > We are also following this approach across all SoCs in the downstream > msm-kernel as well. > > Please let me know if I am missing anything here. Not sure, please take the same approach as SM8475, not a different one. Best regards, Krzysztof