[PATCH 0/2] dt-bindings: watchdog: Add support for FSD SoC watchdog

[PATCH 0/2] dt-bindings: watchdog: Add support for FSD SoC watchdog

[Varada Pavani]

The FSD SoC features 3 CPU clusters, each with its own Watchdog Timer (WDT) instance.
The DT-binding and device data is updated to reflect the cluster index and clock configurations as per the HW user manual.

Varada Pavani (2):
  dt-bindings: watchdog: Modify tesla fsd bindings
  arm64: dts: fsd: Fix Clock handle for WDT

 .../bindings/watchdog/samsung-wdt.yaml        |  9 ++++---
 arch/arm64/boot/dts/tesla/fsd.dtsi            | 24 ++++++++++++-------
 2 files changed, 19 insertions(+), 14 deletions(-)

-- 
2.49.0

[PATCH 1/2] dt-bindings: watchdog: Modify tesla fsd bindings

[Varada Pavani]

FSD SoC WDT is using Samsung legacy WDT driver with
"samsung,exynos7-wdt" compatibility. Now change the compatibility due to
few driver changes (PMU bit changes for each WDT instance and Clocks)
for WDT found in FSD SoC.

Signed-off-by: Varada Pavani <v.pavani@samsung.com>
---
 .../devicetree/bindings/watchdog/samsung-wdt.yaml        | 9 ++++-----
 1 file changed, 4 insertions(+), 5 deletions(-)

diff --git a/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml b/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml
index d175ae968336..db2009654fe4 100644
--- a/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml
+++ b/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml
@@ -27,10 +27,7 @@ properties:
           - samsung,exynos850-wdt                 # for Exynos850
           - samsung,exynosautov9-wdt              # for Exynosautov9
           - samsung,exynosautov920-wdt            # for Exynosautov920
-      - items:
-          - enum:
-              - tesla,fsd-wdt
-          - const: samsung,exynos7-wdt
+          - tesla,fsd-wdt
 
   reg:
     maxItems: 1
@@ -79,6 +76,7 @@ allOf:
               - samsung,exynos850-wdt
               - samsung,exynosautov9-wdt
               - samsung,exynosautov920-wdt
+              - tesla,fsd-wdt
     then:
       required:
         - samsung,syscon-phandle
@@ -91,6 +89,7 @@ allOf:
               - samsung,exynos850-wdt
               - samsung,exynosautov9-wdt
               - samsung,exynosautov920-wdt
+              - tesla,fsd-wdt
     then:
       properties:
         clocks:
@@ -102,7 +101,7 @@ allOf:
             - const: watchdog
             - const: watchdog_src
         samsung,cluster-index:
-          enum: [0, 1]
+          enum: [0, 1, 2]
       required:
         - samsung,cluster-index
     else:
-- 
2.49.0

[PATCH 2/2] arm64: dts: fsd: Fix Clock handle for WDT

[Varada Pavani]

FSD SoC WDT has few changes when compared to exynos7 interms of Clocks,
PMU register bits for each cluster. So use "tesla,fsd-wdt"
compatibility for using correct driver data.
FSD supports 2 Clocks for WDT (PCLK and CLK).
- use fin_pll source Clock for all timer related calculations.
- use bus Clock (IMEM_WDT0_IPCLKPORT_PCLK) to gate/ungate the register
interface. Update both as per WDT UM.

Signed-off-by: Varada Pavani <v.pavani@samsung.com>
---
 arch/arm64/boot/dts/tesla/fsd.dtsi | 24 +++++++++++++++---------
 1 file changed, 15 insertions(+), 9 deletions(-)

diff --git a/arch/arm64/boot/dts/tesla/fsd.dtsi b/arch/arm64/boot/dts/tesla/fsd.dtsi
index 690b4ed9c29b..ff031a630f10 100644
--- a/arch/arm64/boot/dts/tesla/fsd.dtsi
+++ b/arch/arm64/boot/dts/tesla/fsd.dtsi
@@ -624,30 +624,36 @@ pmu_system_controller: system-controller@11400000 {
 		};
 
 		watchdog_0: watchdog@100a0000 {
-			compatible = "tesla,fsd-wdt", "samsung,exynos7-wdt";
+			compatible = "tesla,fsd-wdt";
 			reg = <0x0 0x100a0000 0x0 0x100>;
 			interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>;
 			samsung,syscon-phandle = <&pmu_system_controller>;
-			clocks = <&fin_pll>;
-			clock-names = "watchdog";
+			clocks = <&clock_imem IMEM_WDT0_IPCLKPORT_PCLK>,
+				<&fin_pll>;
+			clock-names = "watchdog", "watchdog_src";
+			samsung,cluster-index = <0>;
 		};
 
 		watchdog_1: watchdog@100b0000 {
-			compatible = "tesla,fsd-wdt", "samsung,exynos7-wdt";
+			compatible = "tesla,fsd-wdt";
 			reg = <0x0 0x100b0000 0x0 0x100>;
 			interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>;
 			samsung,syscon-phandle = <&pmu_system_controller>;
-			clocks = <&fin_pll>;
-			clock-names = "watchdog";
+			clocks = <&clock_imem IMEM_WDT1_IPCLKPORT_PCLK>,
+				<&fin_pll>;
+			clock-names = "watchdog", "watchdog_src";
+			samsung,cluster-index = <1>;
 		};
 
 		watchdog_2: watchdog@100c0000 {
-			compatible = "tesla,fsd-wdt", "samsung,exynos7-wdt";
+			compatible = "tesla,fsd-wdt";
 			reg = <0x0 0x100c0000 0x0 0x100>;
 			interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>;
 			samsung,syscon-phandle = <&pmu_system_controller>;
-			clocks = <&fin_pll>;
-			clock-names = "watchdog";
+			clocks = <&clock_imem IMEM_WDT2_IPCLKPORT_PCLK>,
+				<&fin_pll>;
+			clock-names = "watchdog", "watchdog_src";
+			samsung,cluster-index = <2>;
 		};
 
 		pwm_0: pwm@14100000 {
-- 
2.49.0

Re: [PATCH 1/2] dt-bindings: watchdog: Modify tesla fsd bindings

[Krzysztof Kozlowski]

On 29/08/2025 15:56, Varada Pavani wrote:
> FSD SoC WDT is using Samsung legacy WDT driver with
> "samsung,exynos7-wdt" compatibility. Now change the compatibility due to
> few driver changes (PMU bit changes for each WDT instance and Clocks)
> for WDT found in FSD SoC.

Eh, no, this does not work like that. FSD SoC was released like 8 years
ago, so how hardware can change now?

You cannot claim ABI needs changes because your driver does something,
it's just misinterpretation of bindings.

Please read writing bindings. DTS was added recently, in 2022, but 3
years is long enough to test it, so I must assume this was tested.

Otherwise you need to REALLY carefully explain that.

Best regards,
Krzysztof

Re: [PATCH 2/2] arm64: dts: fsd: Fix Clock handle for WDT

[Krzysztof Kozlowski]

On 29/08/2025 15:56, Varada Pavani wrote:
> FSD SoC WDT has few changes when compared to exynos7 interms of Clocks,
> PMU register bits for each cluster. So use "tesla,fsd-wdt"

So what was added in 2022?

> compatibility for using correct driver data.
> FSD supports 2 Clocks for WDT (PCLK and CLK).
> - use fin_pll source Clock for all timer related calculations.
> - use bus Clock (IMEM_WDT0_IPCLKPORT_PCLK) to gate/ungate the register
> interface. Update both as per WDT UM.

No, you break all the users. Probably users don't care, but I do care
because I use that arguments for reviewing other patches, so I apply a
bit stricter rules for existing Samsung trees.

Otherwise provide rationale about impact and what was happening in 2022
with this code...


Best regards,
Krzysztof

Re: [PATCH 1/2] dt-bindings: watchdog: Modify tesla fsd bindings

[Krzysztof Kozlowski]

On 29/08/2025 15:56, Varada Pavani wrote:
> FSD SoC WDT is using Samsung legacy WDT driver with
> "samsung,exynos7-wdt" compatibility. Now change the compatibility due to
> few driver changes (PMU bit changes for each WDT instance and Clocks)
> for WDT found in FSD SoC.
> 
> Signed-off-by: Varada Pavani <v.pavani@samsung.com>
More comments:
1. Subject: completely vague, everything is modify, every binding is
"bindings". Write useful subjects.

2. ... and never tested :/
The amount of very poor contributions from Samsung recently skyrocketed.
Like 66% of contributions were not passing basic guidelines, basic
process, so should not have been sent.


<form letter>
Please use scripts/get_maintainers.pl to get a list of necessary people
and lists to CC. It might happen, that command when run on an older
kernel, gives you outdated entries. Therefore please be sure you base
your patches on recent Linux kernel.

Tools like b4 or scripts/get_maintainer.pl provide you proper list of
people, so fix your workflow. Tools might also fail if you work on some
ancient tree (don't, instead use mainline) or work on fork of kernel
(don't, instead use mainline). Just use b4 and everything should be
fine, although remember about `b4 prep --auto-to-cc` if you added new
patches to the patchset.

You missed at least devicetree list (maybe more), so this won't be
tested by automated tooling. Performing review on untested code might be
a waste of time.

Please kindly resend and include all necessary To/Cc entries.
</form letter>



Best regards,
Krzysztof