* [PATCH v4 0/4] clk: samsung: exynos990: CMU_TOP fixes (mux regs, widths, factors)
@ 2025-08-25 5:51 Denzeel Oliva
2025-08-25 5:51 ` [PATCH v4 1/4] clk: samsung: exynos990: Fix CMU TOP mux/div widths and add fixed-factors Denzeel Oliva
` (3 more replies)
0 siblings, 4 replies; 9+ messages in thread
From: Denzeel Oliva @ 2025-08-25 5:51 UTC (permalink / raw)
To: Krzysztof Kozlowski, Sylwester Nawrocki, Chanwoo Choi,
Alim Akhtar, Michael Turquette, Stephen Boyd, Rob Herring,
Conor Dooley
Cc: linux-samsung-soc, linux-clk, linux-arm-kernel, linux-kernel,
devicetree, Denzeel Oliva
Hi,
Two small fixes for Exynos990 CMU_TOP:
Correct PLL mux register selection (use PLL_CON0), add DPU_BUS and
CMUREF mux/div, and update clock IDs.
Fix mux/div bit widths and replace a few bogus divs with fixed-factor
clocks (HSI1/2 PCIe, USBDP debug); also fix OTP rate.
Changes in v2:
- In the first commit the divratio of
PLL_SHARED0_DIV3 should not be changed.
Changes in v3:
- There is no ABI massive break, the new ID clocks are
in the last define CMU_TOP block.
Changes in v4:
- Fix compilation for define CLK_DOUT_CMU_CMUREF to
CLK_DOUT_CMU_CLK_CMUREF
Please review.
Denzeel Oliva
Signed-off-by: Denzeel Oliva <wachiturroxd150@gmail.com>
---
Denzeel Oliva (4):
clk: samsung: exynos990: Fix CMU TOP mux/div widths and add fixed-factors
dt-bindings: clock: exynos990: Extend clocks IDs
clk: samsung: exynos990: update CLK_NR_TOP for new IDs clocks
clk: samsung: exynos990: Fix PLL mux regs, add DPU/CMUREF
drivers/clk/samsung/clk-exynos990.c | 136 ++++++++++++++++----------
include/dt-bindings/clock/samsung,exynos990.h | 4 +
2 files changed, 89 insertions(+), 51 deletions(-)
---
base-commit: 0f4c93f7eb861acab537dbe94441817a270537bf
change-id: 20250825-cmu-top-5c709c1d07c2
Best regards,
--
Denzeel Oliva <wachiturroxd150@gmail.com>
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v4 1/4] clk: samsung: exynos990: Fix CMU TOP mux/div widths and add fixed-factors
2025-08-25 5:51 [PATCH v4 0/4] clk: samsung: exynos990: CMU_TOP fixes (mux regs, widths, factors) Denzeel Oliva
@ 2025-08-25 5:51 ` Denzeel Oliva
2025-08-30 9:17 ` Krzysztof Kozlowski
2025-08-25 5:51 ` [PATCH v4 2/4] dt-bindings: clock: exynos990: Extend clocks IDs Denzeel Oliva
` (2 subsequent siblings)
3 siblings, 1 reply; 9+ messages in thread
From: Denzeel Oliva @ 2025-08-25 5:51 UTC (permalink / raw)
To: Krzysztof Kozlowski, Sylwester Nawrocki, Chanwoo Choi,
Alim Akhtar, Michael Turquette, Stephen Boyd, Rob Herring,
Conor Dooley
Cc: linux-samsung-soc, linux-clk, linux-arm-kernel, linux-kernel,
devicetree, Denzeel Oliva
Correct mux/div bit widths in CMU TOP (DPU, DSP_BUS, G2D_MSCL,
HSI0/1/2). Replace wrong divs with fixed-factor clocks for
HSI1/2 PCIe and USBDP debug. Also add OTP rate in ffactor.
These align with Exynos990 downstream cmucal and ensure correct
parent/rate selection.
Signed-off-by: Denzeel Oliva <wachiturroxd150@gmail.com>
---
drivers/clk/samsung/clk-exynos990.c | 37 +++++++++++++++++++++----------------
1 file changed, 21 insertions(+), 16 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos990.c b/drivers/clk/samsung/clk-exynos990.c
index 8d3f193d2..105ba0363 100644
--- a/drivers/clk/samsung/clk-exynos990.c
+++ b/drivers/clk/samsung/clk-exynos990.c
@@ -759,11 +759,11 @@ static const struct samsung_mux_clock top_mux_clks[] __initconst = {
MUX(CLK_MOUT_CMU_DPU_ALT, "mout_cmu_dpu_alt",
mout_cmu_dpu_alt_p, CLK_CON_MUX_MUX_CLKCMU_DPU_ALT, 0, 2),
MUX(CLK_MOUT_CMU_DSP_BUS, "mout_cmu_dsp_bus",
- mout_cmu_dsp_bus_p, CLK_CON_MUX_MUX_CLKCMU_DSP_BUS, 0, 2),
+ mout_cmu_dsp_bus_p, CLK_CON_MUX_MUX_CLKCMU_DSP_BUS, 0, 3),
MUX(CLK_MOUT_CMU_G2D_G2D, "mout_cmu_g2d_g2d",
mout_cmu_g2d_g2d_p, CLK_CON_MUX_MUX_CLKCMU_G2D_G2D, 0, 2),
MUX(CLK_MOUT_CMU_G2D_MSCL, "mout_cmu_g2d_mscl",
- mout_cmu_g2d_mscl_p, CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL, 0, 1),
+ mout_cmu_g2d_mscl_p, CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL, 0, 2),
MUX(CLK_MOUT_CMU_HPM, "mout_cmu_hpm",
mout_cmu_hpm_p, CLK_CON_MUX_MUX_CLKCMU_HPM, 0, 2),
MUX(CLK_MOUT_CMU_HSI0_BUS, "mout_cmu_hsi0_bus",
@@ -775,7 +775,7 @@ static const struct samsung_mux_clock top_mux_clks[] __initconst = {
0, 2),
MUX(CLK_MOUT_CMU_HSI0_USBDP_DEBUG, "mout_cmu_hsi0_usbdp_debug",
mout_cmu_hsi0_usbdp_debug_p,
- CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDP_DEBUG, 0, 2),
+ CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDP_DEBUG, 0, 1),
MUX(CLK_MOUT_CMU_HSI1_BUS, "mout_cmu_hsi1_bus",
mout_cmu_hsi1_bus_p, CLK_CON_MUX_MUX_CLKCMU_HSI1_BUS, 0, 3),
MUX(CLK_MOUT_CMU_HSI1_MMC_CARD, "mout_cmu_hsi1_mmc_card",
@@ -788,7 +788,7 @@ static const struct samsung_mux_clock top_mux_clks[] __initconst = {
0, 2),
MUX(CLK_MOUT_CMU_HSI1_UFS_EMBD, "mout_cmu_hsi1_ufs_embd",
mout_cmu_hsi1_ufs_embd_p, CLK_CON_MUX_MUX_CLKCMU_HSI1_UFS_EMBD,
- 0, 1),
+ 0, 2),
MUX(CLK_MOUT_CMU_HSI2_BUS, "mout_cmu_hsi2_bus",
mout_cmu_hsi2_bus_p, CLK_CON_MUX_MUX_CLKCMU_HSI2_BUS, 0, 1),
MUX(CLK_MOUT_CMU_HSI2_PCIE, "mout_cmu_hsi2_pcie",
@@ -862,7 +862,7 @@ static const struct samsung_div_clock top_div_clks[] __initconst = {
CLK_CON_DIV_PLL_SHARED4_DIV4, 0, 1),
DIV(CLK_DOUT_CMU_APM_BUS, "dout_cmu_apm_bus", "gout_cmu_apm_bus",
- CLK_CON_DIV_CLKCMU_APM_BUS, 0, 3),
+ CLK_CON_DIV_CLKCMU_APM_BUS, 0, 2),
DIV(CLK_DOUT_CMU_AUD_CPU, "dout_cmu_aud_cpu", "gout_cmu_aud_cpu",
CLK_CON_DIV_CLKCMU_AUD_CPU, 0, 3),
DIV(CLK_DOUT_CMU_BUS0_BUS, "dout_cmu_bus0_bus", "gout_cmu_bus0_bus",
@@ -887,9 +887,9 @@ static const struct samsung_div_clock top_div_clks[] __initconst = {
CLK_CON_DIV_CLKCMU_CMU_BOOST, 0, 2),
DIV(CLK_DOUT_CMU_CORE_BUS, "dout_cmu_core_bus", "gout_cmu_core_bus",
CLK_CON_DIV_CLKCMU_CORE_BUS, 0, 4),
- DIV(CLK_DOUT_CMU_CPUCL0_DBG_BUS, "dout_cmu_cpucl0_debug",
+ DIV(CLK_DOUT_CMU_CPUCL0_DBG_BUS, "dout_cmu_cpucl0_dbg_bus",
"gout_cmu_cpucl0_dbg_bus", CLK_CON_DIV_CLKCMU_CPUCL0_DBG_BUS,
- 0, 3),
+ 0, 4),
DIV(CLK_DOUT_CMU_CPUCL0_SWITCH, "dout_cmu_cpucl0_switch",
"gout_cmu_cpucl0_switch", CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH, 0, 3),
DIV(CLK_DOUT_CMU_CPUCL1_SWITCH, "dout_cmu_cpucl1_switch",
@@ -924,16 +924,11 @@ static const struct samsung_div_clock top_div_clks[] __initconst = {
CLK_CON_DIV_CLKCMU_HSI0_DPGTC, 0, 3),
DIV(CLK_DOUT_CMU_HSI0_USB31DRD, "dout_cmu_hsi0_usb31drd",
"gout_cmu_hsi0_usb31drd", CLK_CON_DIV_CLKCMU_HSI0_USB31DRD, 0, 4),
- DIV(CLK_DOUT_CMU_HSI0_USBDP_DEBUG, "dout_cmu_hsi0_usbdp_debug",
- "gout_cmu_hsi0_usbdp_debug", CLK_CON_DIV_CLKCMU_HSI0_USBDP_DEBUG,
- 0, 4),
DIV(CLK_DOUT_CMU_HSI1_BUS, "dout_cmu_hsi1_bus", "gout_cmu_hsi1_bus",
CLK_CON_DIV_CLKCMU_HSI1_BUS, 0, 3),
DIV(CLK_DOUT_CMU_HSI1_MMC_CARD, "dout_cmu_hsi1_mmc_card",
"gout_cmu_hsi1_mmc_card", CLK_CON_DIV_CLKCMU_HSI1_MMC_CARD,
0, 9),
- DIV(CLK_DOUT_CMU_HSI1_PCIE, "dout_cmu_hsi1_pcie", "gout_cmu_hsi1_pcie",
- CLK_CON_DIV_CLKCMU_HSI1_PCIE, 0, 7),
DIV(CLK_DOUT_CMU_HSI1_UFS_CARD, "dout_cmu_hsi1_ufs_card",
"gout_cmu_hsi1_ufs_card", CLK_CON_DIV_CLKCMU_HSI1_UFS_CARD,
0, 3),
@@ -942,8 +937,6 @@ static const struct samsung_div_clock top_div_clks[] __initconst = {
0, 3),
DIV(CLK_DOUT_CMU_HSI2_BUS, "dout_cmu_hsi2_bus", "gout_cmu_hsi2_bus",
CLK_CON_DIV_CLKCMU_HSI2_BUS, 0, 4),
- DIV(CLK_DOUT_CMU_HSI2_PCIE, "dout_cmu_hsi2_pcie", "gout_cmu_hsi2_pcie",
- CLK_CON_DIV_CLKCMU_HSI2_PCIE, 0, 7),
DIV(CLK_DOUT_CMU_IPP_BUS, "dout_cmu_ipp_bus", "gout_cmu_ipp_bus",
CLK_CON_DIV_CLKCMU_IPP_BUS, 0, 4),
DIV(CLK_DOUT_CMU_ITP_BUS, "dout_cmu_itp_bus", "gout_cmu_itp_bus",
@@ -979,8 +972,18 @@ static const struct samsung_div_clock top_div_clks[] __initconst = {
CLK_CON_DIV_CLKCMU_TNR_BUS, 0, 4),
DIV(CLK_DOUT_CMU_VRA_BUS, "dout_cmu_vra_bus", "gout_cmu_vra_bus",
CLK_CON_DIV_CLKCMU_VRA_BUS, 0, 4),
- DIV(CLK_DOUT_CMU_DPU, "dout_cmu_clkcmu_dpu", "gout_cmu_dpu",
- CLK_CON_DIV_DIV_CLKCMU_DPU, 0, 4),
+ DIV(CLK_DOUT_CMU_DPU, "dout_cmu_dpu", "gout_cmu_dpu",
+ CLK_CON_DIV_DIV_CLKCMU_DPU, 0, 3),
+};
+
+static const struct samsung_fixed_factor_clock cmu_top_ffactor[] __initconst = {
+ FFACTOR(CLK_DOUT_CMU_HSI1_PCIE, "dout_cmu_hsi1_pcie",
+ "gout_cmu_hsi1_pcie", 1, 8, 0),
+ FFACTOR(CLK_DOUT_CMU_OTP, "dout_cmu_otp", "oscclk", 1, 8, 0),
+ FFACTOR(CLK_DOUT_CMU_HSI0_USBDP_DEBUG, "dout_cmu_hsi0_usbdp_debug",
+ "gout_cmu_hsi0_usbdp_debug", 1, 8, 0),
+ FFACTOR(CLK_DOUT_CMU_HSI2_PCIE, "dout_cmu_hsi2_pcie",
+ "gout_cmu_hsi2_pcie", 1, 8, 0),
};
static const struct samsung_gate_clock top_gate_clks[] __initconst = {
@@ -1126,6 +1129,8 @@ static const struct samsung_cmu_info top_cmu_info __initconst = {
.nr_mux_clks = ARRAY_SIZE(top_mux_clks),
.div_clks = top_div_clks,
.nr_div_clks = ARRAY_SIZE(top_div_clks),
+ .fixed_factor_clks = cmu_top_ffactor,
+ .nr_fixed_factor_clks = ARRAY_SIZE(cmu_top_ffactor),
.gate_clks = top_gate_clks,
.nr_gate_clks = ARRAY_SIZE(top_gate_clks),
.nr_clk_ids = CLKS_NR_TOP,
--
2.50.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v4 2/4] dt-bindings: clock: exynos990: Extend clocks IDs
2025-08-25 5:51 [PATCH v4 0/4] clk: samsung: exynos990: CMU_TOP fixes (mux regs, widths, factors) Denzeel Oliva
2025-08-25 5:51 ` [PATCH v4 1/4] clk: samsung: exynos990: Fix CMU TOP mux/div widths and add fixed-factors Denzeel Oliva
@ 2025-08-25 5:51 ` Denzeel Oliva
2025-08-29 15:26 ` Rob Herring (Arm)
2025-08-25 5:51 ` [PATCH v4 3/4] clk: samsung: exynos990: update CLK_NR_TOP for new IDs clocks Denzeel Oliva
2025-08-25 5:51 ` [PATCH v4 4/4] clk: samsung: exynos990: Fix PLL mux regs, add DPU/CMUREF Denzeel Oliva
3 siblings, 1 reply; 9+ messages in thread
From: Denzeel Oliva @ 2025-08-25 5:51 UTC (permalink / raw)
To: Krzysztof Kozlowski, Sylwester Nawrocki, Chanwoo Choi,
Alim Akhtar, Michael Turquette, Stephen Boyd, Rob Herring,
Conor Dooley
Cc: linux-samsung-soc, linux-clk, linux-arm-kernel, linux-kernel,
devicetree, Denzeel Oliva
Add missing clock definitions for DPU and CMUREF.
Signed-off-by: Denzeel Oliva <wachiturroxd150@gmail.com>
---
include/dt-bindings/clock/samsung,exynos990.h | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/include/dt-bindings/clock/samsung,exynos990.h b/include/dt-bindings/clock/samsung,exynos990.h
index 6b9df09d2..c5c79e078 100644
--- a/include/dt-bindings/clock/samsung,exynos990.h
+++ b/include/dt-bindings/clock/samsung,exynos990.h
@@ -208,6 +208,10 @@
#define CLK_GOUT_CMU_SSP_BUS 197
#define CLK_GOUT_CMU_TNR_BUS 198
#define CLK_GOUT_CMU_VRA_BUS 199
+#define CLK_MOUT_CMU_CMUREF 200
+#define CLK_MOUT_CMU_DPU_BUS 201
+#define CLK_MOUT_CMU_CLK_CMUREF 202
+#define CLK_DOUT_CMU_CLK_CMUREF 203
/* CMU_HSI0 */
#define CLK_MOUT_HSI0_BUS_USER 1
--
2.50.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v4 3/4] clk: samsung: exynos990: update CLK_NR_TOP for new IDs clocks
2025-08-25 5:51 [PATCH v4 0/4] clk: samsung: exynos990: CMU_TOP fixes (mux regs, widths, factors) Denzeel Oliva
2025-08-25 5:51 ` [PATCH v4 1/4] clk: samsung: exynos990: Fix CMU TOP mux/div widths and add fixed-factors Denzeel Oliva
2025-08-25 5:51 ` [PATCH v4 2/4] dt-bindings: clock: exynos990: Extend clocks IDs Denzeel Oliva
@ 2025-08-25 5:51 ` Denzeel Oliva
2025-08-30 9:18 ` Krzysztof Kozlowski
2025-08-25 5:51 ` [PATCH v4 4/4] clk: samsung: exynos990: Fix PLL mux regs, add DPU/CMUREF Denzeel Oliva
3 siblings, 1 reply; 9+ messages in thread
From: Denzeel Oliva @ 2025-08-25 5:51 UTC (permalink / raw)
To: Krzysztof Kozlowski, Sylwester Nawrocki, Chanwoo Choi,
Alim Akhtar, Michael Turquette, Stephen Boyd, Rob Herring,
Conor Dooley
Cc: linux-samsung-soc, linux-clk, linux-arm-kernel, linux-kernel,
devicetree, Denzeel Oliva
The new clock IDs have been added and put last,
it is necessary to change.
Signed-off-by: Denzeel Oliva <wachiturroxd150@gmail.com>
---
drivers/clk/samsung/clk-exynos990.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/samsung/clk-exynos990.c b/drivers/clk/samsung/clk-exynos990.c
index 105ba0363..9fcdad7cc 100644
--- a/drivers/clk/samsung/clk-exynos990.c
+++ b/drivers/clk/samsung/clk-exynos990.c
@@ -17,7 +17,7 @@
#include "clk-pll.h"
/* NOTE: Must be equal to the last clock ID increased by one */
-#define CLKS_NR_TOP (CLK_GOUT_CMU_VRA_BUS + 1)
+#define CLKS_NR_TOP (CLK_DOUT_CMU_CLK_CMUREF + 1)
#define CLKS_NR_HSI0 (CLK_GOUT_HSI0_XIU_D_HSI0_ACLK + 1)
#define CLKS_NR_PERIS (CLK_GOUT_PERIS_OTP_CON_TOP_OSCCLK + 1)
--
2.50.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v4 4/4] clk: samsung: exynos990: Fix PLL mux regs, add DPU/CMUREF
2025-08-25 5:51 [PATCH v4 0/4] clk: samsung: exynos990: CMU_TOP fixes (mux regs, widths, factors) Denzeel Oliva
` (2 preceding siblings ...)
2025-08-25 5:51 ` [PATCH v4 3/4] clk: samsung: exynos990: update CLK_NR_TOP for new IDs clocks Denzeel Oliva
@ 2025-08-25 5:51 ` Denzeel Oliva
2025-08-30 9:16 ` Krzysztof Kozlowski
3 siblings, 1 reply; 9+ messages in thread
From: Denzeel Oliva @ 2025-08-25 5:51 UTC (permalink / raw)
To: Krzysztof Kozlowski, Sylwester Nawrocki, Chanwoo Choi,
Alim Akhtar, Michael Turquette, Stephen Boyd, Rob Herring,
Conor Dooley
Cc: linux-samsung-soc, linux-clk, linux-arm-kernel, linux-kernel,
devicetree, Denzeel Oliva
Switch PLL muxes to PLL_CON0 to correct parent selection and
clock rates. Add DPU_BUS and CMUREF mux/div and their register
hooks and parents.
Signed-off-by: Denzeel Oliva <wachiturroxd150@gmail.com>
---
drivers/clk/samsung/clk-exynos990.c | 97 ++++++++++++++++++++++++-------------
1 file changed, 63 insertions(+), 34 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos990.c b/drivers/clk/samsung/clk-exynos990.c
index 9fcdad7cc..d1135708c 100644
--- a/drivers/clk/samsung/clk-exynos990.c
+++ b/drivers/clk/samsung/clk-exynos990.c
@@ -45,6 +45,7 @@
#define PLL_CON3_PLL_SHARED3 0x024c
#define PLL_CON0_PLL_SHARED4 0x0280
#define PLL_CON3_PLL_SHARED4 0x028c
+#define CLK_CON_MUX_CLKCMU_DPU_BUS 0x1000
#define CLK_CON_MUX_MUX_CLKCMU_APM_BUS 0x1004
#define CLK_CON_MUX_MUX_CLKCMU_AUD_CPU 0x1008
#define CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS 0x100c
@@ -103,6 +104,8 @@
#define CLK_CON_MUX_MUX_CLKCMU_SSP_BUS 0x10e0
#define CLK_CON_MUX_MUX_CLKCMU_TNR_BUS 0x10e4
#define CLK_CON_MUX_MUX_CLKCMU_VRA_BUS 0x10e8
+#define CLK_CON_MUX_MUX_CLK_CMU_CMUREF 0x10f0
+#define CLK_CON_MUX_MUX_CMU_CMUREF 0x10f4
#define CLK_CON_DIV_CLKCMU_APM_BUS 0x1800
#define CLK_CON_DIV_CLKCMU_AUD_CPU 0x1804
#define CLK_CON_DIV_CLKCMU_BUS0_BUS 0x1808
@@ -162,6 +165,7 @@
#define CLK_CON_DIV_CLKCMU_VRA_BUS 0x18e0
#define CLK_CON_DIV_DIV_CLKCMU_DPU 0x18e8
#define CLK_CON_DIV_DIV_CLKCMU_DPU_ALT 0x18ec
+#define CLK_CON_DIV_DIV_CLK_CMU_CMUREF 0x18f0
#define CLK_CON_DIV_PLL_SHARED0_DIV2 0x18f4
#define CLK_CON_DIV_PLL_SHARED0_DIV3 0x18f8
#define CLK_CON_DIV_PLL_SHARED0_DIV4 0x18fc
@@ -239,13 +243,21 @@ static const unsigned long top_clk_regs[] __initconst = {
PLL_LOCKTIME_PLL_SHARED2,
PLL_LOCKTIME_PLL_SHARED3,
PLL_LOCKTIME_PLL_SHARED4,
+ PLL_CON0_PLL_G3D,
PLL_CON3_PLL_G3D,
+ PLL_CON0_PLL_MMC,
PLL_CON3_PLL_MMC,
+ PLL_CON0_PLL_SHARED0,
PLL_CON3_PLL_SHARED0,
+ PLL_CON0_PLL_SHARED1,
PLL_CON3_PLL_SHARED1,
+ PLL_CON0_PLL_SHARED2,
PLL_CON3_PLL_SHARED2,
+ PLL_CON0_PLL_SHARED3,
PLL_CON3_PLL_SHARED3,
+ PLL_CON0_PLL_SHARED4,
PLL_CON3_PLL_SHARED4,
+ CLK_CON_MUX_CLKCMU_DPU_BUS,
CLK_CON_MUX_MUX_CLKCMU_APM_BUS,
CLK_CON_MUX_MUX_CLKCMU_AUD_CPU,
CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS,
@@ -304,6 +316,8 @@ static const unsigned long top_clk_regs[] __initconst = {
CLK_CON_MUX_MUX_CLKCMU_SSP_BUS,
CLK_CON_MUX_MUX_CLKCMU_TNR_BUS,
CLK_CON_MUX_MUX_CLKCMU_VRA_BUS,
+ CLK_CON_MUX_MUX_CLK_CMU_CMUREF,
+ CLK_CON_MUX_MUX_CMU_CMUREF,
CLK_CON_DIV_CLKCMU_APM_BUS,
CLK_CON_DIV_CLKCMU_AUD_CPU,
CLK_CON_DIV_CLKCMU_BUS0_BUS,
@@ -363,6 +377,7 @@ static const unsigned long top_clk_regs[] __initconst = {
CLK_CON_DIV_CLKCMU_VRA_BUS,
CLK_CON_DIV_DIV_CLKCMU_DPU,
CLK_CON_DIV_DIV_CLKCMU_DPU_ALT,
+ CLK_CON_DIV_DIV_CLK_CMU_CMUREF,
CLK_CON_DIV_PLL_SHARED0_DIV2,
CLK_CON_DIV_PLL_SHARED0_DIV3,
CLK_CON_DIV_PLL_SHARED0_DIV4,
@@ -458,6 +473,8 @@ PNAME(mout_pll_shared3_p) = { "oscclk", "fout_shared3_pll" };
PNAME(mout_pll_shared4_p) = { "oscclk", "fout_shared4_pll" };
PNAME(mout_pll_mmc_p) = { "oscclk", "fout_mmc_pll" };
PNAME(mout_pll_g3d_p) = { "oscclk", "fout_g3d_pll" };
+PNAME(mout_cmu_dpu_bus_p) = { "dout_cmu_dpu",
+ "dout_cmu_dpu_alt" };
PNAME(mout_cmu_apm_bus_p) = { "dout_cmu_shared0_div2",
"dout_cmu_shared2_div2" };
PNAME(mout_cmu_aud_cpu_p) = { "dout_cmu_shared0_div2",
@@ -507,7 +524,7 @@ PNAME(mout_cmu_cpucl0_switch_p) = { "fout_shared4_pll",
"dout_cmu_shared0_div2",
"fout_shared2_pll",
"dout_cmu_shared0_div4" };
-PNAME(mout_cmu_cpucl1_switch_p) = { "fout_shared4_pll",
+PNAME(mout_cmu_cpucl1_switch_p) = { "fout_shared4_pll",
"dout_cmu_shared0_div2",
"fout_shared2_pll",
"dout_cmu_shared0_div4" };
@@ -577,7 +594,7 @@ PNAME(mout_cmu_hsi1_bus_p) = { "dout_cmu_shared0_div3",
"dout_cmu_shared4_div3",
"dout_cmu_shared2_div2",
"fout_mmc_pll", "oscclk", "oscclk" };
-PNAME(mout_cmu_hsi1_mmc_card_p) = { "oscclk", "fout_shared2_pll",
+PNAME(mout_cmu_hsi1_mmc_card_p) = { "oscclk", "fout_shared2_pll",
"fout_mmc_pll",
"dout_cmu_shared0_div4" };
PNAME(mout_cmu_hsi1_pcie_p) = { "oscclk", "fout_shared2_pll" };
@@ -672,6 +689,12 @@ PNAME(mout_cmu_vra_bus_p) = { "dout_cmu_shared0_div3",
"dout_cmu_shared4_div2",
"dout_cmu_shared0_div4",
"dout_cmu_shared4_div3" };
+PNAME(mout_cmu_cmuref_p) = { "oscclk",
+ "dout_cmu_clk_cmuref" };
+PNAME(mout_cmu_clk_cmuref_p) = { "dout_cmu_shared0_div4",
+ "dout_cmu_shared1_div4",
+ "dout_cmu_shared2_div2",
+ "oscclk" };
/*
* Register name to clock name mangling strategy used in this file
@@ -689,19 +712,21 @@ PNAME(mout_cmu_vra_bus_p) = { "dout_cmu_shared0_div3",
static const struct samsung_mux_clock top_mux_clks[] __initconst = {
MUX(CLK_MOUT_PLL_SHARED0, "mout_pll_shared0", mout_pll_shared0_p,
- PLL_CON3_PLL_SHARED0, 4, 1),
+ PLL_CON0_PLL_SHARED0, 4, 1),
MUX(CLK_MOUT_PLL_SHARED1, "mout_pll_shared1", mout_pll_shared1_p,
- PLL_CON3_PLL_SHARED1, 4, 1),
+ PLL_CON0_PLL_SHARED1, 4, 1),
MUX(CLK_MOUT_PLL_SHARED2, "mout_pll_shared2", mout_pll_shared2_p,
- PLL_CON3_PLL_SHARED2, 4, 1),
+ PLL_CON0_PLL_SHARED2, 4, 1),
MUX(CLK_MOUT_PLL_SHARED3, "mout_pll_shared3", mout_pll_shared3_p,
- PLL_CON3_PLL_SHARED3, 4, 1),
+ PLL_CON0_PLL_SHARED3, 4, 1),
MUX(CLK_MOUT_PLL_SHARED4, "mout_pll_shared4", mout_pll_shared4_p,
PLL_CON0_PLL_SHARED4, 4, 1),
MUX(CLK_MOUT_PLL_MMC, "mout_pll_mmc", mout_pll_mmc_p,
PLL_CON0_PLL_MMC, 4, 1),
MUX(CLK_MOUT_PLL_G3D, "mout_pll_g3d", mout_pll_g3d_p,
PLL_CON0_PLL_G3D, 4, 1),
+ MUX(CLK_MOUT_CMU_DPU_BUS, "mout_cmu_dpu_bus",
+ mout_cmu_dpu_bus_p, CLK_CON_MUX_CLKCMU_DPU_BUS, 0, 1),
MUX(CLK_MOUT_CMU_APM_BUS, "mout_cmu_apm_bus",
mout_cmu_apm_bus_p, CLK_CON_MUX_MUX_CLKCMU_APM_BUS, 0, 1),
MUX(CLK_MOUT_CMU_AUD_CPU, "mout_cmu_aud_cpu",
@@ -830,37 +855,13 @@ static const struct samsung_mux_clock top_mux_clks[] __initconst = {
mout_cmu_tnr_bus_p, CLK_CON_MUX_MUX_CLKCMU_TNR_BUS, 0, 3),
MUX(CLK_MOUT_CMU_VRA_BUS, "mout_cmu_vra_bus",
mout_cmu_vra_bus_p, CLK_CON_MUX_MUX_CLKCMU_VRA_BUS, 0, 2),
+ MUX(CLK_MOUT_CMU_CMUREF, "mout_cmu_cmuref",
+ mout_cmu_cmuref_p, CLK_CON_MUX_MUX_CMU_CMUREF, 0, 1),
+ MUX(CLK_MOUT_CMU_CLK_CMUREF, "mout_cmu_clk_cmuref",
+ mout_cmu_clk_cmuref_p, CLK_CON_MUX_MUX_CLK_CMU_CMUREF, 0, 2),
};
static const struct samsung_div_clock top_div_clks[] __initconst = {
- /* SHARED0 region*/
- DIV(CLK_DOUT_CMU_SHARED0_DIV2, "dout_cmu_shared0_div2", "mout_pll_shared0",
- CLK_CON_DIV_PLL_SHARED0_DIV2, 0, 1),
- DIV(CLK_DOUT_CMU_SHARED0_DIV3, "dout_cmu_shared0_div3", "mout_pll_shared0",
- CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2),
- DIV(CLK_DOUT_CMU_SHARED0_DIV4, "dout_cmu_shared0_div4", "dout_cmu_shared0_div2",
- CLK_CON_DIV_PLL_SHARED0_DIV4, 0, 1),
-
- /* SHARED1 region*/
- DIV(CLK_DOUT_CMU_SHARED1_DIV2, "dout_cmu_shared1_div2", "mout_pll_shared1",
- CLK_CON_DIV_PLL_SHARED1_DIV2, 0, 1),
- DIV(CLK_DOUT_CMU_SHARED1_DIV3, "dout_cmu_shared1_div3", "mout_pll_shared1",
- CLK_CON_DIV_PLL_SHARED1_DIV3, 0, 2),
- DIV(CLK_DOUT_CMU_SHARED1_DIV4, "dout_cmu_shared1_div4", "dout_cmu_shared1_div2",
- CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1),
-
- /* SHARED2 region */
- DIV(CLK_DOUT_CMU_SHARED2_DIV2, "dout_cmu_shared2_div2", "mout_pll_shared2",
- CLK_CON_DIV_PLL_SHARED2_DIV2, 0, 1),
-
- /* SHARED4 region*/
- DIV(CLK_DOUT_CMU_SHARED4_DIV2, "dout_cmu_shared4_div2", "mout_pll_shared4",
- CLK_CON_DIV_PLL_SHARED4_DIV2, 0, 1),
- DIV(CLK_DOUT_CMU_SHARED4_DIV3, "dout_cmu_shared4_div3", "mout_pll_shared4",
- CLK_CON_DIV_PLL_SHARED4_DIV3, 0, 2),
- DIV(CLK_DOUT_CMU_SHARED4_DIV4, "dout_cmu_shared4_div4", "mout_pll_shared4",
- CLK_CON_DIV_PLL_SHARED4_DIV4, 0, 1),
-
DIV(CLK_DOUT_CMU_APM_BUS, "dout_cmu_apm_bus", "gout_cmu_apm_bus",
CLK_CON_DIV_CLKCMU_APM_BUS, 0, 2),
DIV(CLK_DOUT_CMU_AUD_CPU, "dout_cmu_aud_cpu", "gout_cmu_aud_cpu",
@@ -974,6 +975,34 @@ static const struct samsung_div_clock top_div_clks[] __initconst = {
CLK_CON_DIV_CLKCMU_VRA_BUS, 0, 4),
DIV(CLK_DOUT_CMU_DPU, "dout_cmu_dpu", "gout_cmu_dpu",
CLK_CON_DIV_DIV_CLKCMU_DPU, 0, 3),
+ DIV(CLK_DOUT_CMU_DPU_ALT, "dout_cmu_dpu_alt", "gout_cmu_dpu_bus",
+ CLK_CON_DIV_DIV_CLKCMU_DPU_ALT, 0, 4),
+ DIV(CLK_DOUT_CMU_CLK_CMUREF, "dout_cmu_clk_cmuref", "mout_cmu_clk_cmuref",
+ CLK_CON_DIV_DIV_CLK_CMU_CMUREF, 0, 2),
+ /* SHARED0 region*/
+ DIV(CLK_DOUT_CMU_SHARED0_DIV2, "dout_cmu_shared0_div2", "mout_pll_shared0",
+ CLK_CON_DIV_PLL_SHARED0_DIV2, 0, 1),
+ DIV(CLK_DOUT_CMU_SHARED0_DIV3, "dout_cmu_shared0_div3", "mout_pll_shared0",
+ CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2),
+ DIV(CLK_DOUT_CMU_SHARED0_DIV4, "dout_cmu_shared0_div4", "dout_cmu_shared0_div2",
+ CLK_CON_DIV_PLL_SHARED0_DIV4, 0, 1),
+ /* SHARED1 region*/
+ DIV(CLK_DOUT_CMU_SHARED1_DIV2, "dout_cmu_shared1_div2", "mout_pll_shared1",
+ CLK_CON_DIV_PLL_SHARED1_DIV2, 0, 1),
+ DIV(CLK_DOUT_CMU_SHARED1_DIV3, "dout_cmu_shared1_div3", "mout_pll_shared1",
+ CLK_CON_DIV_PLL_SHARED1_DIV3, 0, 2),
+ DIV(CLK_DOUT_CMU_SHARED1_DIV4, "dout_cmu_shared1_div4", "dout_cmu_shared1_div2",
+ CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1),
+ /* SHARED2 region */
+ DIV(CLK_DOUT_CMU_SHARED2_DIV2, "dout_cmu_shared2_div2", "mout_pll_shared2",
+ CLK_CON_DIV_PLL_SHARED2_DIV2, 0, 1),
+ /* SHARED4 region*/
+ DIV(CLK_DOUT_CMU_SHARED4_DIV2, "dout_cmu_shared4_div2", "mout_pll_shared4",
+ CLK_CON_DIV_PLL_SHARED4_DIV2, 0, 1),
+ DIV(CLK_DOUT_CMU_SHARED4_DIV3, "dout_cmu_shared4_div3", "mout_pll_shared4",
+ CLK_CON_DIV_PLL_SHARED4_DIV3, 0, 2),
+ DIV(CLK_DOUT_CMU_SHARED4_DIV4, "dout_cmu_shared4_div4", "dout_cmu_shared4_div2",
+ CLK_CON_DIV_PLL_SHARED4_DIV4, 0, 1),
};
static const struct samsung_fixed_factor_clock cmu_top_ffactor[] __initconst = {
--
2.50.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH v4 2/4] dt-bindings: clock: exynos990: Extend clocks IDs
2025-08-25 5:51 ` [PATCH v4 2/4] dt-bindings: clock: exynos990: Extend clocks IDs Denzeel Oliva
@ 2025-08-29 15:26 ` Rob Herring (Arm)
0 siblings, 0 replies; 9+ messages in thread
From: Rob Herring (Arm) @ 2025-08-29 15:26 UTC (permalink / raw)
To: Denzeel Oliva
Cc: linux-clk, Michael Turquette, linux-kernel, Chanwoo Choi,
devicetree, Conor Dooley, Alim Akhtar, Krzysztof Kozlowski,
linux-arm-kernel, Stephen Boyd, linux-samsung-soc,
Sylwester Nawrocki
On Mon, 25 Aug 2025 05:51:16 +0000, Denzeel Oliva wrote:
> Add missing clock definitions for DPU and CMUREF.
>
> Signed-off-by: Denzeel Oliva <wachiturroxd150@gmail.com>
> ---
> include/dt-bindings/clock/samsung,exynos990.h | 4 ++++
> 1 file changed, 4 insertions(+)
>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v4 4/4] clk: samsung: exynos990: Fix PLL mux regs, add DPU/CMUREF
2025-08-25 5:51 ` [PATCH v4 4/4] clk: samsung: exynos990: Fix PLL mux regs, add DPU/CMUREF Denzeel Oliva
@ 2025-08-30 9:16 ` Krzysztof Kozlowski
0 siblings, 0 replies; 9+ messages in thread
From: Krzysztof Kozlowski @ 2025-08-30 9:16 UTC (permalink / raw)
To: Denzeel Oliva, Sylwester Nawrocki, Chanwoo Choi, Alim Akhtar,
Michael Turquette, Stephen Boyd, Rob Herring, Conor Dooley
Cc: linux-samsung-soc, linux-clk, linux-arm-kernel, linux-kernel,
devicetree
On 25/08/2025 07:51, Denzeel Oliva wrote:
> Switch PLL muxes to PLL_CON0 to correct parent selection and
> clock rates. Add DPU_BUS and CMUREF mux/div and their register
> hooks and parents.
>
> Signed-off-by: Denzeel Oliva <wachiturroxd150@gmail.com>
> ---
> drivers/clk/samsung/clk-exynos990.c | 97 ++++++++++++++++++++++++-------------
> 1 file changed, 63 insertions(+), 34 deletions(-)
>
> diff --git a/drivers/clk/samsung/clk-exynos990.c b/drivers/clk/samsung/clk-exynos990.c
> index 9fcdad7cc..d1135708c 100644
> --- a/drivers/clk/samsung/clk-exynos990.c
> +++ b/drivers/clk/samsung/clk-exynos990.c
> @@ -45,6 +45,7 @@
> #define PLL_CON3_PLL_SHARED3 0x024c
> #define PLL_CON0_PLL_SHARED4 0x0280
> #define PLL_CON3_PLL_SHARED4 0x028c
> +#define CLK_CON_MUX_CLKCMU_DPU_BUS 0x1000
> #define CLK_CON_MUX_MUX_CLKCMU_APM_BUS 0x1004
> #define CLK_CON_MUX_MUX_CLKCMU_AUD_CPU 0x1008
> #define CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS 0x100c
> @@ -103,6 +104,8 @@
> #define CLK_CON_MUX_MUX_CLKCMU_SSP_BUS 0x10e0
> #define CLK_CON_MUX_MUX_CLKCMU_TNR_BUS 0x10e4
> #define CLK_CON_MUX_MUX_CLKCMU_VRA_BUS 0x10e8
> +#define CLK_CON_MUX_MUX_CLK_CMU_CMUREF 0x10f0
> +#define CLK_CON_MUX_MUX_CMU_CMUREF 0x10f4
> #define CLK_CON_DIV_CLKCMU_APM_BUS 0x1800
> #define CLK_CON_DIV_CLKCMU_AUD_CPU 0x1804
> #define CLK_CON_DIV_CLKCMU_BUS0_BUS 0x1808
> @@ -162,6 +165,7 @@
> #define CLK_CON_DIV_CLKCMU_VRA_BUS 0x18e0
> #define CLK_CON_DIV_DIV_CLKCMU_DPU 0x18e8
> #define CLK_CON_DIV_DIV_CLKCMU_DPU_ALT 0x18ec
> +#define CLK_CON_DIV_DIV_CLK_CMU_CMUREF 0x18f0
> #define CLK_CON_DIV_PLL_SHARED0_DIV2 0x18f4
> #define CLK_CON_DIV_PLL_SHARED0_DIV3 0x18f8
> #define CLK_CON_DIV_PLL_SHARED0_DIV4 0x18fc
> @@ -239,13 +243,21 @@ static const unsigned long top_clk_regs[] __initconst = {
> PLL_LOCKTIME_PLL_SHARED2,
> PLL_LOCKTIME_PLL_SHARED3,
> PLL_LOCKTIME_PLL_SHARED4,
> + PLL_CON0_PLL_G3D,
> PLL_CON3_PLL_G3D,
> + PLL_CON0_PLL_MMC,
> PLL_CON3_PLL_MMC,
> + PLL_CON0_PLL_SHARED0,
> PLL_CON3_PLL_SHARED0,
> + PLL_CON0_PLL_SHARED1,
> PLL_CON3_PLL_SHARED1,
> + PLL_CON0_PLL_SHARED2,
> PLL_CON3_PLL_SHARED2,
> + PLL_CON0_PLL_SHARED3,
> PLL_CON3_PLL_SHARED3,
> + PLL_CON0_PLL_SHARED4,
> PLL_CON3_PLL_SHARED4,
> + CLK_CON_MUX_CLKCMU_DPU_BUS,
> CLK_CON_MUX_MUX_CLKCMU_APM_BUS,
> CLK_CON_MUX_MUX_CLKCMU_AUD_CPU,
> CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS,
> @@ -304,6 +316,8 @@ static const unsigned long top_clk_regs[] __initconst = {
> CLK_CON_MUX_MUX_CLKCMU_SSP_BUS,
> CLK_CON_MUX_MUX_CLKCMU_TNR_BUS,
> CLK_CON_MUX_MUX_CLKCMU_VRA_BUS,
> + CLK_CON_MUX_MUX_CLK_CMU_CMUREF,
> + CLK_CON_MUX_MUX_CMU_CMUREF,
> CLK_CON_DIV_CLKCMU_APM_BUS,
> CLK_CON_DIV_CLKCMU_AUD_CPU,
> CLK_CON_DIV_CLKCMU_BUS0_BUS,
> @@ -363,6 +377,7 @@ static const unsigned long top_clk_regs[] __initconst = {
> CLK_CON_DIV_CLKCMU_VRA_BUS,
> CLK_CON_DIV_DIV_CLKCMU_DPU,
> CLK_CON_DIV_DIV_CLKCMU_DPU_ALT,
> + CLK_CON_DIV_DIV_CLK_CMU_CMUREF,
> CLK_CON_DIV_PLL_SHARED0_DIV2,
> CLK_CON_DIV_PLL_SHARED0_DIV3,
> CLK_CON_DIV_PLL_SHARED0_DIV4,
> @@ -458,6 +473,8 @@ PNAME(mout_pll_shared3_p) = { "oscclk", "fout_shared3_pll" };
> PNAME(mout_pll_shared4_p) = { "oscclk", "fout_shared4_pll" };
> PNAME(mout_pll_mmc_p) = { "oscclk", "fout_mmc_pll" };
> PNAME(mout_pll_g3d_p) = { "oscclk", "fout_g3d_pll" };
> +PNAME(mout_cmu_dpu_bus_p) = { "dout_cmu_dpu",
> + "dout_cmu_dpu_alt" };
> PNAME(mout_cmu_apm_bus_p) = { "dout_cmu_shared0_div2",
> "dout_cmu_shared2_div2" };
> PNAME(mout_cmu_aud_cpu_p) = { "dout_cmu_shared0_div2",
> @@ -507,7 +524,7 @@ PNAME(mout_cmu_cpucl0_switch_p) = { "fout_shared4_pll",
> "dout_cmu_shared0_div2",
> "fout_shared2_pll",
> "dout_cmu_shared0_div4" };
> -PNAME(mout_cmu_cpucl1_switch_p) = { "fout_shared4_pll",
> +PNAME(mout_cmu_cpucl1_switch_p) = { "fout_shared4_pll",
I don't understand this change.
> "dout_cmu_shared0_div2",
> "fout_shared2_pll",
> "dout_cmu_shared0_div4" };
> @@ -577,7 +594,7 @@ PNAME(mout_cmu_hsi1_bus_p) = { "dout_cmu_shared0_div3",
> "dout_cmu_shared4_div3",
> "dout_cmu_shared2_div2",
> "fout_mmc_pll", "oscclk", "oscclk" };
> -PNAME(mout_cmu_hsi1_mmc_card_p) = { "oscclk", "fout_shared2_pll",
> +PNAME(mout_cmu_hsi1_mmc_card_p) = { "oscclk", "fout_shared2_pll",
Neither this, looks like you changed nothing here.
> "fout_mmc_pll",
> "dout_cmu_shared0_div4" };
> PNAME(mout_cmu_hsi1_pcie_p) = { "oscclk", "fout_shared2_pll" };
> @@ -672,6 +689,12 @@ PNAME(mout_cmu_vra_bus_p) = { "dout_cmu_shared0_div3",
> "dout_cmu_shared4_div2",
> "dout_cmu_shared0_div4",
> "dout_cmu_shared4_div3" };
> +PNAME(mout_cmu_cmuref_p) = { "oscclk",
> + "dout_cmu_clk_cmuref" };
> +PNAME(mout_cmu_clk_cmuref_p) = { "dout_cmu_shared0_div4",
> + "dout_cmu_shared1_div4",
> + "dout_cmu_shared2_div2",
> + "oscclk" };
>
> /*
> * Register name to clock name mangling strategy used in this file
> @@ -689,19 +712,21 @@ PNAME(mout_cmu_vra_bus_p) = { "dout_cmu_shared0_div3",
>
> static const struct samsung_mux_clock top_mux_clks[] __initconst = {
> MUX(CLK_MOUT_PLL_SHARED0, "mout_pll_shared0", mout_pll_shared0_p,
> - PLL_CON3_PLL_SHARED0, 4, 1),
> + PLL_CON0_PLL_SHARED0, 4, 1),
> MUX(CLK_MOUT_PLL_SHARED1, "mout_pll_shared1", mout_pll_shared1_p,
> - PLL_CON3_PLL_SHARED1, 4, 1),
> + PLL_CON0_PLL_SHARED1, 4, 1),
> MUX(CLK_MOUT_PLL_SHARED2, "mout_pll_shared2", mout_pll_shared2_p,
> - PLL_CON3_PLL_SHARED2, 4, 1),
> + PLL_CON0_PLL_SHARED2, 4, 1),
> MUX(CLK_MOUT_PLL_SHARED3, "mout_pll_shared3", mout_pll_shared3_p,
> - PLL_CON3_PLL_SHARED3, 4, 1),
> + PLL_CON0_PLL_SHARED3, 4, 1),
This looks like fix, so shuold be sent separately with Fixes tag.
> MUX(CLK_MOUT_PLL_SHARED4, "mout_pll_shared4", mout_pll_shared4_p,
> PLL_CON0_PLL_SHARED4, 4, 1),
> MUX(CLK_MOUT_PLL_MMC, "mout_pll_mmc", mout_pll_mmc_p,
> PLL_CON0_PLL_MMC, 4, 1),
> MUX(CLK_MOUT_PLL_G3D, "mout_pll_g3d", mout_pll_g3d_p,
> PLL_CON0_PLL_G3D, 4, 1),
> + MUX(CLK_MOUT_CMU_DPU_BUS, "mout_cmu_dpu_bus",
> + mout_cmu_dpu_bus_p, CLK_CON_MUX_CLKCMU_DPU_BUS, 0, 1),
> MUX(CLK_MOUT_CMU_APM_BUS, "mout_cmu_apm_bus",
> mout_cmu_apm_bus_p, CLK_CON_MUX_MUX_CLKCMU_APM_BUS, 0, 1),
> MUX(CLK_MOUT_CMU_AUD_CPU, "mout_cmu_aud_cpu",
> @@ -830,37 +855,13 @@ static const struct samsung_mux_clock top_mux_clks[] __initconst = {
> mout_cmu_tnr_bus_p, CLK_CON_MUX_MUX_CLKCMU_TNR_BUS, 0, 3),
> MUX(CLK_MOUT_CMU_VRA_BUS, "mout_cmu_vra_bus",
> mout_cmu_vra_bus_p, CLK_CON_MUX_MUX_CLKCMU_VRA_BUS, 0, 2),
> + MUX(CLK_MOUT_CMU_CMUREF, "mout_cmu_cmuref",
> + mout_cmu_cmuref_p, CLK_CON_MUX_MUX_CMU_CMUREF, 0, 1),
> + MUX(CLK_MOUT_CMU_CLK_CMUREF, "mout_cmu_clk_cmuref",
> + mout_cmu_clk_cmuref_p, CLK_CON_MUX_MUX_CLK_CMU_CMUREF, 0, 2),
> };
>
> static const struct samsung_div_clock top_div_clks[] __initconst = {
> - /* SHARED0 region*/
> - DIV(CLK_DOUT_CMU_SHARED0_DIV2, "dout_cmu_shared0_div2", "mout_pll_shared0",
> - CLK_CON_DIV_PLL_SHARED0_DIV2, 0, 1),
> - DIV(CLK_DOUT_CMU_SHARED0_DIV3, "dout_cmu_shared0_div3", "mout_pll_shared0",
> - CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2),
> - DIV(CLK_DOUT_CMU_SHARED0_DIV4, "dout_cmu_shared0_div4", "dout_cmu_shared0_div2",
> - CLK_CON_DIV_PLL_SHARED0_DIV4, 0, 1),
And this is not really explained in the commit msg.
> -
> - /* SHARED1 region*/
> - DIV(CLK_DOUT_CMU_SHARED1_DIV2, "dout_cmu_shared1_div2", "mout_pll_shared1",
> - CLK_CON_DIV_PLL_SHARED1_DIV2, 0, 1),
> - DIV(CLK_DOUT_CMU_SHARED1_DIV3, "dout_cmu_shared1_div3", "mout_pll_shared1",
> - CLK_CON_DIV_PLL_SHARED1_DIV3, 0, 2),
> - DIV(CLK_DOUT_CMU_SHARED1_DIV4, "dout_cmu_shared1_div4", "dout_cmu_shared1_div2",
> - CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1),
> -
> - /* SHARED2 region */
> - DIV(CLK_DOUT_CMU_SHARED2_DIV2, "dout_cmu_shared2_div2", "mout_pll_shared2",
> - CLK_CON_DIV_PLL_SHARED2_DIV2, 0, 1),
> -
> - /* SHARED4 region*/
> - DIV(CLK_DOUT_CMU_SHARED4_DIV2, "dout_cmu_shared4_div2", "mout_pll_shared4",
> - CLK_CON_DIV_PLL_SHARED4_DIV2, 0, 1),
> - DIV(CLK_DOUT_CMU_SHARED4_DIV3, "dout_cmu_shared4_div3", "mout_pll_shared4",
> - CLK_CON_DIV_PLL_SHARED4_DIV3, 0, 2),
> - DIV(CLK_DOUT_CMU_SHARED4_DIV4, "dout_cmu_shared4_div4", "mout_pll_shared4",
> - CLK_CON_DIV_PLL_SHARED4_DIV4, 0, 1),
> -
> DIV(CLK_DOUT_CMU_APM_BUS, "dout_cmu_apm_bus", "gout_cmu_apm_bus",
> CLK_CON_DIV_CLKCMU_APM_BUS, 0, 2),
> DIV(CLK_DOUT_CMU_AUD_CPU, "dout_cmu_aud_cpu", "gout_cmu_aud_cpu",
> @@ -974,6 +975,34 @@ static const struct samsung_div_clock top_div_clks[] __initconst = {
> CLK_CON_DIV_CLKCMU_VRA_BUS, 0, 4),
> DIV(CLK_DOUT_CMU_DPU, "dout_cmu_dpu", "gout_cmu_dpu",
> CLK_CON_DIV_DIV_CLKCMU_DPU, 0, 3),
> + DIV(CLK_DOUT_CMU_DPU_ALT, "dout_cmu_dpu_alt", "gout_cmu_dpu_bus",
> + CLK_CON_DIV_DIV_CLKCMU_DPU_ALT, 0, 4),
> + DIV(CLK_DOUT_CMU_CLK_CMUREF, "dout_cmu_clk_cmuref", "mout_cmu_clk_cmuref",
> + CLK_CON_DIV_DIV_CLK_CMU_CMUREF, 0, 2),
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v4 1/4] clk: samsung: exynos990: Fix CMU TOP mux/div widths and add fixed-factors
2025-08-25 5:51 ` [PATCH v4 1/4] clk: samsung: exynos990: Fix CMU TOP mux/div widths and add fixed-factors Denzeel Oliva
@ 2025-08-30 9:17 ` Krzysztof Kozlowski
0 siblings, 0 replies; 9+ messages in thread
From: Krzysztof Kozlowski @ 2025-08-30 9:17 UTC (permalink / raw)
To: Denzeel Oliva, Sylwester Nawrocki, Chanwoo Choi, Alim Akhtar,
Michael Turquette, Stephen Boyd, Rob Herring, Conor Dooley
Cc: linux-samsung-soc, linux-clk, linux-arm-kernel, linux-kernel,
devicetree
On 25/08/2025 07:51, Denzeel Oliva wrote:
> Correct mux/div bit widths in CMU TOP (DPU, DSP_BUS, G2D_MSCL,
> HSI0/1/2). Replace wrong divs with fixed-factor clocks for
Separate commits.
> HSI1/2 PCIe and USBDP debug. Also add OTP rate in ffactor.
> These align with Exynos990 downstream cmucal and ensure correct
> parent/rate selection.
Fixes tags.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v4 3/4] clk: samsung: exynos990: update CLK_NR_TOP for new IDs clocks
2025-08-25 5:51 ` [PATCH v4 3/4] clk: samsung: exynos990: update CLK_NR_TOP for new IDs clocks Denzeel Oliva
@ 2025-08-30 9:18 ` Krzysztof Kozlowski
0 siblings, 0 replies; 9+ messages in thread
From: Krzysztof Kozlowski @ 2025-08-30 9:18 UTC (permalink / raw)
To: Denzeel Oliva, Sylwester Nawrocki, Chanwoo Choi, Alim Akhtar,
Michael Turquette, Stephen Boyd, Rob Herring, Conor Dooley
Cc: linux-samsung-soc, linux-clk, linux-arm-kernel, linux-kernel,
devicetree
On 25/08/2025 07:51, Denzeel Oliva wrote:
> The new clock IDs have been added and put last,
> it is necessary to change.
>
> Signed-off-by: Denzeel Oliva <wachiturroxd150@gmail.com>
> ---
> drivers/clk/samsung/clk-exynos990.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/clk/samsung/clk-exynos990.c b/drivers/clk/samsung/clk-exynos990.c
> index 105ba0363..9fcdad7cc 100644
> --- a/drivers/clk/samsung/clk-exynos990.c
> +++ b/drivers/clk/samsung/clk-exynos990.c
> @@ -17,7 +17,7 @@
> #include "clk-pll.h"
>
> /* NOTE: Must be equal to the last clock ID increased by one */
> -#define CLKS_NR_TOP (CLK_GOUT_CMU_VRA_BUS + 1)
> +#define CLKS_NR_TOP (CLK_DOUT_CMU_CLK_CMUREF + 1)
This belongs to the driver patch introducing these new clocks. Such
change alone makes no sense or commit msg really does not explain issue
being fixed here.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2025-08-30 9:18 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-08-25 5:51 [PATCH v4 0/4] clk: samsung: exynos990: CMU_TOP fixes (mux regs, widths, factors) Denzeel Oliva
2025-08-25 5:51 ` [PATCH v4 1/4] clk: samsung: exynos990: Fix CMU TOP mux/div widths and add fixed-factors Denzeel Oliva
2025-08-30 9:17 ` Krzysztof Kozlowski
2025-08-25 5:51 ` [PATCH v4 2/4] dt-bindings: clock: exynos990: Extend clocks IDs Denzeel Oliva
2025-08-29 15:26 ` Rob Herring (Arm)
2025-08-25 5:51 ` [PATCH v4 3/4] clk: samsung: exynos990: update CLK_NR_TOP for new IDs clocks Denzeel Oliva
2025-08-30 9:18 ` Krzysztof Kozlowski
2025-08-25 5:51 ` [PATCH v4 4/4] clk: samsung: exynos990: Fix PLL mux regs, add DPU/CMUREF Denzeel Oliva
2025-08-30 9:16 ` Krzysztof Kozlowski
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