Re: Re: [PATCH v9 2/3] clock: eswin: Add eic7700 clock driver

["Xuyang Dong" <dongxuyang@eswincomputing.com>]

> > +
> > +/* divider clocks */
> > +static struct eswin_divider_clock eic7700_div_clks[] = {
> > +	EIC7700_DIV(EIC7700_CLK_DIV_SYS_CFG_DYNM, "divider_sys_cfg_div_dynm",
> > +		    "fixed_rate_clk_spll0_fout3", 0,
> > +		    EIC7700_REG_OFFSET_SYSCFG_CTRL, 4, 3,
> > +		    CLK_DIVIDER_ONE_BASED),
> > +	EIC7700_DIV(EIC7700_CLK_DIV_NOC_NSP_DYNM, "divider_noc_nsp_div_dynm",
> > +		    "fixed_rate_clk_spll2_fout1", 0,
> > +		    EIC7700_REG_OFFSET_NOC_CTRL, 0, 3, CLK_DIVIDER_ONE_BASED),
> > +	EIC7700_DIV(EIC7700_CLK_DIV_BOOTSPI_DYNM, "divider_bootspi_div_dynm",
> > +		    "gate_clk_spll0_fout2", 0, EIC7700_REG_OFFSET_BOOTSPI_CTRL,
> > +		    4, 6, CLK_DIVIDER_ONE_BASED),
> > +	EIC7700_DIV(EIC7700_CLK_DIV_SCPU_CORE_DYNM,
> > +		    "divider_scpu_core_div_dynm", "fixed_rate_clk_spll0_fout1",
> > +		    0, EIC7700_REG_OFFSET_SCPU_CORE_CTRL, 4, 4,
> > +		    CLK_DIVIDER_ONE_BASED),
> > +	EIC7700_DIV(EIC7700_CLK_DIV_LPCPU_CORE_DYNM,
> > +		    "divider_lpcpu_core_div_dynm", "fixed_rate_clk_spll0_fout1",
> > +		    0, EIC7700_REG_OFFSET_LPCPU_CORE_CTRL, 4, 4,
> > +		    CLK_DIVIDER_ONE_BASED),
> 
> During testing on top of next-20251219 I got the following:
> 
> [    0.126102] divider_lpcpu_core_div_dynm: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set
> [    0.126194] WARNING: drivers/clk/clk-divider.c:145 at divider_recalc_rate+0x8a/0x9c, CPU#0: swapper/0/1
> 
> Therefore I suggest for above line needing to be:
> 
> +                   CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO),

Hi Marcel,

Thank you! This is indeed a bug and will be fixed in the next version. 
Could you please share the detailed testing methods with me so that I 
can reproduce this issue on my side?

Best regards,
Xuyang Dong