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Wed, 02 Jul 2025 08:43:25 +0000 (GMT) Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 5628hOmg031410 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 2 Jul 2025 08:43:24 GMT Received: from [10.217.217.109] (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Wed, 2 Jul 2025 01:43:19 -0700 Message-ID: <4884d189-e43a-4932-af52-e1987bd7106c@quicinc.com> Date: Wed, 2 Jul 2025 14:13:14 +0530 Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v10 01/10] clk: qcom: clk-alpha-pll: Add support for dynamic update for slewing PLLs To: Dmitry Baryshkov CC: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , "Catalin Marinas" , Will Deacon , Ajit Pandey , Imran Shaik , "Jagadeesh Kona" , , , , , References: <20250625-qcs615-mm-v10-clock-controllers-v10-0-ec48255f90d8@quicinc.com> <20250625-qcs615-mm-v10-clock-controllers-v10-1-ec48255f90d8@quicinc.com> <44dddd3f-d2d2-4d4b-831a-21e6d9050445@quicinc.com> <667ac51f-d19d-4832-9aa6-97d9a86e0068@oss.qualcomm.com> Content-Language: en-US From: Taniya Das In-Reply-To: <667ac51f-d19d-4832-9aa6-97d9a86e0068@oss.qualcomm.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzAyMDA2OSBTYWx0ZWRfX8VcgtUhyolYE VzR1RXp2VdwzTnrCopUKekm8qLZdpBh04QtuOXo8dJbDQSw6Xdzy5vJXf0uwXBd0gE1aa6GsjHo Eq+UP46sNtfjAeq0r6rmQR+hFAGW8QHhIQPsFG02d9wVQjZEnsWHUlimx8kgUQDz2Tx5T08bBWz uNuIKtPGXHKOL3uraFUOsUTvmz3poHoZ/yUzl+H9asmRwnfqfQeWF1I+IZP50hIQ6VxFYyaAR5E wHEV9PYb8SU80DNxm+H//JlkA2n8jatGeYH2Ki3+D62sWbv1C1iLh3PLNmC2LKwriw7ZwchtZJ3 akOnR5a/x4eHFOkcnUDFkP2mUp9EVM0qKDSMkb2FV4YNUnZBDbCmxJ22apKKaBEJCiPm6e8Oyip 1H+wf4BEMLPTPrqbZXcRldcfRexN0Anbj//UTVeDhHD33hH2BmEQxNhIAj9P1m0NaToa5yMR X-Authority-Analysis: v=2.4 cv=EbvIQOmC c=1 sm=1 tr=0 ts=6864f12d cx=c_pps a=JYp8KDb2vCoCEuGobkYCKw==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=GEpy-HfZoHoA:10 a=IkcTkHD0fZMA:10 a=Wb1JkmetP80A:10 a=COk6AnOGAAAA:8 a=O75FsbJ6qr0OxAJT8SUA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: z_qDogjY66KuJUuri63Fz3YxX51oqibx X-Proofpoint-GUID: z_qDogjY66KuJUuri63Fz3YxX51oqibx X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.7,FMLib:17.12.80.40 definitions=2025-07-02_01,2025-06-27_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 mlxscore=0 priorityscore=1501 mlxlogscore=999 lowpriorityscore=0 malwarescore=0 adultscore=0 clxscore=1015 bulkscore=0 impostorscore=0 spamscore=0 suspectscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507020069 On 6/27/2025 6:07 PM, Dmitry Baryshkov wrote: > On 27/06/2025 13:13, Taniya Das wrote: >> >> >> On 6/25/2025 5:17 PM, Dmitry Baryshkov wrote: >>> On Wed, Jun 25, 2025 at 04:13:26PM +0530, Taniya Das wrote: >>>> The alpha PLLs which slew to a new frequency at runtime would require >>>> the PLL to calibrate at the mid point of the VCO. Add the new PLL ops >>>> which can support the slewing of the PLL to a new frequency. >>>> >>>> Reviewed-by: Imran Shaik >>>> Signed-off-by: Taniya Das >>>> --- >>>>   drivers/clk/qcom/clk-alpha-pll.c | 169 +++++++++++++++++++++++++++ >>>> ++++++++++++ >>>>   drivers/clk/qcom/clk-alpha-pll.h |   1 + >>>>   2 files changed, 170 insertions(+) >>>> >> >>>> +    /* >>>> +     * Dynamic pll update will not support switching frequencies >>>> across >>>> +     * vco ranges. In those cases fall back to normal alpha set rate. >>>> +     */ >>>> +    if (curr_vco->val != vco->val) >>>> +        return clk_alpha_pll_set_rate(hw, rate, parent_rate); >>>> + >>>> +    a <<= ALPHA_REG_BITWIDTH - ALPHA_BITWIDTH; >>>> + >>>> +    regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); >>>> +    regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), >>>> lower_32_bits(a)); >>>> +    regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), >>>> upper_32_bits(a)); >>> >>> We have code that does this in __clk_alpha_pll_set_rate() and now you >>> are adding two more copies. Please extract PLL_L_VAL, PLL_ALPHA_VAL and >>> PLL_USER_CTL / PLL_VCO_MASK into a helper function. >>> >> >> Dmitry, I was thinking of implementing the following as a reusable >> helper since it can be leveraged by most of the functions. I'd >> appreciate your suggestions or feedback. > > The code below looks good to me. Please use 'alpha' instead of 'a'. Thanks, I will use 'alpha' in the next patch. Taniya