Linux clock framework development
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From: Krzysztof Kozlowski <krzk@kernel.org>
To: Clement LE GOFFIC <clement.legoffic@foss.st.com>,
	Will Deacon <will@kernel.org>,
	Mark Rutland <mark.rutland@arm.com>,
	Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Maxime Coquelin <mcoquelin.stm32@gmail.com>,
	Alexandre Torgue <alexandre.torgue@foss.st.com>,
	Philipp Zabel <p.zabel@pengutronix.de>,
	Jonathan Corbet <corbet@lwn.net>,
	Gatien Chevallier <gatien.chevallier@foss.st.com>,
	Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>,
	Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Cc: linux-arm-kernel@lists.infradead.org,
	linux-perf-users@vger.kernel.org, devicetree@vger.kernel.org,
	linux-stm32@st-md-mailman.stormreply.com,
	linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org,
	linux-clk@vger.kernel.org
Subject: Re: [PATCH 06/13] perf: stm32: introduce DDRPERFM driver
Date: Wed, 25 Jun 2025 08:35:06 +0200	[thread overview]
Message-ID: <49483568-b287-45ca-a66c-1e0ad0490225@kernel.org> (raw)
In-Reply-To: <5044c733-8836-43bd-85d7-0f552b000fb1@foss.st.com>

On 24/06/2025 12:43, Clement LE GOFFIC wrote:
> On 6/23/25 11:45, Krzysztof Kozlowski wrote:
> [...]
> 
> Hi Krzysztof,
> 
> Sorry I forgot to address comments below.
> 
>>> +
>>> +static const struct stm32_ddr_pmu_cfg stm32_ddr_pmu_cfg_mp1 = {
>>> +	.regs = &stm32_ddr_pmu_regspec_mp1,
>>> +	.attribute = stm32_ddr_pmu_attr_groups_mp1,
>>> +	.counters_nb = MP1_CNT_NB,
>>> +	.evt_counters_nb = MP1_CNT_NB - 1, /* Time counter is not an event counter */
>>> +	.time_cnt_idx = MP1_TIME_CNT_IDX,
>>> +	.get_counter = stm32_ddr_pmu_get_event_counter_mp1,
>>> +};
>>> +
>>> +static const struct stm32_ddr_pmu_cfg stm32_ddr_pmu_cfg_mp2 = {
>>> +	.regs = &stm32_ddr_pmu_regspec_mp2,
>>> +	.attribute = stm32_ddr_pmu_attr_groups_mp2,
>>> +	.counters_nb = MP2_CNT_NB,
>>> +	.evt_counters_nb = MP2_CNT_NB - 1, /* Time counter is an event counter */
>>> +	.time_cnt_idx = MP2_TIME_CNT_IDX,
>>> +	.get_counter = stm32_ddr_pmu_get_event_counter_mp2,
>>> +};
>>> +
>>> +static const struct dev_pm_ops stm32_ddr_pmu_pm_ops = {
>>> +	SET_SYSTEM_SLEEP_PM_OPS(NULL, stm32_ddr_pmu_device_resume)
>>> +};
>>> +
>>> +static const struct of_device_id stm32_ddr_pmu_of_match[] = {
>>> +	{
>>> +		.compatible = "st,stm32mp131-ddr-pmu",
>>> +		.data = &stm32_ddr_pmu_cfg_mp1
>>> +	},
>>> +	{
>>> +		.compatible = "st,stm32mp151-ddr-pmu",
>>> +		.data = &stm32_ddr_pmu_cfg_mp1
>>
>> So devices are compatible, thus express it correctly and drop this.
> 
> Ok so I assume this comes with your comment in the bindings and 
> basically don't get you point here.
> Can you please be more precise ?

Express compatibility in the bindings, like 90% of SoCs are doing, so
with proper fallback and drop this entry in the table. My comment was
pretty precise, because this is completely standard pattern, also used
already in stm32.

Best regards,
Krzysztof

  reply	other threads:[~2025-06-25  6:35 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-06-23  9:27 [PATCH 00/13] Introduce STM32 DDR PMU for STM32MP platforms Clément Le Goffic
2025-06-23  9:27 ` [PATCH 01/13] bus: firewall: move stm32_firewall header file in include folder Clément Le Goffic
2025-06-23  9:27 ` [PATCH 02/13] dt-bindings: stm32: stm32mp25: add `access-controller-cell` property Clément Le Goffic
2025-06-23 10:32   ` Rob Herring (Arm)
2025-06-23  9:27 ` [PATCH 03/13] clk: stm32mp25: add firewall grant_access ops Clément Le Goffic
2025-06-23  9:27 ` [PATCH 04/13] arm64: dts: st: set rcc as an access-controller Clément Le Goffic
2025-06-23  9:27 ` [PATCH 05/13] dt-bindings: perf: stm32: introduce DDRPERFM dt-bindings Clément Le Goffic
2025-06-23  9:48   ` Krzysztof Kozlowski
2025-06-23 15:00     ` Clement LE GOFFIC
2025-06-23  9:27 ` [PATCH 06/13] perf: stm32: introduce DDRPERFM driver Clément Le Goffic
2025-06-23  9:45   ` Krzysztof Kozlowski
2025-06-23 15:02     ` Clement LE GOFFIC
2025-06-24 10:43     ` Clement LE GOFFIC
2025-06-25  6:35       ` Krzysztof Kozlowski [this message]
2025-06-25  8:33         ` Clement LE GOFFIC
2025-06-25  8:48           ` Krzysztof Kozlowski
2025-06-25  9:09             ` Clement LE GOFFIC
2025-06-23 20:43   ` kernel test robot
2025-06-26 23:52   ` kernel test robot
2025-06-30  8:38   ` Philipp Zabel
2025-07-02 14:13     ` Clement LE GOFFIC
2025-06-23  9:27 ` [PATCH 07/13] Documentation: perf: stm32: add ddrperfm support Clément Le Goffic
2025-06-23  9:27 ` [PATCH 08/13] MAINTAINERS: add myself as STM32 DDR PMU maintainer Clément Le Goffic
2025-06-23  9:27 ` [PATCH 09/13] ARM: dts: stm32: add ddrperfm on stm32mp131 Clément Le Goffic
2025-06-23  9:27 ` [PATCH 10/13] ARM: dts: stm32: add ddrperfm on stm32mp151 Clément Le Goffic
2025-06-23  9:27 ` [PATCH 11/13] arm64: dts: st: add ddrperfm on stm32mp251 Clément Le Goffic
2025-06-23  9:27 ` [PATCH 12/13] arm64: dts: st: support ddrperfm on stm32mp257f-dk Clément Le Goffic
2025-06-23  9:27 ` [PATCH 13/13] arm64: dts: st: support ddrperfm on stm32mp257f-ev1 Clément Le Goffic

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